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synced 2026-03-14 23:09:45 +01:00
realtek: eth: refactor transmit function
Provide a new transmit function. It is cleaner and closer to upstream than what we have now. The basic features are: - Avoid memory moving and keep data in the SKBs - Only protect really critcal parts by a lock as transmit queues will be only called once by the kernel Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/21778 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Markus Stockhausen
Robert Marko
parent
1b2f8975f7
commit
41300fd88a
2 changed files with 94 additions and 90 deletions
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@ -114,7 +114,7 @@ struct notify_b {
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u32 reserved2[8];
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};
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static void rteth_838x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
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static void rteth_838x_create_tx_header(struct rteth_packet *h, unsigned int dest_port, int prio)
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{
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/* cpu_tag[0] is reserved on the RTL83XX SoCs */
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h->cpu_tag[1] = 0x0400; /* BIT 10: RTL8380_CPU_TAG */
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@ -128,7 +128,7 @@ static void rteth_838x_create_tx_header(struct p_hdr *h, unsigned int dest_port,
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h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 12;
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}
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static void rteth_839x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
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static void rteth_839x_create_tx_header(struct rteth_packet *h, unsigned int dest_port, int prio)
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{
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/* cpu_tag[0] is reserved on the RTL83XX SoCs */
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h->cpu_tag[1] = 0x0100; /* RTL8390_CPU_TAG marker */
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@ -149,7 +149,7 @@ static void rteth_839x_create_tx_header(struct p_hdr *h, unsigned int dest_port,
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h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 8;
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}
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static void rteth_930x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
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static void rteth_930x_create_tx_header(struct rteth_packet *h, unsigned int dest_port, int prio)
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{
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h->cpu_tag[0] = 0x8000; /* CPU tag marker */
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@ -168,7 +168,7 @@ static void rteth_930x_create_tx_header(struct p_hdr *h, unsigned int dest_port,
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h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8;
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}
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static void rteth_931x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
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static void rteth_931x_create_tx_header(struct rteth_packet *h, unsigned int dest_port, int prio)
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{
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h->cpu_tag[0] = 0x8000; /* CPU tag marker */
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@ -557,8 +557,10 @@ static void rteth_hw_ring_setup(struct rteth_ctrl *ctrl)
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for (int i = 0; i < ctrl->rxrings; i++)
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sw_w32(KSEG1ADDR(&ring->rx_r[i]), ctrl->r->dma_rx_base + i * 4);
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for (int i = 0; i < TXRINGS; i++)
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sw_w32(KSEG1ADDR(&ring->tx_r[i]), ctrl->r->dma_tx_base + i * 4);
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for (int r = 0; r < RTETH_TX_RINGS; r++)
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sw_w32(ctrl->tx_dma +
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r * sizeof(struct rteth_tx) + offsetof(struct rteth_tx, ring),
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ctrl->r->dma_tx_base + r * 4);
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}
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static void rtl838x_hw_en_rxtx(struct rteth_ctrl *ctrl)
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@ -967,100 +969,102 @@ static void rteth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
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spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static int rteth_start_xmit(struct sk_buff *skb, struct net_device *dev)
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static int rteth_start_xmit(struct sk_buff *skb, struct net_device *netdev)
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{
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int len;
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struct rteth_ctrl *ctrl = netdev_priv(dev);
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struct ring_b *ring = ctrl->membase;
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int ret;
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unsigned long flags;
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struct p_hdr *h;
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int dest_port = -1;
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int q = skb_get_queue_mapping(skb) % TXRINGS;
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struct rteth_ctrl *ctrl = netdev_priv(netdev);
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int slot, len = skb->len, dest_port = -1;
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int ring = skb_get_queue_mapping(skb);
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struct device *dev = &ctrl->pdev->dev;
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struct rteth_packet *packet;
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dma_addr_t packet_dma;
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if (q) /* Check for high prio queue */
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pr_debug("SKB priority: %d\n", skb->priority);
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spin_lock_irqsave(&ctrl->lock, flags);
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len = skb->len;
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/* Check for DSA tagging at the end of the buffer */
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if (netdev_uses_dsa(dev) &&
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if (netdev_uses_dsa(netdev) &&
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skb->data[len - 4] == 0x80 &&
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skb->data[len - 3] < ctrl->r->cpu_port &&
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skb->data[len - 2] == 0x10 &&
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skb->data[len - 1] == 0x00) {
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/* Reuse tag space for CRC if possible */
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/* DSA tag, reuse space for CRC */
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dest_port = skb->data[len - 3];
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skb->data[len - 4] = skb->data[len - 3] = skb->data[len - 2] = skb->data[len - 1] = 0x00;
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len -= 4;
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}
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len += 4; /* Add space for CRC */
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if (skb_padto(skb, len)) {
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ret = NETDEV_TX_OK;
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goto txdone;
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}
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/* We can send this packet if CPU owns the descriptor */
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if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {
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/* Set descriptor for tx */
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h = &ring->tx_header[q][ring->c_tx[q]];
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h->size = len;
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h->len = len;
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/* On RTL8380 SoCs, small packet lengths being sent need adjustments */
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if (ctrl->r->family_id == RTL8380_FAMILY_ID) {
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if (len < ETH_ZLEN - 4)
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h->len -= 4;
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}
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if (dest_port >= 0)
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ctrl->r->create_tx_header(h, dest_port, skb->priority >> 1);
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/* Copy packet data to tx buffer */
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memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
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/* Make sure packet data is visible to ASIC */
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wmb();
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/* Hand over to switch */
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ring->tx_r[q][ring->c_tx[q]] |= 1;
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/* Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs */
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if (ctrl->r->family_id == RTL8380_FAMILY_ID) {
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for (int i = 0; i < 10; i++) {
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u32 val = sw_r32(ctrl->r->dma_if_ctrl);
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if ((val & 0xc) == 0xc)
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break;
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}
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}
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/* Tell switch to send data */
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if (ctrl->r->family_id == RTL9310_FAMILY_ID || ctrl->r->family_id == RTL9300_FAMILY_ID) {
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/* Ring ID q == 0: Low priority, Ring ID = 1: High prio queue */
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if (!q)
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sw_w32_mask(0, BIT(2), ctrl->r->dma_if_ctrl);
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else
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sw_w32_mask(0, BIT(3), ctrl->r->dma_if_ctrl);
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} else {
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sw_w32_mask(0, TX_DO, ctrl->r->dma_if_ctrl);
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}
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dev->stats.tx_packets++;
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dev->stats.tx_bytes += len;
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dev_kfree_skb(skb);
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ring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN;
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ret = NETDEV_TX_OK;
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skb->data[len - 4] = skb->data[len - 3] = 0;
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skb->data[len - 2] = skb->data[len - 1] = 0;
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} else {
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dev_warn(&ctrl->pdev->dev, "Data is owned by switch\n");
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ret = NETDEV_TX_BUSY;
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/* No DSA tag, add space for CRC */
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len += 4;
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}
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txdone:
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spin_unlock_irqrestore(&ctrl->lock, flags);
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if (unlikely(skb_padto(skb, len))) {
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netdev->stats.tx_errors++;
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dev_warn(dev, "skb pad failed\n");
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return ret;
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return NETDEV_TX_OK;
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}
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slot = ctrl->tx_data[ring].slot;
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packet = &ctrl->tx_data[ring].packet[slot];
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packet_dma = ctrl->tx_data[ring].ring[slot];
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if (unlikely(packet_dma & RTETH_OWN_CPU)) {
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netif_stop_subqueue(netdev, ring);
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if (net_ratelimit())
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dev_warn(dev, "tx ring %d busy, waiting for slot %d\n", ring, slot);
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return NETDEV_TX_BUSY;
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}
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packet->dma = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(dev, packet->dma))) {
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dev_kfree_skb_any(skb);
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netdev->stats.tx_errors++;
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return NETDEV_TX_OK;
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}
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if (likely(packet->skb)) {
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/* cleanup old data of this slot */
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dma_unmap_single(dev, packet->dma, packet->skb->len, DMA_TO_DEVICE);
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dev_kfree_skb_any(packet->skb);
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}
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if (ctrl->r->family_id == RTL8380_FAMILY_ID) {
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/* On RTL8380 SoCs, small packet lengths being sent need adjustments */
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if (len < ETH_ZLEN - 4)
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len -= 4;
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}
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if (dest_port >= 0)
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ctrl->r->create_tx_header(packet, dest_port, 0); // TODO ok to set prio to 0?
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/* Transfer data and hand packet over to switch */
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packet->len = len;
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packet->skb = skb;
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dma_wmb();
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ctrl->tx_data[ring].ring[slot] = packet_dma | RTETH_OWN_CPU;
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ctrl->tx_data[ring].slot = (slot + 1) % RTETH_TX_RING_SIZE;
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wmb();
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spin_lock(&ctrl->tx_lock);
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/* Before starting TX, prevent a Lexra bus bug on RTL8380 SoCs */
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if (ctrl->r->family_id == RTL8380_FAMILY_ID) {
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for (int i = 0; i < 10; i++) {
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u32 val = sw_r32(ctrl->r->dma_if_ctrl);
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if ((val & 0xc) == 0xc)
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break;
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}
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}
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/* Tell switch to send data */
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if (ctrl->r->family_id == RTL9310_FAMILY_ID || ctrl->r->family_id == RTL9300_FAMILY_ID)
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sw_w32_mask(0, BIT(2 + ring), ctrl->r->dma_if_ctrl);
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else
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sw_w32_mask(0, TX_DO, ctrl->r->dma_if_ctrl);
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netdev->stats.tx_packets++;
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netdev->stats.tx_bytes += len;
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spin_unlock(&ctrl->tx_lock);
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return NETDEV_TX_OK;
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}
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static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
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@ -435,7 +435,7 @@ struct rteth_config {
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u32 (*get_mac_tx_pause_sts)(int port);
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int mac;
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int l2_tbl_flush_ctrl;
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void (*create_tx_header)(struct p_hdr *h, unsigned int dest_port, int prio);
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void (*create_tx_header)(struct rteth_packet *h, unsigned int dest_port, int prio);
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bool (*decode_tag)(struct p_hdr *h, struct dsa_tag *tag);
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void (*hw_reset)(struct rteth_ctrl *ctrl);
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int (*init_mac)(struct rteth_ctrl *ctrl);
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