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airoha: backport upstream fixes for pinctrl PHY LED and MDIO
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Backport fixes for Airoha pinctrl driver for PHY LED and MDIO bus. This fix a copy-paste error for PHY LED and a misconfiguration for MT7530 embedded Switch MDIO bus GPIO pin to permit usage of external PHYs. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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2 changed files with 126 additions and 0 deletions
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@ -0,0 +1,68 @@
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From af87d38c442c75a40c7d0a7d8c31557e2e6ccf98 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Sun, 25 May 2025 20:22:40 +0200
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Subject: [PATCH 1/2] pinctrl: airoha: fix wrong PHY LED mux value for LED1
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GPIO46
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In all the MUX value for LED1 GPIO46 there is a Copy-Paste error where
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the MUX value is set to LED0_MODE_MASK instead of LED1_MODE_MASK.
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This wasn't notice as there were no board that made use of the
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secondary PHY LED but looking at the internal Documentation the actual
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value should be LED1_MODE_MASK similar to the other GPIO entry.
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Fix the wrong value to apply the correct MUX configuration.
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Cc: stable@vger.kernel.org
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Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/pinctrl/mediatek/pinctrl-airoha.c | 16 ++++++++--------
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1 file changed, 8 insertions(+), 8 deletions(-)
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--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
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+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
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@@ -1746,8 +1746,8 @@ static const struct airoha_pinctrl_func_
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.regmap[0] = {
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AIROHA_FUNC_MUX,
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REG_GPIO_2ND_I2C_MODE,
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- GPIO_LAN3_LED0_MODE_MASK,
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- GPIO_LAN3_LED0_MODE_MASK
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+ GPIO_LAN3_LED1_MODE_MASK,
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+ GPIO_LAN3_LED1_MODE_MASK
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},
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.regmap[1] = {
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AIROHA_FUNC_MUX,
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@@ -1810,8 +1810,8 @@ static const struct airoha_pinctrl_func_
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.regmap[0] = {
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AIROHA_FUNC_MUX,
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REG_GPIO_2ND_I2C_MODE,
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- GPIO_LAN3_LED0_MODE_MASK,
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- GPIO_LAN3_LED0_MODE_MASK
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+ GPIO_LAN3_LED1_MODE_MASK,
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+ GPIO_LAN3_LED1_MODE_MASK
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},
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.regmap[1] = {
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AIROHA_FUNC_MUX,
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@@ -1874,8 +1874,8 @@ static const struct airoha_pinctrl_func_
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.regmap[0] = {
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AIROHA_FUNC_MUX,
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REG_GPIO_2ND_I2C_MODE,
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- GPIO_LAN3_LED0_MODE_MASK,
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- GPIO_LAN3_LED0_MODE_MASK
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+ GPIO_LAN3_LED1_MODE_MASK,
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+ GPIO_LAN3_LED1_MODE_MASK
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},
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.regmap[1] = {
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AIROHA_FUNC_MUX,
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@@ -1938,8 +1938,8 @@ static const struct airoha_pinctrl_func_
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.regmap[0] = {
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AIROHA_FUNC_MUX,
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REG_GPIO_2ND_I2C_MODE,
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- GPIO_LAN3_LED0_MODE_MASK,
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- GPIO_LAN3_LED0_MODE_MASK
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+ GPIO_LAN3_LED1_MODE_MASK,
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+ GPIO_LAN3_LED1_MODE_MASK
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},
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.regmap[1] = {
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AIROHA_FUNC_MUX,
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@ -0,0 +1,58 @@
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From 110930eb12699b92f767fc599c7ab467dd42358a Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Tue, 8 Jul 2025 14:49:56 +0200
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Subject: [PATCH 2/2] pinctrl: airoha: fix wrong MDIO function bitmaks
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With further testing with an attached Aeonsemi it was discovered that
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the pinctrl MDIO function applied the wrong bitmask. The error was
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probably caused by the confusing documentation related to these bits.
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Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE
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is never actually set but instead it's set force enable to the 2 GPIO
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(gpio 1-2) for MDC and MDIO pin.
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Applying this configuration permits correct functionality of any
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externally attached PHY.
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Cc: stable@vger.kernel.org
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Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/pinctrl/mediatek/pinctrl-airoha.c | 15 +++++++++------
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1 file changed, 9 insertions(+), 6 deletions(-)
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--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
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+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
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@@ -102,6 +102,9 @@
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#define JTAG_UDI_EN_MASK BIT(4)
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#define JTAG_DFD_EN_MASK BIT(3)
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+#define REG_FORCE_GPIO_EN 0x0228
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+#define FORCE_GPIO_EN(n) BIT(n)
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+
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/* LED MAP */
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#define REG_LAN_LED0_MAPPING 0x027c
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#define REG_LAN_LED1_MAPPING 0x0280
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@@ -713,16 +716,16 @@ static const struct airoha_pinctrl_func_
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.name = "mdio",
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.regmap[0] = {
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AIROHA_FUNC_MUX,
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- REG_GPIO_PON_MODE,
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- GPIO_SGMII_MDIO_MODE_MASK,
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- GPIO_SGMII_MDIO_MODE_MASK
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- },
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- .regmap[1] = {
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- AIROHA_FUNC_MUX,
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REG_GPIO_2ND_I2C_MODE,
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GPIO_MDC_IO_MASTER_MODE_MODE,
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GPIO_MDC_IO_MASTER_MODE_MODE
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},
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+ .regmap[1] = {
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+ AIROHA_FUNC_MUX,
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+ REG_FORCE_GPIO_EN,
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+ FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
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+ FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
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+ },
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.regmap_size = 2,
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},
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};
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