diff --git a/target/linux/realtek/dts/rtl8392_zyxel_gs1920-24hp-v1.dts b/target/linux/realtek/dts/rtl8392_zyxel_gs1920-24hp-v1.dts new file mode 100644 index 0000000000..813f3e1571 --- /dev/null +++ b/target/linux/realtek/dts/rtl8392_zyxel_gs1920-24hp-v1.dts @@ -0,0 +1,317 @@ +/dts-v1/; + +#include "rtl839x.dtsi" + +#include +#include +#include + +/ { + compatible = "zyxel,gs1920-24hp-v1", "realtek,rtl8392-soc"; + model = "Zyxel GS1920-24HPv1"; + + aliases { + led-boot = &led_sys; + led-failsafe = &led_sys; + led-running = &led_sys; + led-upgrade = &led_sys; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + chosen { + stdout-path = "serial0:9600n8"; + }; + + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_disable_sys_led>; + compatible = "gpio-leds"; + + led_sys: sys { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + alarm { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_FAULT; + color = ; + }; + + locator { + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + mode { + label = "reset"; + gpios = <&gpio1 32 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + /* i2c of the lower left SFP cage: port 25 */ + i2c0: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp0: sfp-p25 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + los-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio0 23 GPIO_ACTIVE_LOW>; + tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + + /* i2c of the upper left SFP cage: port 26 */ + i2c1: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp1: sfp-p26 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio0 17 GPIO_ACTIVE_LOW>; + tx-fault-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + + /* i2c of the lower right SFP cage: port 27 */ + i2c2: i2c-gpio-2 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp2: sfp-p27 { + compatible = "sff,sfp"; + i2c-bus = <&i2c2>; + los-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio0 13 GPIO_ACTIVE_LOW>; + tx-fault-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + /* i2c of the upper right SFP cage: port 28 */ + i2c3: i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp3: sfp-p28 { + compatible = "sff,sfp"; + i2c-bus = <&i2c3>; + los-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio0 20 GPIO_ACTIVE_LOW>; + tx-fault-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + }; + + /* i2c for hwmon/PoE */ + i2c4: i2c-gpio-4 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio0 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + adt7468: adt7468@2e { + compatible = "adi,adt7468"; + reg = <0x2e>; + }; + }; +}; + +&spi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootbase"; + reg = <0x0 0x20000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + factory_macaddr: macaddr@1fff8 { + reg = <0x1fff8 0x6>; + }; + }; + }; + + partition@20000 { + label = "reserved"; + reg = <0x20000 0x90000>; + read-only; + }; + + partition@b0000 { + reg = <0xb0000 0xf50000>; + label = "factory"; + + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x0 0x10000>; + }; + + partition@10000 { + label = "firmware"; + reg = <0x10000 0xf40000>; + compatible = "openwrt,uimage", "denx,uimage"; + }; + }; + }; + }; +}; + +ðernet0 { + nvmem-cells = <&factory_macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&mdio_bus0 { + /* External phy RTL8218B #1 */ + EXTERNAL_PHY(0) + EXTERNAL_PHY(1) + EXTERNAL_PHY(2) + EXTERNAL_PHY(3) + EXTERNAL_PHY(4) + EXTERNAL_PHY(5) + EXTERNAL_PHY(6) + EXTERNAL_PHY(7) + + /* External phy RTL8218B #2 */ + EXTERNAL_PHY(8) + EXTERNAL_PHY(9) + EXTERNAL_PHY(10) + EXTERNAL_PHY(11) + EXTERNAL_PHY(12) + EXTERNAL_PHY(13) + EXTERNAL_PHY(14) + EXTERNAL_PHY(15) + + /* External phy RTL8218B #3 */ + EXTERNAL_PHY(16) + EXTERNAL_PHY(17) + EXTERNAL_PHY(18) + EXTERNAL_PHY(19) + EXTERNAL_PHY(20) + EXTERNAL_PHY(21) + EXTERNAL_PHY(22) + EXTERNAL_PHY(23) + + /* External phy RTL8214FC #1 */ + EXTERNAL_SFP_PHY_FULL(48, 0) + EXTERNAL_SFP_PHY_FULL(49, 1) + EXTERNAL_SFP_PHY_FULL(50, 2) + EXTERNAL_SFP_PHY_FULL(51, 3) + +}; + +&switch0 { + ports { + SWITCH_PORT_SDS(0, 1, 0, qsgmii) + SWITCH_PORT_SDS(1, 2, 0, qsgmii) + SWITCH_PORT_SDS(2, 3, 0, qsgmii) + SWITCH_PORT_SDS(3, 4, 0, qsgmii) + SWITCH_PORT_SDS(4, 5, 1, qsgmii) + SWITCH_PORT_SDS(5, 6, 1, qsgmii) + SWITCH_PORT_SDS(6, 7, 1, qsgmii) + SWITCH_PORT_SDS(7, 8, 1, qsgmii) + + SWITCH_PORT_SDS(8, 9, 2, qsgmii) + SWITCH_PORT_SDS(9, 10, 2, qsgmii) + SWITCH_PORT_SDS(10, 11, 2, qsgmii) + SWITCH_PORT_SDS(11, 12, 2, qsgmii) + SWITCH_PORT_SDS(12, 13, 3, qsgmii) + SWITCH_PORT_SDS(13, 14, 3, qsgmii) + SWITCH_PORT_SDS(14, 15, 3, qsgmii) + SWITCH_PORT_SDS(15, 16, 3, qsgmii) + + SWITCH_PORT_SDS(16, 17, 4, qsgmii) + SWITCH_PORT_SDS(17, 18, 4, qsgmii) + SWITCH_PORT_SDS(18, 19, 4, qsgmii) + SWITCH_PORT_SDS(19, 20, 4, qsgmii) + SWITCH_PORT_SDS(20, 21, 5, qsgmii) + SWITCH_PORT_SDS(21, 22, 5, qsgmii) + SWITCH_PORT_SDS(22, 23, 5, qsgmii) + SWITCH_PORT_SDS(23, 24, 5, qsgmii) + + SWITCH_PORT_SDS(48, 25, 12, qsgmii) + SWITCH_PORT_SDS(49, 26, 12, qsgmii) + SWITCH_PORT_SDS(50, 27, 12, qsgmii) + SWITCH_PORT_SDS(51, 28, 12, qsgmii) + + /* CPU-Port */ + port@52 { + ethernet = <ðernet0>; + reg = <52>; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&mdio_aux { + status = "okay"; + + gpio1: expander@3 { + compatible = "realtek,rtl8231"; + reg = <3>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio1 0 0 37>; + + led-controller { + compatible = "realtek,rtl8231-leds"; + status = "disabled"; + }; + }; +}; diff --git a/target/linux/realtek/image/rtl839x.mk b/target/linux/realtek/image/rtl839x.mk index 755e9ce49c..2e399fd061 100644 --- a/target/linux/realtek/image/rtl839x.mk +++ b/target/linux/realtek/image/rtl839x.mk @@ -97,3 +97,29 @@ define Device/zyxel_gs1900-48-a1 SUPPORTED_DEVICES += zyxel,gs1900-48 endef TARGET_DEVICES += zyxel_gs1900-48-a1 + +define Device/zyxel_gs1920-24hp-v1 + FLASH_ADDR := 0xb40c0000 + ARTIFACTS := loader.bin + ARTIFACT/loader.bin := \ + rt-loader-standalone | \ + zynsig + SOC := rtl8392 + IMAGE_SIZE := 12144k + DEVICE_VENDOR := Zyxel + DEVICE_MODEL := GS1920-24HP + DEVICE_VARIANT := v1 + DEVICE_PACKAGES := \ + kmod-hwmon-lm85 + KERNEL := \ + kernel-bin | \ + append-dtb | \ + rt-compress | \ + uImage lzma + KERNEL_INITRAMFS := \ + kernel-bin | \ + append-dtb | \ + rt-compress | \ + rt-loader +endef +TARGET_DEVICES += zyxel_gs1920-24hp-v1 diff --git a/target/linux/realtek/rtl839x/config-6.12 b/target/linux/realtek/rtl839x/config-6.12 index 684ba5e590..0bca1d970d 100644 --- a/target/linux/realtek/rtl839x/config-6.12 +++ b/target/linux/realtek/rtl839x/config-6.12 @@ -110,6 +110,7 @@ CONFIG_HZ_PERIODIC=y CONFIG_I2C=y CONFIG_I2C_ALGOBIT=y CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y CONFIG_I2C_GPIO=y CONFIG_I2C_GPIO_SHARED=y # CONFIG_I2C_MUX_RTL9300 is not set