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arm-trusted-firmware-stm32: bump to v2.13
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Since version 4.8.0, OPTEE handles correctly RTC clock configuration for
STM32MP15 based boards. So the patch can be dropped.

Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://github.com/openwrt/openwrt/pull/20953
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Thomas Richard 2025-11-18 13:33:48 +01:00 • committed by Hauke Mehrtens
parent 9c87b7f85e
commit 1cbaed41b5
2 changed files with 3 additions and 54 deletions
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6
package/boot/arm-trusted-firmware-stm32/Makefile
View file

@ -7,10 +7,10 @@
include $(TOPDIR)/rules.mk
PKG_VERSION:=2.12
PKG_RELEASE:=2
PKG_VERSION:=2.13
PKG_RELEASE:=1
PKG_HASH:=b4c047493cac1152203e1ba121ae57267e4899b7bf56eb365e22a933342d31c9
PKG_HASH:=afb5c408392fcec840bd30de9b02a236b0108142024f9853b542b596b0d894e3
PKG_MAINTAINER:=Thomas Richard <thomas.richard@bootlin.com>
include $(INCLUDE_DIR)/kernel.mk

51
package/boot/arm-trusted-firmware-stm32/patches/0001-fix-stm32mp1-fdts-re-enable-RTC-clock.patch
View file

@ -1,51 +0,0 @@
From 33573ea6842198cfdb5b3fdd320db9e2045855e9 Mon Sep 17 00:00:00 2001
From: Valentin Caron <valentin.caron@foss.st.com>
Date: Wed, 11 Dec 2024 11:20:04 +0100
Subject: [PATCH] fix(stm32mp1-fdts): re-enable RTC clock
On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
yet. Re-enable it temporary to get LSE as clock source of RTC.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Change-Id: Ib6071229552e456faffb4fdfc8db9808140d54a7
---
fdts/stm32mp157c-ed1.dts | 2 ++
fdts/stm32mp15xx-dkx.dtsi | 2 ++
2 files changed, 4 insertions(+)
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -194,6 +194,7 @@
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
+ CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_CKPER_HSE
@@ -242,6 +243,7 @@
DIV(DIV_APB3, 1)
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
+ DIV(DIV_RTC, 23)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>;
--- a/fdts/stm32mp15xx-dkx.dtsi
+++ b/fdts/stm32mp15xx-dkx.dtsi
@@ -198,6 +198,7 @@
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
+ CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_CKPER_HSE
@@ -246,6 +247,7 @@
DIV(DIV_APB3, 1)
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
+ DIV(DIV_RTC, 23)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>;