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realtek: dsa: rtl93xx: Add link aggregation support
With this commit it is possible to create 802.3ad compatible bond interface that is interoperable with other 802.3ad compatible switches. Each trunk group can have maximum of 8 ports as members. Hardware also supports trunking with stacked switches, however it is not handled here and the driver only configures the local trunk. rtl930x and rtl931x has minimal differences in trunk/lag Co-developed-by: Sven Eckelmann <se@simonwunderlich.de> Signed-off-by: Sven Eckelmann <se@simonwunderlich.de> Signed-off-by: Harshal Gohel <hg@simonwunderlich.de> Link: https://github.com/openwrt/openwrt/pull/21740 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Harshal Gohel
Hauke Mehrtens
parent
f556b54a2c
commit
05096060ca
4 changed files with 509 additions and 0 deletions
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@ -528,6 +528,148 @@ int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
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return priv->r->lag_set_distribution_algorithm(priv, group, algoidx, algomsk);
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}
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static int rtldsa_93xx_lag_set_group2ports(struct rtl838x_switch_priv *priv, int group,
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struct netdev_lag_upper_info *info)
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{
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DECLARE_BITMAP(ports, ARRAY_SIZE(priv->ports));
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struct rtldsa_93xx_lag_entry e;
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unsigned int table_pos = 0;
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u8 num_of_lag_ports = 0;
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u8 group_ports[8];
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u32 data[3];
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int i;
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/* Read lag table using Table control register 2 */
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struct table_reg *r = priv->r->lag_table();
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rtl_table_read(r, group);
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bitmap_clear(ports, 0, ARRAY_SIZE(priv->ports));
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bitmap_from_arr64(ports, &priv->lags_port_members[group],
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ARRAY_SIZE(priv->ports));
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for (i = 0; i < 3; i++)
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data[i] = sw_r32(rtl_table_data(r, i));
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priv->r->lag_fill_data(data, &e);
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num_of_lag_ports = bitmap_weight(ports, ARRAY_SIZE(priv->ports));
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if (num_of_lag_ports > ARRAY_SIZE(group_ports)) {
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pr_err("%s: Number of LAG ports too high: %u", __func__,
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num_of_lag_ports);
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return -ENOSPC;
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}
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memset(group_ports, 0x3f, sizeof(group_ports));
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table_pos = 0;
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for_each_set_bit(i, ports, ARRAY_SIZE(priv->ports)) {
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group_ports[table_pos] = i;
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table_pos++;
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}
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/* Remove tx disabled ports */
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num_of_lag_ports = table_pos;
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e.trk_dev0 = 0;
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e.trk_port0 = group_ports[0];
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e.trk_dev1 = 0;
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e.trk_port1 = group_ports[1];
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e.trk_dev2 = 0;
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e.trk_port2 = group_ports[2];
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e.trk_dev3 = 0;
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e.trk_port3 = group_ports[3];
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e.trk_dev4 = 0;
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e.trk_port4 = group_ports[4];
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e.trk_dev5 = 0;
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e.trk_port5 = group_ports[5];
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e.trk_dev6 = 0;
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e.trk_port6 = group_ports[6];
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e.trk_dev7 = 0;
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e.trk_port7 = group_ports[7];
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e.num_tx_candi = num_of_lag_ports;
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/* set hash_mask_idx to 0 if we are deleting lag group */
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if (info) {
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if (info->hash_type == NETDEV_LAG_HASH_L2) {
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e.l2_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L2;
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e.ip4_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L2;
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e.ip6_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L2;
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} else if (info->hash_type == NETDEV_LAG_HASH_L23) {
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e.l2_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L23;
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e.ip4_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L23;
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e.ip6_hash_mask_idx = RTL93XX_HASH_MASK_INDEX_L23;
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} else {
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return -EOPNOTSUPP;
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}
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}
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priv->r->lag_write_data(data, &e);
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for (i = 0; i < 3; i++)
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sw_w32(data[i], rtl_table_data(r, i));
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rtl_table_write(r, group);
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rtl_table_release(r);
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return 0;
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}
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static inline void rtldsa_93xx_lag_set_local_group2ports(struct rtl838x_switch_priv *priv, int group,
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u64 ports)
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{
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priv->r->set_port_reg_be(ports, priv->r->trk_mbr_ctr(group));
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}
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int rtldsa_93xx_lag_set_port_members(struct rtl838x_switch_priv *priv, int group,
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u64 members, struct netdev_lag_upper_info *info)
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{
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DECLARE_BITMAP(affected_members, ARRAY_SIZE(priv->ports));
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bool valid_group;
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u64 old_members;
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u64 affected;
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size_t port;
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int ret;
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/* calculate modifications of the LAG group */
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old_members = priv->lags_port_members[group];
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priv->lags_port_members[group] = members;
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affected = old_members | priv->lags_port_members[group];
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bitmap_clear(affected_members, 0, ARRAY_SIZE(priv->ports));
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bitmap_from_arr64(affected_members, &affected, BITS_PER_TYPE(affected));
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valid_group = __sw_hweight64(priv->lags_port_members[group]);
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/* apply global group and port settings */
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ret = rtldsa_93xx_lag_set_group2ports(priv, group, info);
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if (ret)
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return ret;
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for_each_set_bit(port, affected_members, ARRAY_SIZE(priv->ports)) {
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bool valid = priv->lags_port_members[group] & BIT_ULL(port);
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priv->r->lag_set_port2group(group, port, valid);
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}
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/* apply local group and port settings */
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priv->r->lag_set_local_group_id(group, group, valid_group);
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rtldsa_93xx_lag_set_local_group2ports(priv, group, priv->lags_port_members[group]);
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for_each_set_bit(port, affected_members, ARRAY_SIZE(priv->ports)) {
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bool valid = priv->lags_port_members[group] & BIT_ULL(port);
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priv->r->lag_set_local_port2group(group, port, valid);
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}
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/* write lag table (and maybe additional information) to SRAM */
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priv->r->lag_sync_tables();
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return 0;
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}
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// Currently Unused
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// /* Allocate a 64 bit octet counter located in the LOG HW table */
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// static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv)
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@ -406,13 +406,98 @@
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#define RTL839X_TRK_HASH_IDX_CTRL (0x2280)
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#define RTL839X_TRK_HASH_CTRL (0x2284)
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#define RTL930X_LOCAL_PORT_TRK_MAP (0xD0C8)
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#define RTL930X_TRK_ID_CTRL (0xA3A8)
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#define RTL930X_TRK_MBR_CTRL (0xA41C)
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#define RTL930X_TRK_HASH_CTRL (0x9F80)
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#define RTL930X_TRK_CTRL (0x9F88)
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#define RTL930X_TRK_SHIFT_CTRL (0x9F8C)
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#define RTL930X_TRK_LOCAL_TBL_REFRESH (0x9F90)
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#define RTL930X_TRK_LOCAL_TBL (0x9F94)
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#define RTL930X_TRK_STK_CTRL (0xA07C)
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#define RTL930X_TRK_ID_CTRL_TRK_VALID BIT(6)
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#define RTL930X_TRK_ID_CTRL_TRK_ID GENMASK(5, 0)
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#define RTL930X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR BIT(6)
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#define RTL930X_LOCAL_PORT_TRK_MAP_TRK_ID GENMASK(5, 0)
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#define RTL930X_SRC_TRK_MAP_TRK_VALID BIT(31)
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#define RTL930X_SRC_TRK_MAP_TRK_ID GENMASK(30, 25)
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#define RTL931X_LOCAL_PORT_TRK_MAP (0x4CAC)
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#define RTL931X_TRK_ID_CTRL (0xB800)
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#define RTL931X_TRK_MBR_CTRL (0xB8D0)
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#define RTL931X_TRK_HASH_CTRL (0xBA70)
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#define RTL931X_TRK_CTRL (0xBA78)
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#define RTL931X_TRK_SHIFT_CTRL (0xBA7C)
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#define RTL931X_TRK_LOCAL_TBL_REFRESH (0xBA80)
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#define RTL931X_TRK_LOCAL_TBL (0xBA84)
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#define RTL931X_TRK_STK_CTRL (0xBE94)
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#define RLT931X_TRK_ID_CTRL_TRK_ID GENMASK(6, 0)
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#define RTL931X_TRK_ID_CTRL_TRK_VALID BIT(7)
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#define RTL931X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR BIT(7)
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#define RTL931X_LOCAL_PORT_TRK_MAP_TRK_ID GENMASK(6, 0)
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#define RTL931X_SRC_TRK_MAP_TRK_ID GENMASK(30, 24)
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#define RTL931X_SRC_TRK_MAP_TRK_ID_VALID BIT(31)
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#define GENMASK_MOD(high, low) GENMASK((high) % 32, (low) % 32)
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#define BIT_MOD(bit) BIT((bit) % 32)
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/* RTL930X LAG Table offsets */
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#define RTL930X_LAG_NUM_TX_CANDI GENMASK_MOD(92, 89)
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#define RTL930X_LAG_L2_HASH_MSK_IDX BIT_MOD(88)
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#define RTL930X_LAG_IP4_HASH_MSK_IDX BIT_MOD(87)
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#define RTL930X_LAG_IP6_HASH_MSK_IDX BIT_MOD(86)
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#define RTL930X_LAG_SEP_DLF_BCAST_EN BIT_MOD(85)
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#define RTL930X_LAG_SEP_KWN_MC_EN BIT_MOD(84)
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#define RTL930X_LAG_TRK_DEV7 GENMASK_MOD(83, 80)
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#define RTL930X_LAG_TRK_PORT7 GENMASK_MOD(79, 74)
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#define RTL930X_LAG_TRK_DEV6 GENMASK_MOD(73, 70)
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#define RTL930X_LAG_TRK_PORT6 GENMASK_MOD(69, 64)
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#define RTL930X_LAG_TRK_DEV5 GENMASK_MOD(61, 58)
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#define RTL930X_LAG_TRK_PORT5 GENMASK_MOD(57, 52)
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#define RTL930X_LAG_TRK_DEV4 GENMASK_MOD(51, 48)
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#define RTL930X_LAG_TRK_PORT4 GENMASK_MOD(47, 42)
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#define RTL930X_LAG_TRK_DEV3 GENMASK_MOD(41, 38)
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#define RTL930X_LAG_TRK_PORT3 GENMASK_MOD(37, 32)
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#define RTL930X_LAG_TRK_DEV2 GENMASK_MOD(29, 26)
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#define RTL930X_LAG_TRK_PORT2 GENMASK_MOD(25, 20)
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#define RTL930X_LAG_TRK_DEV1 GENMASK_MOD(19, 16)
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#define RTL930X_LAG_TRK_PORT1 GENMASK_MOD(15, 10)
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#define RTL930X_LAG_TRK_DEV0 GENMASK_MOD(9, 6)
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#define RTL930X_LAG_TRK_PORT0 GENMASK_MOD(5, 0)
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/* RTL931X LAG Table offsets */
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#define RTL931X_LAG_NUM_TX_CANDI GENMASK_MOD(92, 89)
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#define RTL931X_LAG_L2_HASH_MSK_IDX BIT_MOD(88)
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#define RTL931X_LAG_IP4_HASH_MSK_IDX BIT_MOD(87)
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#define RTL931X_LAG_IP6_HASH_MSK_IDX BIT_MOD(86)
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#define RTL931X_LAG_SEP_FLOOD_EN BIT_MOD(85)
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#define RTL931X_LAG_SEP_KWN_MC_EN BIT_MOD(84)
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#define RTL931X_LAG_TRK_DEV7 GENMASK_MOD(83, 80)
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#define RTL931X_LAG_TRK_PORT7 GENMASK_MOD(79, 74)
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#define RTL931X_LAG_TRK_DEV6 GENMASK_MOD(73, 70)
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#define RTL931X_LAG_TRK_PORT6 GENMASK_MOD(69, 64)
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#define RTL931X_LAG_TRK_DEV5 GENMASK_MOD(61, 58)
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#define RTL931X_LAG_TRK_PORT5 GENMASK_MOD(57, 52)
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#define RTL931X_LAG_TRK_DEV4 GENMASK_MOD(51, 48)
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#define RTL931X_LAG_TRK_PORT4 GENMASK_MOD(47, 42)
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#define RTL931X_LAG_TRK_DEV3 GENMASK_MOD(41, 38)
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#define RTL931X_LAG_TRK_PORT3 GENMASK_MOD(37, 32)
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#define RTL931X_LAG_TRK_DEV2 GENMASK_MOD(29, 26)
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#define RTL931X_LAG_TRK_PORT2 GENMASK_MOD(25, 20)
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#define RTL931X_LAG_TRK_DEV1 GENMASK_MOD(19, 16)
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#define RTL931X_LAG_TRK_PORT1 GENMASK_MOD(15, 10)
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#define RTL931X_LAG_TRK_DEV0 GENMASK_MOD(9, 6)
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#define RTL931X_LAG_TRK_PORT0 GENMASK_MOD(5, 0)
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/* Attack prevention */
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#define RTL838X_ATK_PRVNT_PORT_EN (0x5B00)
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@ -886,6 +971,36 @@ struct rtldsa_counter_state {
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struct rtnl_link_stats64 link_stat;
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};
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struct rtldsa_93xx_lag_entry {
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u32 trk_port0:6;
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u32 trk_dev0:4;
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u32 trk_port1:6;
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u32 trk_dev1:4;
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u32 trk_port2:6;
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u32 trk_dev2:4;
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u32 trk_port3:6;
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u32 trk_dev3:4;
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u32 trk_port4:6;
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u32 trk_dev4:4;
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u32 trk_port5:6;
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u32 trk_dev5:4;
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u32 trk_port6:6;
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u32 trk_dev6:4;
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u32 trk_port7:6;
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u32 trk_dev7:4;
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u32 sep_kwn_mc_en:1;
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union {
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// for rtl930x
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u32 sep_dlf_bcast_en:1;
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// for rtl931x
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u32 sep_flood_en:1;
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} flood_dlf_bcast;
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u32 ip6_hash_mask_idx:1;
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u32 ip4_hash_mask_idx:1;
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u32 l2_hash_mask_idx:1;
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u32 num_tx_candi:4;
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};
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struct rtldsa_port {
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bool enable:1;
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bool phy_is_integrated:1;
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@ -1387,6 +1502,13 @@ struct rtldsa_config {
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int (*lag_set_distribution_algorithm)(struct rtl838x_switch_priv *priv,
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int group, int algoidx,
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u32 algomask);
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void (*lag_set_local_group_id)(int local_group, int global_group, bool valid);
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void (*lag_write_data)(u32 data[], struct rtldsa_93xx_lag_entry *e);
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void (*lag_fill_data)(u32 data[], struct rtldsa_93xx_lag_entry *e);
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void (*lag_set_local_port2group)(int group, int port, bool valid);
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void (*lag_set_port2group)(int group, int port, bool valid);
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struct table_reg* (*lag_table)(void);
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void (*lag_sync_tables)(void);
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};
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struct rtl838x_switch_priv {
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@ -1463,6 +1585,8 @@ void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv);
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void rtldsa_93xx_lag_switch_init(struct rtl838x_switch_priv *priv);
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int rtldsa_93xx_lag_set_distribution_algorithm(struct rtl838x_switch_priv *priv,
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int group, int algoidx, u32 algomsk);
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int rtldsa_93xx_lag_set_port_members(struct rtl838x_switch_priv *priv, int group,
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u64 members, struct netdev_lag_upper_info *info);
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void rtldsa_93xx_prepare_lag_fdb(struct rtl838x_l2_entry *e, int lag_group);
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@ -532,6 +532,118 @@ static void rtldsa_930x_enable_flood(int port, bool enable)
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RTL930X_L2_LRN_PORT_CONSTRT_CTRL + port * 4);
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}
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static void rtldsa_930x_lag_set_port2group(int group, int port, bool valid)
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{
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struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 8);
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u32 mask = valid ? RTL930X_SRC_TRK_MAP_TRK_VALID : 0;
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rtl_table_read(r, port);
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mask |= FIELD_PREP(RTL930X_SRC_TRK_MAP_TRK_ID, group); // Update TRK Field.
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sw_w32(mask, rtl_table_data(r, 0));
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rtl_table_write(r, port);
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rtl_table_release(r);
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}
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/* Write data from the data buffer into the lag-entry strucure */
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static void rtldsa_930x_lag_fill_data(u32 data[], struct rtldsa_93xx_lag_entry *e)
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{
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/* 95-64 */
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e->num_tx_candi = FIELD_GET(RTL930X_LAG_NUM_TX_CANDI, data[0]);
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e->l2_hash_mask_idx = FIELD_GET(RTL930X_LAG_L2_HASH_MSK_IDX, data[0]);
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e->ip4_hash_mask_idx = FIELD_GET(RTL930X_LAG_IP4_HASH_MSK_IDX, data[0]);
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e->ip6_hash_mask_idx = FIELD_GET(RTL930X_LAG_IP6_HASH_MSK_IDX, data[0]);
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e->flood_dlf_bcast.sep_dlf_bcast_en = FIELD_GET(RTL930X_LAG_SEP_DLF_BCAST_EN, data[0]);
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e->sep_kwn_mc_en = FIELD_GET(RTL930X_LAG_SEP_KWN_MC_EN, data[0]);
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e->trk_dev7 = FIELD_GET(RTL930X_LAG_TRK_DEV7, data[0]);
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e->trk_port7 = FIELD_GET(RTL930X_LAG_TRK_PORT7, data[0]);
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e->trk_dev6 = FIELD_GET(RTL930X_LAG_TRK_DEV6, data[0]);
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e->trk_port6 = FIELD_GET(RTL930X_LAG_TRK_PORT6, data[0]);
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/* 63-32 */
|
||||
e->trk_dev5 = FIELD_GET(RTL930X_LAG_TRK_DEV5, data[1]);
|
||||
e->trk_port5 = FIELD_GET(RTL930X_LAG_TRK_PORT5, data[1]);
|
||||
e->trk_dev4 = FIELD_GET(RTL930X_LAG_TRK_DEV4, data[1]);
|
||||
e->trk_port4 = FIELD_GET(RTL930X_LAG_TRK_PORT4, data[1]);
|
||||
e->trk_dev3 = FIELD_GET(RTL930X_LAG_TRK_DEV3, data[1]);
|
||||
e->trk_port3 = FIELD_GET(RTL930X_LAG_TRK_PORT3, data[1]);
|
||||
|
||||
/* 31-0 */
|
||||
e->trk_dev2 = FIELD_GET(RTL930X_LAG_TRK_DEV2, data[2]);
|
||||
e->trk_port2 = FIELD_GET(RTL930X_LAG_TRK_PORT2, data[2]);
|
||||
e->trk_dev1 = FIELD_GET(RTL930X_LAG_TRK_DEV1, data[2]);
|
||||
e->trk_port1 = FIELD_GET(RTL930X_LAG_TRK_PORT1, data[2]);
|
||||
e->trk_dev0 = FIELD_GET(RTL930X_LAG_TRK_DEV0, data[2]);
|
||||
e->trk_port0 = FIELD_GET(RTL930X_LAG_TRK_PORT0, data[2]);
|
||||
}
|
||||
|
||||
/* Write lag-entry data into buffer */
|
||||
static void rtldsa_930x_lag_write_data(u32 data[], struct rtldsa_93xx_lag_entry *e)
|
||||
{
|
||||
/* 95-64 */
|
||||
data[0] = FIELD_PREP(RTL930X_LAG_NUM_TX_CANDI, e->num_tx_candi);
|
||||
data[0] |= FIELD_PREP(RTL930X_LAG_L2_HASH_MSK_IDX, e->l2_hash_mask_idx);
|
||||
data[0] |= FIELD_PREP(RTL930X_LAG_IP4_HASH_MSK_IDX, e->ip4_hash_mask_idx);
|
||||
data[0] |= FIELD_PREP(RTL930X_LAG_IP6_HASH_MSK_IDX, e->ip6_hash_mask_idx);
|
||||
data[0] |= FIELD_PREP(RTL930X_LAG_SEP_DLF_BCAST_EN, e->flood_dlf_bcast.sep_dlf_bcast_en);
|
||||
data[0] |= FIELD_PREP(RTL930X_LAG_SEP_KWN_MC_EN, e->sep_kwn_mc_en);
|
||||
data[0] |= FIELD_PREP(RTL930X_LAG_TRK_DEV7, e->trk_dev7);
|
||||
data[0] |= FIELD_PREP(RTL930X_LAG_TRK_PORT7, e->trk_port7);
|
||||
data[0] |= FIELD_PREP(RTL930X_LAG_TRK_DEV6, e->trk_dev6);
|
||||
data[0] |= FIELD_PREP(RTL930X_LAG_TRK_PORT6, e->trk_port6);
|
||||
|
||||
/* 63-32 */
|
||||
data[1] = FIELD_PREP(RTL930X_LAG_TRK_DEV5, e->trk_dev5);
|
||||
data[1] |= FIELD_PREP(RTL930X_LAG_TRK_PORT5, e->trk_port5);
|
||||
data[1] |= FIELD_PREP(RTL930X_LAG_TRK_DEV4, e->trk_dev4);
|
||||
data[1] |= FIELD_PREP(RTL930X_LAG_TRK_PORT4, e->trk_port4);
|
||||
data[1] |= FIELD_PREP(RTL930X_LAG_TRK_DEV3, e->trk_dev3);
|
||||
data[1] |= FIELD_PREP(RTL930X_LAG_TRK_PORT3, e->trk_port3);
|
||||
|
||||
/* 31-0 */
|
||||
data[2] = FIELD_PREP(RTL930X_LAG_TRK_DEV2, e->trk_dev2);
|
||||
data[2] |= FIELD_PREP(RTL930X_LAG_TRK_PORT2, e->trk_port2);
|
||||
data[2] |= FIELD_PREP(RTL930X_LAG_TRK_DEV1, e->trk_dev1);
|
||||
data[2] |= FIELD_PREP(RTL930X_LAG_TRK_PORT1, e->trk_port1);
|
||||
data[2] |= FIELD_PREP(RTL930X_LAG_TRK_DEV0, e->trk_dev0);
|
||||
data[2] |= FIELD_PREP(RTL930X_LAG_TRK_PORT0, e->trk_port0);
|
||||
}
|
||||
|
||||
static void rtldsa_930x_lag_set_local_group_id(int local_group, int global_group, bool valid)
|
||||
{
|
||||
u32 mask = 0;
|
||||
|
||||
mask |= valid ? RTL930X_TRK_ID_CTRL_TRK_VALID : 0;
|
||||
mask |= FIELD_PREP(RTL930X_TRK_ID_CTRL_TRK_ID, global_group);
|
||||
sw_w32(mask, RTL930X_TRK_ID_CTRL + (4 * local_group));
|
||||
}
|
||||
|
||||
static void rtldsa_930x_lag_set_local_port2group(int group, int port, bool valid)
|
||||
{
|
||||
u32 mask = 0;
|
||||
|
||||
mask |= valid ? RTL930X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR : 0;
|
||||
mask |= FIELD_PREP(RTL930X_LOCAL_PORT_TRK_MAP_TRK_ID, group);
|
||||
sw_w32(mask, RTL930X_LOCAL_PORT_TRK_MAP + (4 * port));
|
||||
}
|
||||
|
||||
static void rtldsa_930x_lag_sync_tables(void)
|
||||
{
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
sw_w32(BIT(0), RTL930X_TRK_LOCAL_TBL_REFRESH);
|
||||
|
||||
ret = readx_poll_timeout(sw_r32, RTL930X_TRK_LOCAL_TBL_REFRESH, val,
|
||||
!(val & BIT(0)), 20, 10000);
|
||||
if (ret)
|
||||
pr_err("%s: timeout\n", __func__);
|
||||
}
|
||||
|
||||
static struct table_reg *rtldsa_930x_lag_table(void)
|
||||
{
|
||||
return rtl_table_get(RTL9300_TBL_0, 7);
|
||||
}
|
||||
|
||||
static int rtldsa_930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, int port, u32 port_state[])
|
||||
{
|
||||
int idx = 1 - ((port + 3) / 16);
|
||||
|
|
@ -2806,4 +2918,11 @@ const struct rtldsa_config rtldsa_930x_cfg = {
|
|||
.lag_switch_init = rtldsa_93xx_lag_switch_init,
|
||||
.lag_set_port_members = rtldsa_93xx_lag_set_port_members,
|
||||
.lag_set_distribution_algorithm = rtldsa_93xx_lag_set_distribution_algorithm,
|
||||
.lag_set_local_group_id = rtldsa_930x_lag_set_local_group_id,
|
||||
.lag_write_data = rtldsa_930x_lag_write_data,
|
||||
.lag_fill_data = rtldsa_930x_lag_fill_data,
|
||||
.lag_set_local_port2group = rtldsa_930x_lag_set_local_port2group,
|
||||
.lag_set_port2group = rtldsa_930x_lag_set_port2group,
|
||||
.lag_sync_tables = rtldsa_930x_lag_sync_tables,
|
||||
.lag_table = rtldsa_930x_lag_table,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1745,6 +1745,123 @@ static void rtldsa_931x_led_init(struct rtl838x_switch_priv *priv)
|
|||
dev_dbg(dev, "%08x: %08x\n", 0xbb000600 + i * 4, sw_r32(0x0600 + i * 4));
|
||||
}
|
||||
|
||||
static void rtldsa_931x_lag_set_port2group(int group, int port, bool valid)
|
||||
{
|
||||
u32 trk_id_valid = valid ? RTL931X_SRC_TRK_MAP_TRK_ID_VALID : 0;
|
||||
struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 13);
|
||||
u32 mask = 0;
|
||||
|
||||
rtl_table_read(r, port);
|
||||
|
||||
mask |= trk_id_valid;
|
||||
/* Update TRK Field */
|
||||
mask |= FIELD_PREP(RTL931X_SRC_TRK_MAP_TRK_ID, group);
|
||||
|
||||
sw_w32(mask, rtl_table_data(r, 0));
|
||||
rtl_table_write(r, port);
|
||||
rtl_table_release(r);
|
||||
}
|
||||
|
||||
/* Write data from the data buffer into the lag-entry strucure */
|
||||
static void rtldsa_931x_lag_fill_data(u32 data[], struct rtldsa_93xx_lag_entry *e)
|
||||
{
|
||||
/* 95-64 */
|
||||
e->num_tx_candi = FIELD_GET(RTL931X_LAG_NUM_TX_CANDI, data[0]);
|
||||
e->l2_hash_mask_idx = FIELD_GET(RTL931X_LAG_L2_HASH_MSK_IDX, data[0]);
|
||||
e->ip4_hash_mask_idx = FIELD_GET(RTL931X_LAG_IP4_HASH_MSK_IDX, data[0]);
|
||||
e->ip6_hash_mask_idx = FIELD_GET(RTL931X_LAG_IP6_HASH_MSK_IDX, data[0]);
|
||||
e->flood_dlf_bcast.sep_flood_en = FIELD_GET(RTL931X_LAG_SEP_FLOOD_EN, data[0]);
|
||||
e->sep_kwn_mc_en = FIELD_GET(RTL931X_LAG_SEP_KWN_MC_EN, data[0]);
|
||||
e->trk_dev7 = FIELD_GET(RTL931X_LAG_TRK_DEV7, data[0]);
|
||||
e->trk_port7 = FIELD_GET(RTL931X_LAG_TRK_PORT7, data[0]);
|
||||
e->trk_dev6 = FIELD_GET(RTL931X_LAG_TRK_DEV6, data[0]);
|
||||
e->trk_port6 = FIELD_GET(RTL931X_LAG_TRK_PORT6, data[0]);
|
||||
|
||||
/* 63-32 */
|
||||
e->trk_dev5 = FIELD_GET(RTL931X_LAG_TRK_DEV5, data[1]);
|
||||
e->trk_port5 = FIELD_GET(RTL931X_LAG_TRK_PORT5, data[1]);
|
||||
e->trk_dev4 = FIELD_GET(RTL931X_LAG_TRK_DEV4, data[1]);
|
||||
e->trk_port4 = FIELD_GET(RTL931X_LAG_TRK_PORT4, data[1]);
|
||||
e->trk_dev3 = FIELD_GET(RTL931X_LAG_TRK_DEV3, data[1]);
|
||||
e->trk_port3 = FIELD_GET(RTL931X_LAG_TRK_PORT3, data[1]);
|
||||
|
||||
/* 31-0 */
|
||||
e->trk_dev2 = FIELD_GET(RTL931X_LAG_TRK_DEV2, data[2]);
|
||||
e->trk_port2 = FIELD_GET(RTL931X_LAG_TRK_PORT2, data[2]);
|
||||
e->trk_dev1 = FIELD_GET(RTL931X_LAG_TRK_DEV1, data[2]);
|
||||
e->trk_port1 = FIELD_GET(RTL931X_LAG_TRK_PORT1, data[2]);
|
||||
e->trk_dev0 = FIELD_GET(RTL931X_LAG_TRK_DEV0, data[2]);
|
||||
e->trk_port0 = FIELD_GET(RTL931X_LAG_TRK_PORT0, data[2]);
|
||||
}
|
||||
|
||||
/* Write lag-entry data into buffer */
|
||||
static void rtldsa_931x_lag_write_data(u32 data[], struct rtldsa_93xx_lag_entry *e)
|
||||
{
|
||||
/* 95-64 */
|
||||
data[0] = FIELD_PREP(RTL931X_LAG_NUM_TX_CANDI, e->num_tx_candi);
|
||||
data[0] |= FIELD_PREP(RTL931X_LAG_L2_HASH_MSK_IDX, e->l2_hash_mask_idx);
|
||||
data[0] |= FIELD_PREP(RTL931X_LAG_IP4_HASH_MSK_IDX, e->ip4_hash_mask_idx);
|
||||
data[0] |= FIELD_PREP(RTL931X_LAG_IP6_HASH_MSK_IDX, e->ip6_hash_mask_idx);
|
||||
data[0] |= FIELD_PREP(RTL931X_LAG_SEP_FLOOD_EN, e->flood_dlf_bcast.sep_flood_en);
|
||||
data[0] |= FIELD_PREP(RTL931X_LAG_SEP_KWN_MC_EN, e->sep_kwn_mc_en);
|
||||
data[0] |= FIELD_PREP(RTL931X_LAG_TRK_DEV7, e->trk_dev7);
|
||||
data[0] |= FIELD_PREP(RTL931X_LAG_TRK_PORT7, e->trk_port7);
|
||||
data[0] |= FIELD_PREP(RTL931X_LAG_TRK_DEV6, e->trk_dev6);
|
||||
data[0] |= FIELD_PREP(RTL931X_LAG_TRK_PORT6, e->trk_port6);
|
||||
|
||||
/* 63-32 */
|
||||
data[1] = FIELD_PREP(RTL931X_LAG_TRK_DEV5, e->trk_dev5);
|
||||
data[1] |= FIELD_PREP(RTL931X_LAG_TRK_PORT5, e->trk_port5);
|
||||
data[1] |= FIELD_PREP(RTL931X_LAG_TRK_DEV4, e->trk_dev4);
|
||||
data[1] |= FIELD_PREP(RTL931X_LAG_TRK_PORT4, e->trk_port4);
|
||||
data[1] |= FIELD_PREP(RTL931X_LAG_TRK_DEV3, e->trk_dev3);
|
||||
data[1] |= FIELD_PREP(RTL931X_LAG_TRK_PORT3, e->trk_port3);
|
||||
|
||||
/* 31-0 */
|
||||
data[2] = FIELD_PREP(RTL931X_LAG_TRK_DEV2, e->trk_dev2);
|
||||
data[2] |= FIELD_PREP(RTL931X_LAG_TRK_PORT2, e->trk_port2);
|
||||
data[2] |= FIELD_PREP(RTL931X_LAG_TRK_DEV1, e->trk_dev1);
|
||||
data[2] |= FIELD_PREP(RTL931X_LAG_TRK_PORT1, e->trk_port1);
|
||||
data[2] |= FIELD_PREP(RTL931X_LAG_TRK_DEV0, e->trk_dev0);
|
||||
data[2] |= FIELD_PREP(RTL931X_LAG_TRK_PORT0, e->trk_port0);
|
||||
}
|
||||
|
||||
static void rtldsa_931x_lag_set_local_group_id(int local_group, int global_group, bool valid)
|
||||
{
|
||||
u32 mask = 0;
|
||||
|
||||
mask |= valid ? RTL931X_TRK_ID_CTRL_TRK_VALID : 0;
|
||||
mask |= FIELD_PREP(RLT931X_TRK_ID_CTRL_TRK_ID, global_group);
|
||||
sw_w32(mask, RTL931X_TRK_ID_CTRL + (4 * local_group));
|
||||
}
|
||||
|
||||
static void rtldsa_931x_lag_set_local_port2group(int group, int port, bool valid)
|
||||
{
|
||||
u32 mask = 0;
|
||||
|
||||
mask |= valid ? RTL931X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR : 0;
|
||||
mask |= FIELD_PREP(RTL931X_LOCAL_PORT_TRK_MAP_TRK_ID, group);
|
||||
sw_w32(mask, RTL931X_LOCAL_PORT_TRK_MAP + (4 * port));
|
||||
}
|
||||
|
||||
static void rtldsa_931x_lag_sync_tables(void)
|
||||
{
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
sw_w32(BIT(0), RTL931X_TRK_LOCAL_TBL_REFRESH);
|
||||
|
||||
ret = readx_poll_timeout(sw_r32, RTL931X_TRK_LOCAL_TBL_REFRESH, val,
|
||||
!(val & BIT(0)), 20, 10000);
|
||||
if (ret)
|
||||
pr_err("%s: timeout\n", __func__);
|
||||
}
|
||||
|
||||
static struct table_reg *rtldsa_931x_lag_table(void)
|
||||
{
|
||||
return rtl_table_get(RTL9310_TBL_2, 0);
|
||||
}
|
||||
|
||||
static u64 rtldsa_931x_stat_port_table_read(int port, unsigned int mib_size,
|
||||
unsigned int mib_offset, bool is_pvt)
|
||||
{
|
||||
|
|
@ -1930,4 +2047,11 @@ const struct rtldsa_config rtldsa_931x_cfg = {
|
|||
.lag_switch_init = rtldsa_93xx_lag_switch_init,
|
||||
.lag_set_port_members = rtldsa_93xx_lag_set_port_members,
|
||||
.lag_set_distribution_algorithm = rtldsa_93xx_lag_set_distribution_algorithm,
|
||||
.lag_set_local_group_id = rtldsa_931x_lag_set_local_group_id,
|
||||
.lag_write_data = rtldsa_931x_lag_write_data,
|
||||
.lag_fill_data = rtldsa_931x_lag_fill_data,
|
||||
.lag_set_local_port2group = rtldsa_931x_lag_set_local_port2group,
|
||||
.lag_set_port2group = rtldsa_931x_lag_set_port2group,
|
||||
.lag_sync_tables = rtldsa_931x_lag_sync_tables,
|
||||
.lag_table = rtldsa_931x_lag_table,
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue