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qualcommax: ipq50xx: backport upstreamed patches for adding ipq5018 GE PHY support
Use upstreamed patch for adding driver support and the the mdio and phy nodes. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/19890 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
George Moussalem
Robert Marko
parent
f11f4a35c9
commit
0465daed5d
12 changed files with 76 additions and 110 deletions
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@ -1,7 +1,6 @@
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CONFIG_GPIO_WATCHDOG=y
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# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
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CONFIG_GRO_CELLS=y
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CONFIG_IPQ5018_PHY=y
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CONFIG_IPQ_CMN_PLL=y
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CONFIG_IPQ_GCC_5018=y
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CONFIG_LEDS_PWM=y
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@ -1,11 +1,7 @@
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From 19600588e6403ff9f6c1e985fc025afb9160a56f Mon Sep 17 00:00:00 2001
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From f6a4a55ae5d99f865e106916a9295548e381de47 Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Wed, 28 May 2025 08:37:25 +0400
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Subject: [PATCH v2 2/5] clk: qcom: gcc-ipq5018: fix GE PHY reset
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MIME-Version: 1.0
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Content-Type: text/plain; charset="utf-8"
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Content-Transfer-Encoding: 7bit
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Message-Id: <20250528-ipq5018-ge-phy-v2-2-68fc3a8248dd@outlook.com>
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Date: Mon, 30 Jun 2025 16:35:00 +0400
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Subject: clk: qcom: gcc-ipq5018: fix GE PHY reset
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The MISC reset is supposed to trigger a resets across the MDC, DSP, and
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RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask
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@ -14,11 +10,16 @@ driver.
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Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-1-01be06378c15@outlook.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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drivers/clk/qcom/gcc-ipq5018.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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(limited to 'drivers/clk/qcom/gcc-ipq5018.c')
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--- a/drivers/clk/qcom/gcc-ipq5018.c
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+++ b/drivers/clk/qcom/gcc-ipq5018.c
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@@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_i
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@ -1,75 +1,39 @@
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From 9a89cb300c1ed5b90bae5684c88c85895a15c849 Mon Sep 17 00:00:00 2001
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From d46502279a11b48ede1d8bf65a229c8231bf0602 Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Mon, 02 Jun 2025 12:50:39 +0400
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Subject: [PATCH v3 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support
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MIME-Version: 1.0
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Content-Type: text/plain; charset="utf-8"
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Content-Transfer-Encoding: 7bit
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Message-Id: <20250602-ipq5018-ge-phy-v3-3-0d8f39f402a6@outlook.com>
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Date: Fri, 13 Jun 2025 05:55:08 +0400
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Subject: net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support
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The IPQ5018 SoC contains a single internal Gigabit Ethernet PHY which
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provides an MDI interface directly to an RJ45 connector or an external
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switch over a PHY to PHY link.
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The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and
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802.3az EEE.
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The PHY supports 10BASE-T/100BASE-TX/1000BASE-T link modes in SGMII
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interface mode, CDT, auto-negotiation and 802.3az EEE.
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Let's add support for this PHY in the at803x driver as it falls within
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the Qualcomm Atheros OUI.
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Link: https://patch.msgid.link/20250613-ipq5018-ge-phy-v5-2-9af06e34ea6b@outlook.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/phy/qcom/Kconfig | 2 +-
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drivers/net/phy/qcom/at803x.c | 185 ++++++++++++++++++++++++++++++++++++++++--
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2 files changed, 178 insertions(+), 9 deletions(-)
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drivers/net/phy/qcom/at803x.c | 167 ++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 167 insertions(+)
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(limited to 'drivers/net/phy/qcom/at803x.c')
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--- a/drivers/net/phy/qcom/Kconfig
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+++ b/drivers/net/phy/qcom/Kconfig
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@@ -7,7 +7,7 @@ config AT803X_PHY
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select QCOM_NET_PHYLIB
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depends on REGULATOR
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help
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- Currently supports the AR8030, AR8031, AR8033, AR8035 model
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+ Currently supports the AR8030, AR8031, AR8033, AR8035, IPQ5018 model
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config QCA83XX_PHY
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tristate "Qualcomm Atheros QCA833x PHYs"
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--- a/drivers/net/phy/qcom/at803x.c
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+++ b/drivers/net/phy/qcom/at803x.c
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@@ -7,19 +7,24 @@
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* Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
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*/
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-#include <linux/phy.h>
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-#include <linux/module.h>
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-#include <linux/string.h>
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-#include <linux/netdevice.h>
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+#include <linux/bitfield.h>
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+#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool_netlink.h>
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-#include <linux/bitfield.h>
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-#include <linux/regulator/of_regulator.h>
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-#include <linux/regulator/driver.h>
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-#include <linux/regulator/consumer.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/module.h>
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+#include <linux/netdevice.h>
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@@ -19,6 +19,7 @@
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#include <linux/regulator/consumer.h>
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#include <linux/of.h>
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+#include <linux/phy.h>
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#include <linux/phylink.h>
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+#include <linux/regmap.h>
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+#include <linux/regulator/consumer.h>
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+#include <linux/regulator/driver.h>
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+#include <linux/regulator/of_regulator.h>
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+#include <linux/reset.h>
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#include <linux/sfp.h>
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+#include <linux/string.h>
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#include <dt-bindings/net/qca-ar803x.h>
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#include "qcom.h"
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@@ -93,6 +98,8 @@
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@@ -93,6 +94,8 @@
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#define ATH8035_PHY_ID 0x004dd072
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#define AT8030_PHY_ID_MASK 0xffffffef
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@ -78,7 +42,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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#define QCA9561_PHY_ID 0x004dd042
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#define AT803X_PAGE_FIBER 0
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@@ -105,6 +112,50 @@
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@@ -105,6 +108,48 @@
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/* disable hibernation mode */
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#define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
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@ -95,8 +59,8 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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+
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+#define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000
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+#define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001
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+#define IPQ5018_PHY_PCS_AZ_CTRL1 0x8008
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+#define IPQ5018_PHY_PCS_AZ_CTRL2 0x8009
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+#define IPQ5018_PHY_PCS_EEE_TX_TIMER 0x8008
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+#define IPQ5018_PHY_PCS_EEE_RX_TIMER 0x8009
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3 0x8074
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4 0x8075
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5 0x8076
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@ -108,8 +72,8 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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+
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+#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1
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+#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6
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+#define IPQ5018_PHY_PCS_AZ_CTRL1_VAL 0x7880
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+#define IPQ5018_PHY_PCS_AZ_CTRL2_VAL 0xc8
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+#define IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL 0x7880
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+#define IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL 0xc8
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL 0xc040
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL 0xa060
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL 0xc040
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@ -123,13 +87,11 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4)
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+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50
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+#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080
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+
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+#define IPQ5018_TCSR_ETH_LDO_READY BIT(0)
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+
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MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi");
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MODULE_LICENSE("GPL");
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@@ -130,6 +181,11 @@ struct at803x_context {
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@@ -130,6 +175,11 @@ struct at803x_context {
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u16 led_control;
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};
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@ -141,7 +103,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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static int at803x_write_page(struct phy_device *phydev, int page)
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{
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int mask;
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@@ -960,6 +1016,105 @@ static int at8035_probe(struct phy_devic
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@@ -960,6 +1010,109 @@ static int at8035_probe(struct phy_devic
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return at8035_parse_dt(phydev);
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}
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@ -171,7 +133,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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+static int ipq5018_config_init(struct phy_device *phydev)
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+{
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+ struct ipq5018_priv *priv = phydev->priv;
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+ u16 val = 0;
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+ u16 val;
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+
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+ /*
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+ * set LDO efuse: first temporarily store ANA_DAC_FILTER value from
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@ -184,11 +146,11 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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+ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT);
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+ at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val);
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+
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+ /* set 8023AZ CTRL values */
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL1,
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+ IPQ5018_PHY_PCS_AZ_CTRL1_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL2,
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+ IPQ5018_PHY_PCS_AZ_CTRL2_VAL);
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+ /* set 8023AZ EEE TX and RX timer values */
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_TX_TIMER,
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+ IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_RX_TIMER,
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+ IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL);
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+
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+ /* set MSE threshold values */
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+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1,
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@ -212,6 +174,10 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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+
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+static void ipq5018_link_change_notify(struct phy_device *phydev)
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+{
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+ /*
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+ * Reset the FIFO buffer upon link disconnects to clear any residual data
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+ * which may cause issues with the FIFO which it cannot recover from.
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+ */
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+ mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr,
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+ IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET,
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+ phydev->link ? IPQ5018_PHY_FIFO_RESET : 0);
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@ -231,7 +197,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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+ "qcom,dac-preset-short-cable");
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+
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+ priv->rst = devm_reset_control_array_get_exclusive(dev);
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+ if (IS_ERR_OR_NULL(priv->rst))
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+ if (IS_ERR(priv->rst))
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+ return dev_err_probe(dev, PTR_ERR(priv->rst),
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+ "failed to acquire reset\n");
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+
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@ -247,7 +213,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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static struct phy_driver at803x_driver[] = {
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{
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/* Qualcomm Atheros AR8035 */
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@@ -1052,6 +1207,19 @@ static struct phy_driver at803x_driver[]
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@@ -1052,6 +1205,19 @@ static struct phy_driver at803x_driver[]
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.soft_reset = genphy_soft_reset,
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.config_aneg = at803x_config_aneg,
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}, {
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@ -267,7 +233,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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/* Qualcomm Atheros QCA9561 */
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PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
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.name = "Qualcomm Atheros QCA9561 built-in PHY",
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@@ -1077,6 +1245,7 @@ static const struct mdio_device_id __may
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@@ -1077,6 +1243,7 @@ static const struct mdio_device_id __may
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{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
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{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
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{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
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@ -1,11 +1,7 @@
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From 97a159dd7747724619e54cb3460d9b8d4ed08be7 Mon Sep 17 00:00:00 2001
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From 1e2261a669a9596ba435c6fe524e026bac0f0e2f Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Mon, 02 Jun 2025 12:50:40 +0400
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Subject: [PATCH v3 4/5] arm64: dts: qcom: ipq5018: Add MDIO buses
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MIME-Version: 1.0
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Content-Type: text/plain; charset="utf-8"
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Content-Transfer-Encoding: 7bit
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Message-Id: <20250602-ipq5018-ge-phy-v3-4-0d8f39f402a6@outlook.com>
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Date: Mon, 30 Jun 2025 16:35:01 +0400
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Subject: arm64: dts: qcom: ipq5018: Add MDIO buses
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IPQ5018 contains two mdio buses of which one bus is used to control the
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SoC's internal GE PHY, while the other bus is connected to external PHYs
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@ -16,13 +12,17 @@ simply add the mdio nodes for them.
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-2-01be06378c15@outlook.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
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1 file changed, 24 insertions(+)
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(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -191,6 +191,30 @@
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@@ -185,6 +185,30 @@
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status = "disabled";
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};
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@ -50,6 +50,6 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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+ status = "disabled";
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+ };
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+
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cmn_pll: clock-controller@9b000 {
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compatible = "qcom,ipq9574-cmn-pll";
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reg = <0x0009b000 0x800>;
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qfprom: qfprom@a0000 {
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compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
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reg = <0x000a0000 0x1000>;
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@ -1,11 +1,7 @@
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From 1b733e878ac1292c6e0f2e9a49685b80c35619b0 Mon Sep 17 00:00:00 2001
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From f5f2b835e316df29b89e28ed7e467df473932e8d Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Mon, 02 Jun 2025 12:50:41 +0400
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Subject: [PATCH v3 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus
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MIME-Version: 1.0
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Content-Type: text/plain; charset="utf-8"
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Content-Transfer-Encoding: 7bit
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Message-Id: <20250602-ipq5018-ge-phy-v3-5-0d8f39f402a6@outlook.com>
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Date: Mon, 30 Jun 2025 16:35:02 +0400
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Subject: arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus
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The IPQ5018 SoC contains an internal GE PHY, always at phy address 7.
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As such, let's add the GE PHY node to the SoC dtsi.
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@ -20,16 +16,20 @@ So let's create two DT fixed clocks and register them in the GCC node.
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-3-01be06378c15@outlook.com
|
||||
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 26 +++++++++++++++++++++++---
|
||||
1 file changed, 23 insertions(+), 3 deletions(-)
|
||||
|
||||
(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -23,6 +23,18 @@
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
@@ -17,6 +17,18 @@
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks {
|
||||
+ gephy_rx_clk: gephy-rx-clk {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
|
|
@ -45,7 +45,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
sleep_clk: sleep-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
@@ -193,7 +205,8 @@
|
||||
@@ -187,7 +199,8 @@
|
||||
|
||||
mdio0: mdio@88000 {
|
||||
compatible = "qcom,ipq5018-mdio";
|
||||
|
|
@ -55,7 +55,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@@ -201,6 +214,13 @@
|
||||
@@ -195,6 +208,13 @@
|
||||
clock-names = "gcc_mdio_ahb_clk";
|
||||
|
||||
status = "disabled";
|
||||
|
|
@ -69,7 +69,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
};
|
||||
|
||||
mdio1: mdio@90000 {
|
||||
@@ -395,8 +415,8 @@
|
||||
@@ -346,8 +366,8 @@
|
||||
<&pcie0_phy>,
|
||||
<&pcie1_phy>,
|
||||
<0>,
|
||||
|
|
@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
---
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -341,6 +341,16 @@
|
||||
@@ -385,6 +385,16 @@
|
||||
reg = <0x01937000 0x21000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
---
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -296,6 +296,30 @@
|
||||
@@ -340,6 +340,30 @@
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
---
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -257,6 +257,14 @@
|
||||
@@ -301,6 +301,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
---
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -420,6 +420,16 @@
|
||||
@@ -464,6 +464,16 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
---
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -444,6 +444,21 @@
|
||||
@@ -488,6 +488,21 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -459,6 +459,36 @@
|
||||
@@ -503,6 +503,36 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -20,10 +20,10 @@ Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
|
|||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
sleep_clk: sleep-clk {
|
||||
gephy_rx_clk: gephy-rx-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
@@ -185,6 +191,17 @@
|
||||
clock-frequency = <125000000>;
|
||||
@@ -229,6 +235,17 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue