mirror of
https://github.com/steve-m/hsdaohSDR.git
synced 2025-12-10 05:14:37 +01:00
initial commit
This commit is contained in:
Steve Markgraf
commit
a6f6bbb0bf
22 changed files with 198687 additions and 0 deletions
133
hsdaohSDR_RDA5815S/0.1/hsdaoh_sdr.kicad_dru
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133
hsdaohSDR_RDA5815S/0.1/hsdaoh_sdr.kicad_dru
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@ -0,0 +1,133 @@
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|||
(version 1)
|
||||
# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '<project>.kicad_dru' file).
|
||||
#
|
||||
# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
|
||||
#
|
||||
# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
|
||||
#
|
||||
# Inspiration
|
||||
# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
|
||||
# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)
|
||||
|
||||
# TODO new rule: NPTH pads.
|
||||
# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
|
||||
# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."
|
||||
|
||||
# TODO: new rule for plated slots: min diameter/width 0.5mm
|
||||
# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."
|
||||
|
||||
# TODO new rule: non-plated slots: min diameter/width 1.0mm
|
||||
# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
|
||||
|
||||
(rule "Track width, outer layer (1oz copper)"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint track_width (min 0.127mm))
|
||||
)
|
||||
|
||||
(rule "Track spacing, outer layer (1oz copper)"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type")
|
||||
(constraint clearance (min 0.127mm))
|
||||
)
|
||||
|
||||
(rule "Track width, inner layer"
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint track_width (min 0.09mm))
|
||||
)
|
||||
|
||||
(rule "Track spacing, inner layer"
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type")
|
||||
(constraint clearance (min 0.09mm))
|
||||
)
|
||||
|
||||
(rule "Silkscreen text"
|
||||
(layer "?.Silkscreen")
|
||||
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
|
||||
(constraint text_thickness (min 0.15mm))
|
||||
(constraint text_height (min 1mm))
|
||||
)
|
||||
|
||||
(rule "Pad to Silkscreen"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
|
||||
(constraint silk_clearance (min 0.15mm))
|
||||
)
|
||||
|
||||
(rule "Edge (routed) to track clearance"
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint edge_clearance (min 0.3mm))
|
||||
)
|
||||
|
||||
#(rule "Edge (v-cut) to track clearance"
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||||
# (condition "A.Type == 'track'")
|
||||
# (constraint edge_clearance (min 0.4mm))
|
||||
#)
|
||||
|
||||
# JLCPCB restrictions ambiguous:
|
||||
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
|
||||
# This rule handles diameter minimum and maximum for ALL holes.
|
||||
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
|
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(rule "Hole diameter"
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(constraint hole_size (min 0.2mm) (max 6.3mm))
|
||||
)
|
||||
|
||||
(rule "Hole (NPTH) diameter"
|
||||
(layer outer)
|
||||
(condition "!A.isPlated()")
|
||||
(constraint hole_size (min 0.5mm))
|
||||
)
|
||||
|
||||
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
|
||||
(rule "Hole (castellated) diameter"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
|
||||
(constraint hole_size (min 0.6mm))
|
||||
)
|
||||
|
||||
# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
|
||||
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
|
||||
(rule "Annular ring width (via and PTH)"
|
||||
(layer outer)
|
||||
(condition "A.isPlated()")
|
||||
(constraint annular_width (min 0.075mm))
|
||||
)
|
||||
|
||||
(rule "Clearance: hole to hole (perimeter), different nets"
|
||||
(layer outer)
|
||||
(condition "A.Net != B.Net")
|
||||
(constraint hole_to_hole (min 0.5mm))
|
||||
)
|
||||
|
||||
(rule "Clearance: hole to hole (perimeter), same net"
|
||||
(layer outer)
|
||||
(condition "A.Net == B.Net")
|
||||
(constraint hole_to_hole (min 0.254mm))
|
||||
)
|
||||
|
||||
(rule "Clearance: track to NPTH hole (perimeter)"
|
||||
# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
|
||||
(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint hole_clearance (min 0.254mm))
|
||||
)
|
||||
|
||||
(rule "Clearance: track to PTH hole perimeter"
|
||||
(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint hole_clearance (min 0.33mm))
|
||||
)
|
||||
|
||||
# TODO: try combining with rule "Clearance: PTH to track, different nets"
|
||||
(rule "Clearance: track to pad"
|
||||
(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint clearance (min 0.2mm))
|
||||
)
|
||||
|
||||
(rule "Clearance: pad/via to pad/via"
|
||||
(layer outer)
|
||||
# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
|
||||
(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
|
||||
(constraint clearance (min 0.127mm))
|
||||
)
|
||||
|
||||
33795
hsdaohSDR_RDA5815S/0.1/hsdaoh_sdr.kicad_pcb
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33795
hsdaohSDR_RDA5815S/0.1/hsdaoh_sdr.kicad_pcb
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File diff suppressed because it is too large
Load diff
77
hsdaohSDR_RDA5815S/0.1/hsdaoh_sdr.kicad_prl
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77
hsdaohSDR_RDA5815S/0.1/hsdaoh_sdr.kicad_prl
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@ -0,0 +1,77 @@
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|||
{
|
||||
"board": {
|
||||
"active_layer": 0,
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": false,
|
||||
"hidden_netclasses": [],
|
||||
"hidden_nets": [],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
"opacity": {
|
||||
"images": 0.6,
|
||||
"pads": 1.0,
|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
},
|
||||
"selection_filter": {
|
||||
"dimensions": true,
|
||||
"footprints": true,
|
||||
"graphics": true,
|
||||
"keepouts": true,
|
||||
"lockedItems": true,
|
||||
"otherItems": true,
|
||||
"pads": true,
|
||||
"text": true,
|
||||
"tracks": true,
|
||||
"vias": true,
|
||||
"zones": true
|
||||
},
|
||||
"visible_items": [
|
||||
0,
|
||||
1,
|
||||
2,
|
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3,
|
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4,
|
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5,
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8,
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9,
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10,
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11,
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12,
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13,
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15,
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16,
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17,
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18,
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19,
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20,
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22,
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23,
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25,
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|
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|
||||
35,
|
||||
36,
|
||||
39,
|
||||
40
|
||||
],
|
||||
"visible_layers": "0001030_80000001",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"meta": {
|
||||
"filename": "hsdaoh_sdr.kicad_prl",
|
||||
"version": 3
|
||||
},
|
||||
"project": {
|
||||
"files": []
|
||||
}
|
||||
}
|
||||
504
hsdaohSDR_RDA5815S/0.1/hsdaoh_sdr.kicad_pro
Normal file
504
hsdaohSDR_RDA5815S/0.1/hsdaoh_sdr.kicad_pro
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|
|
@ -0,0 +1,504 @@
|
|||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.038099999999999995,
|
||||
"copper_line_width": 0.254,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.524,
|
||||
"copper_text_size_v": 1.524,
|
||||
"copper_text_thickness": 0.30479999999999996,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 1.0,
|
||||
"height": 1.7,
|
||||
"width": 1.7
|
||||
},
|
||||
"silk_line_width": 0.15239999999999998,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 0.8128,
|
||||
"silk_text_size_v": 0.8128,
|
||||
"silk_text_thickness": 0.15239999999999998,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"min_clearance": 0.25
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [
|
||||
{
|
||||
"gap": 0.0,
|
||||
"via_gap": 0.0,
|
||||
"width": 0.0
|
||||
}
|
||||
],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_thickness": "warning",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.5,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.0,
|
||||
"min_microvia_drill": 0.0,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_text_height": 0.7999999999999999,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.127,
|
||||
"min_via_annular_width": 0.09999999999999999,
|
||||
"min_via_diameter": 0.6,
|
||||
"solder_mask_clearance": 0.0,
|
||||
"solder_mask_min_width": 0.0,
|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"teardrop_options": [
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 5,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_onpadsmd": true,
|
||||
"td_onroundshapesonly": false,
|
||||
"td_ontrackend": false,
|
||||
"td_onviapad": true
|
||||
}
|
||||
],
|
||||
"teardrop_parameters": [
|
||||
{
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_target_name": "td_round_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_target_name": "td_rect_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_target_name": "td_track_end",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
}
|
||||
],
|
||||
"track_widths": [
|
||||
0.0,
|
||||
0.15,
|
||||
0.2,
|
||||
0.3,
|
||||
0.4,
|
||||
0.6,
|
||||
0.9
|
||||
],
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
},
|
||||
{
|
||||
"diameter": 0.6,
|
||||
"drill": 0.3
|
||||
},
|
||||
{
|
||||
"diameter": 0.9,
|
||||
"drill": 0.4
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false
|
||||
},
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"conflicting_netclasses": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "hsdaoh_sdr.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.127,
|
||||
"diff_pair_gap": 0.254,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.1524,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.6858,
|
||||
"microvia_drill": 0.3302,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.127,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"1372fd37-1466-46f3-b546-7a84e17b7d6b",
|
||||
""
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
5444
hsdaohSDR_RDA5815S/0.1/hsdaoh_sdr.kicad_sch
Normal file
5444
hsdaohSDR_RDA5815S/0.1/hsdaoh_sdr.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
122
hsdaohSDR_RDA5815S/0.1/rda5815S.kicad_sym
Normal file
122
hsdaohSDR_RDA5815S/0.1/rda5815S.kicad_sym
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
(kicad_symbol_lib (version 20220914) (generator kicad_symbol_editor)
|
||||
(symbol "RDA5815S" (in_bom yes) (on_board yes)
|
||||
(property "Reference" "U?" (at 0 21.59 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Value" "" (at 0 -3.81 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 0 -3.81 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 0 -3.81 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(symbol "RDA5815S_1_1"
|
||||
(rectangle (start -15.24 20.32) (end 15.24 -19.05)
|
||||
(stroke (width 0) (type default))
|
||||
(fill (type background))
|
||||
)
|
||||
(pin power_in line (at 17.78 17.78 180) (length 2.54)
|
||||
(name "GND" (effects (font (size 1.27 1.27))))
|
||||
(number "1" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin no_connect line (at 8.89 -21.59 90) (length 2.54)
|
||||
(name "NC" (effects (font (size 1.27 1.27))))
|
||||
(number "10" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin power_in line (at -17.78 8.89 0) (length 2.54)
|
||||
(name "Vcc" (effects (font (size 1.27 1.27))))
|
||||
(number "11" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin bidirectional line (at -17.78 -6.35 0) (length 2.54)
|
||||
(name "XTAL" (effects (font (size 1.27 1.27))))
|
||||
(number "12" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin bidirectional line (at -17.78 -8.89 0) (length 2.54)
|
||||
(name "REFCLK" (effects (font (size 1.27 1.27))))
|
||||
(number "13" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin output line (at -2.54 -21.59 90) (length 2.54)
|
||||
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|
||||
(number "14" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin output line (at 17.78 -6.35 180) (length 2.54)
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||||
(name "BBIP" (effects (font (size 1.27 1.27))))
|
||||
(number "15" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin output line (at 17.78 -8.89 180) (length 2.54)
|
||||
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|
||||
(number "16" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin output line (at 17.78 -11.43 180) (length 2.54)
|
||||
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||||
(number "17" (effects (font (size 1.27 1.27))))
|
||||
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|
||||
(pin output line (at 17.78 -13.97 180) (length 2.54)
|
||||
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|
||||
(number "18" (effects (font (size 1.27 1.27))))
|
||||
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|
||||
(pin power_in line (at -17.78 6.35 0) (length 2.54)
|
||||
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|
||||
(number "19" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin input line (at -17.78 17.78 0) (length 2.54)
|
||||
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|
||||
(number "2" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin no_connect line (at 11.43 -21.59 90) (length 2.54)
|
||||
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||||
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|
||||
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|
||||
(pin bidirectional line (at 17.78 1.27 180) (length 2.54)
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|
||||
(number "21" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin input line (at 17.78 3.81 180) (length 2.54)
|
||||
(name "SCLK" (effects (font (size 1.27 1.27))))
|
||||
(number "22" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin power_in line (at -17.78 3.81 0) (length 2.54)
|
||||
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|
||||
(number "23" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin input line (at -7.62 -21.59 90) (length 2.54)
|
||||
(name "PDN" (effects (font (size 1.27 1.27))))
|
||||
(number "24" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin power_in line (at 17.78 7.62 180) (length 2.54)
|
||||
(name "GND_PAD" (effects (font (size 1.27 1.27))))
|
||||
(number "25" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin power_in line (at 17.78 15.24 180) (length 2.54)
|
||||
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|
||||
(number "3" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin output line (at -17.78 15.24 0) (length 2.54)
|
||||
(name "LOOP" (effects (font (size 1.27 1.27))))
|
||||
(number "4" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin power_in line (at 17.78 12.7 180) (length 2.54)
|
||||
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|
||||
(number "5" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin power_in line (at 17.78 10.16 180) (length 2.54)
|
||||
(name "ADD" (effects (font (size 1.27 1.27))))
|
||||
(number "6" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin input line (at 17.78 -1.27 180) (length 2.54)
|
||||
(name "AGC" (effects (font (size 1.27 1.27))))
|
||||
(number "7" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin no_connect line (at 3.81 -21.59 90) (length 2.54)
|
||||
(name "NC" (effects (font (size 1.27 1.27))))
|
||||
(number "8" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin no_connect line (at 6.35 -21.59 90) (length 2.54)
|
||||
(name "NC" (effects (font (size 1.27 1.27))))
|
||||
(number "9" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
133
hsdaohSDR_RDA5815S/0.1b/hsdaoh_sdr.kicad_dru
Normal file
133
hsdaohSDR_RDA5815S/0.1b/hsdaoh_sdr.kicad_dru
Normal file
|
|
@ -0,0 +1,133 @@
|
|||
(version 1)
|
||||
# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '<project>.kicad_dru' file).
|
||||
#
|
||||
# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
|
||||
#
|
||||
# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
|
||||
#
|
||||
# Inspiration
|
||||
# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
|
||||
# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)
|
||||
|
||||
# TODO new rule: NPTH pads.
|
||||
# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
|
||||
# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."
|
||||
|
||||
# TODO: new rule for plated slots: min diameter/width 0.5mm
|
||||
# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."
|
||||
|
||||
# TODO new rule: non-plated slots: min diameter/width 1.0mm
|
||||
# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
|
||||
|
||||
(rule "Track width, outer layer (1oz copper)"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint track_width (min 0.127mm))
|
||||
)
|
||||
|
||||
(rule "Track spacing, outer layer (1oz copper)"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type")
|
||||
(constraint clearance (min 0.127mm))
|
||||
)
|
||||
|
||||
(rule "Track width, inner layer"
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint track_width (min 0.09mm))
|
||||
)
|
||||
|
||||
(rule "Track spacing, inner layer"
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type")
|
||||
(constraint clearance (min 0.09mm))
|
||||
)
|
||||
|
||||
(rule "Silkscreen text"
|
||||
(layer "?.Silkscreen")
|
||||
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
|
||||
(constraint text_thickness (min 0.15mm))
|
||||
(constraint text_height (min 1mm))
|
||||
)
|
||||
|
||||
(rule "Pad to Silkscreen"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
|
||||
(constraint silk_clearance (min 0.15mm))
|
||||
)
|
||||
|
||||
(rule "Edge (routed) to track clearance"
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint edge_clearance (min 0.3mm))
|
||||
)
|
||||
|
||||
#(rule "Edge (v-cut) to track clearance"
|
||||
# (condition "A.Type == 'track'")
|
||||
# (constraint edge_clearance (min 0.4mm))
|
||||
#)
|
||||
|
||||
# JLCPCB restrictions ambiguous:
|
||||
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
|
||||
# This rule handles diameter minimum and maximum for ALL holes.
|
||||
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
|
||||
(rule "Hole diameter"
|
||||
(constraint hole_size (min 0.2mm) (max 6.3mm))
|
||||
)
|
||||
|
||||
(rule "Hole (NPTH) diameter"
|
||||
(layer outer)
|
||||
(condition "!A.isPlated()")
|
||||
(constraint hole_size (min 0.5mm))
|
||||
)
|
||||
|
||||
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
|
||||
(rule "Hole (castellated) diameter"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
|
||||
(constraint hole_size (min 0.6mm))
|
||||
)
|
||||
|
||||
# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
|
||||
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
|
||||
(rule "Annular ring width (via and PTH)"
|
||||
(layer outer)
|
||||
(condition "A.isPlated()")
|
||||
(constraint annular_width (min 0.075mm))
|
||||
)
|
||||
|
||||
(rule "Clearance: hole to hole (perimeter), different nets"
|
||||
(layer outer)
|
||||
(condition "A.Net != B.Net")
|
||||
(constraint hole_to_hole (min 0.5mm))
|
||||
)
|
||||
|
||||
(rule "Clearance: hole to hole (perimeter), same net"
|
||||
(layer outer)
|
||||
(condition "A.Net == B.Net")
|
||||
(constraint hole_to_hole (min 0.254mm))
|
||||
)
|
||||
|
||||
(rule "Clearance: track to NPTH hole (perimeter)"
|
||||
# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
|
||||
(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint hole_clearance (min 0.254mm))
|
||||
)
|
||||
|
||||
(rule "Clearance: track to PTH hole perimeter"
|
||||
(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint hole_clearance (min 0.33mm))
|
||||
)
|
||||
|
||||
# TODO: try combining with rule "Clearance: PTH to track, different nets"
|
||||
(rule "Clearance: track to pad"
|
||||
(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint clearance (min 0.2mm))
|
||||
)
|
||||
|
||||
(rule "Clearance: pad/via to pad/via"
|
||||
(layer outer)
|
||||
# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
|
||||
(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
|
||||
(constraint clearance (min 0.127mm))
|
||||
)
|
||||
|
||||
67007
hsdaohSDR_RDA5815S/0.1b/hsdaoh_sdr.kicad_pcb
Normal file
67007
hsdaohSDR_RDA5815S/0.1b/hsdaoh_sdr.kicad_pcb
Normal file
File diff suppressed because it is too large
Load diff
83
hsdaohSDR_RDA5815S/0.1b/hsdaoh_sdr.kicad_prl
Normal file
83
hsdaohSDR_RDA5815S/0.1b/hsdaoh_sdr.kicad_prl
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
{
|
||||
"board": {
|
||||
"active_layer": 31,
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": true,
|
||||
"hidden_netclasses": [],
|
||||
"hidden_nets": [],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
"opacity": {
|
||||
"images": 0.6,
|
||||
"pads": 1.0,
|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
},
|
||||
"selection_filter": {
|
||||
"dimensions": true,
|
||||
"footprints": true,
|
||||
"graphics": true,
|
||||
"keepouts": true,
|
||||
"lockedItems": true,
|
||||
"otherItems": true,
|
||||
"pads": true,
|
||||
"text": true,
|
||||
"tracks": true,
|
||||
"vias": true,
|
||||
"zones": true
|
||||
},
|
||||
"visible_items": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30,
|
||||
32,
|
||||
33,
|
||||
34,
|
||||
35,
|
||||
36,
|
||||
39,
|
||||
40
|
||||
],
|
||||
"visible_layers": "0001030_80000001",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"git": {
|
||||
"repo_password": "",
|
||||
"repo_type": "",
|
||||
"repo_username": "",
|
||||
"ssh_key": ""
|
||||
},
|
||||
"meta": {
|
||||
"filename": "hsdaoh_sdr.kicad_prl",
|
||||
"version": 3
|
||||
},
|
||||
"project": {
|
||||
"files": []
|
||||
}
|
||||
}
|
||||
549
hsdaohSDR_RDA5815S/0.1b/hsdaoh_sdr.kicad_pro
Normal file
549
hsdaohSDR_RDA5815S/0.1b/hsdaoh_sdr.kicad_pro
Normal file
|
|
@ -0,0 +1,549 @@
|
|||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"apply_defaults_to_fp_fields": false,
|
||||
"apply_defaults_to_fp_shapes": false,
|
||||
"apply_defaults_to_fp_text": false,
|
||||
"board_outline_line_width": 0.0381,
|
||||
"copper_line_width": 0.254,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.524,
|
||||
"copper_text_size_v": 1.524,
|
||||
"copper_text_thickness": 0.3048,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.05,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.1,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.1,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 1.0,
|
||||
"height": 1.7,
|
||||
"width": 1.7
|
||||
},
|
||||
"silk_line_width": 0.1524,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 0.8128,
|
||||
"silk_text_size_v": 0.8128,
|
||||
"silk_text_thickness": 0.1524,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"min_clearance": 0.25
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [
|
||||
{
|
||||
"gap": 0.0,
|
||||
"via_gap": 0.0,
|
||||
"width": 0.0
|
||||
}
|
||||
],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_symbol_mismatch": "warning",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_thickness": "warning",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.5,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.0,
|
||||
"min_microvia_drill": 0.0,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_text_height": 0.8,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.127,
|
||||
"min_via_annular_width": 0.1,
|
||||
"min_via_diameter": 0.6,
|
||||
"solder_mask_clearance": 0.0,
|
||||
"solder_mask_min_width": 0.0,
|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"teardrop_options": [
|
||||
{
|
||||
"td_onpadsmd": true,
|
||||
"td_onroundshapesonly": false,
|
||||
"td_ontrackend": false,
|
||||
"td_onviapad": true
|
||||
}
|
||||
],
|
||||
"teardrop_parameters": [
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_round_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_rect_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_track_end",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
}
|
||||
],
|
||||
"track_widths": [
|
||||
0.0,
|
||||
0.15,
|
||||
0.2,
|
||||
0.3,
|
||||
0.4,
|
||||
0.6,
|
||||
0.9
|
||||
],
|
||||
"tuning_pattern_settings": {
|
||||
"diff_pair_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 1.0
|
||||
},
|
||||
"diff_pair_skew_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 0.6
|
||||
},
|
||||
"single_track_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 0.6
|
||||
}
|
||||
},
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
},
|
||||
{
|
||||
"diameter": 0.6,
|
||||
"drill": 0.3
|
||||
},
|
||||
{
|
||||
"diameter": 0.9,
|
||||
"drill": 0.4
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false
|
||||
},
|
||||
"ipc2581": {
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": ""
|
||||
},
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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5444
hsdaohSDR_RDA5815S/0.1b/hsdaoh_sdr.kicad_sch
Normal file
5444
hsdaohSDR_RDA5815S/0.1b/hsdaoh_sdr.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
226
hsdaohSDR_RDA5815S/0.1b/rda5815S.kicad_sym
Normal file
226
hsdaohSDR_RDA5815S/0.1b/rda5815S.kicad_sym
Normal file
|
|
@ -0,0 +1,226 @@
|
|||
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|
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
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||||
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||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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||||
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34931
hsdaohSDR_RT7x0/hsdaoh_sdr.kicad_pcb
Normal file
34931
hsdaohSDR_RT7x0/hsdaoh_sdr.kicad_pcb
Normal file
File diff suppressed because it is too large
Load diff
77
hsdaohSDR_RT7x0/hsdaoh_sdr.kicad_prl
Normal file
77
hsdaohSDR_RT7x0/hsdaoh_sdr.kicad_prl
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
{
|
||||
"board": {
|
||||
"active_layer": 31,
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": false,
|
||||
"hidden_netclasses": [],
|
||||
"hidden_nets": [],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
"opacity": {
|
||||
"images": 0.6,
|
||||
"pads": 1.0,
|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
},
|
||||
"selection_filter": {
|
||||
"dimensions": true,
|
||||
"footprints": true,
|
||||
"graphics": true,
|
||||
"keepouts": true,
|
||||
"lockedItems": true,
|
||||
"otherItems": true,
|
||||
"pads": true,
|
||||
"text": true,
|
||||
"tracks": true,
|
||||
"vias": true,
|
||||
"zones": true
|
||||
},
|
||||
"visible_items": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30,
|
||||
32,
|
||||
33,
|
||||
34,
|
||||
35,
|
||||
36,
|
||||
39,
|
||||
40
|
||||
],
|
||||
"visible_layers": "0001030_80000001",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"meta": {
|
||||
"filename": "hsdaoh_sdr.kicad_prl",
|
||||
"version": 3
|
||||
},
|
||||
"project": {
|
||||
"files": []
|
||||
}
|
||||
}
|
||||
506
hsdaohSDR_RT7x0/hsdaoh_sdr.kicad_pro
Normal file
506
hsdaohSDR_RT7x0/hsdaoh_sdr.kicad_pro
Normal file
|
|
@ -0,0 +1,506 @@
|
|||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.038099999999999995,
|
||||
"copper_line_width": 0.254,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.524,
|
||||
"copper_text_size_v": 1.524,
|
||||
"copper_text_thickness": 0.30479999999999996,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 1.0,
|
||||
"height": 1.7,
|
||||
"width": 1.7
|
||||
},
|
||||
"silk_line_width": 0.15239999999999998,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 0.8128,
|
||||
"silk_text_size_v": 0.8128,
|
||||
"silk_text_thickness": 0.15239999999999998,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"min_clearance": 0.25
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [
|
||||
{
|
||||
"gap": 0.0,
|
||||
"via_gap": 0.0,
|
||||
"width": 0.0
|
||||
}
|
||||
],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_thickness": "warning",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.5,
|
||||
"min_hole_clearance": 0.25,
|
||||
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|
||||
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|
||||
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|
||||
"min_resolved_spokes": 2,
|
||||
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|
||||
"min_text_height": 0.7999999999999999,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.127,
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
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|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
],
|
||||
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|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
{
|
||||
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|
||||
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|
||||
}
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
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|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
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|
||||
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|
||||
"no_connect_connected": "warning",
|
||||
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|
||||
"pin_not_connected": "error",
|
||||
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|
||||
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|
||||
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|
||||
"similar_labels": "warning",
|
||||
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|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": [
|
||||
"rda5815S"
|
||||
]
|
||||
},
|
||||
"meta": {
|
||||
"filename": "hsdaoh_sdr.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.127,
|
||||
"diff_pair_gap": 0.254,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.1524,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.6858,
|
||||
"microvia_drill": 0.3302,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.127,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "./",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
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|
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5998
hsdaohSDR_RT7x0/hsdaoh_sdr.kicad_sch
Normal file
5998
hsdaohSDR_RT7x0/hsdaoh_sdr.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
229
hsdaohSDR_RT7x0/rda5815S.kicad_sym
Normal file
229
hsdaohSDR_RT7x0/rda5815S.kicad_sym
Normal file
|
|
@ -0,0 +1,229 @@
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|||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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1721
hsdaohSDR_STV6110/Tuner.kicad_sch
Normal file
1721
hsdaohSDR_STV6110/Tuner.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
36020
hsdaohSDR_STV6110/hsdaoh_sdr.kicad_pcb
Normal file
36020
hsdaohSDR_STV6110/hsdaoh_sdr.kicad_pcb
Normal file
File diff suppressed because it is too large
Load diff
510
hsdaohSDR_STV6110/hsdaoh_sdr.kicad_pro
Normal file
510
hsdaohSDR_STV6110/hsdaoh_sdr.kicad_pro
Normal file
|
|
@ -0,0 +1,510 @@
|
|||
{
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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||||
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||||
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||||
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||||
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4794
hsdaohSDR_STV6110/hsdaoh_sdr.kicad_sch
Normal file
4794
hsdaohSDR_STV6110/hsdaoh_sdr.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
384
hsdaohSDR_STV6110/rda5815S.kicad_sym
Normal file
384
hsdaohSDR_STV6110/rda5815S.kicad_sym
Normal file
|
|
@ -0,0 +1,384 @@
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||||
)
|
||||
Loading…
Add table
Reference in a new issue