mirror of
https://github.com/steve-m/hsdaoh.git
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135 lines
2.1 KiB
C
135 lines
2.1 KiB
C
#ifndef __HSDAOH_PRIVATE_H
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#define __HSDAOH_PRIVATE_H
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enum hsdaoh_async_status {
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HSDAOH_INACTIVE = 0,
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HSDAOH_CANCELING,
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HSDAOH_RUNNING
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};
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struct llist {
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uint8_t *data;
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size_t len;
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uint16_t sid;
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uint16_t format;
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uint32_t srate;
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struct llist *next;
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};
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struct hsdaoh_dev {
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libusb_context *ctx;
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struct libusb_device_handle *devh;
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hsdaoh_read_cb_t cb;
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void *cb_ctx;
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enum hsdaoh_async_status async_status;
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int async_cancel;
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uint16_t vid;
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uint16_t pid;
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/* UVC related */
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uvc_context_t *uvc_ctx;
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uvc_device_t *uvc_dev;
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uvc_device_handle_t *uvc_devh;
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int hid_interface;
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uint8_t edid_seq_cnt;
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int frames_since_error;
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int discard_start_frames;
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unsigned int in_order_cnt;
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uint16_t last_frame_cnt;
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uint16_t last_crc[2];
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uint16_t idle_cnt;
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bool stream_synced;
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unsigned int width, height, fps;
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bool output_float;
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iqconverter_float_t *cnv_f;
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/* status */
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int dev_lost;
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bool driver_active;
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unsigned int xfer_errors;
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char manufact[256];
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char product[256];
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/* buffering */
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pthread_t hsdaoh_output_worker_thread;
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pthread_mutex_t ll_mutex;
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pthread_cond_t cond;
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unsigned int highest_numq;
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unsigned int global_numq;
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struct llist *ll_buffers;
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unsigned int llbuf_num;
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};
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enum
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{
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RAW_8BIT,
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RAW_16BIT,
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RAW_24BIT,
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RAW_32BIT,
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RAW_64BIT,
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PIO_1BIT,
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PIO_2BIT,
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PIO_3BIT,
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PIO_4BIT,
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PIO_5BIT,
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PIO_6BIT,
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PIO_7BIT,
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PIO_8BIT,
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PIO_8BIT_DUAL,
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PIO_8BIT_IQ,
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PIO_9BIT,
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PIO_10BIT,
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PIO_10BIT_DUAL,
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PIO_10BIT_IQ,
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PIO_11BIT,
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PIO_12BIT,
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PIO_12BIT_DUAL,
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PIO_12BIT_IQ,
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PIO_13BIT,
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PIO_14BIT,
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PIO_14BIT_DUAL,
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PIO_14BIT_IQ,
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PIO_15BIT,
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PIO_16BIT,
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PIO_16BIT_DUAL,
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PIO_16BIT_IQ,
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PIO_17BIT,
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PIO_18BIT,
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PIO_19BIT,
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PIO_20BIT,
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PIO_24BIT,
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PIO_24BIT_IQ,
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PIO_28BIT,
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PIO_32BIT,
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PIO_32BIT_IQ,
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PIO_PCM1802_AUDIO,
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// Placeholder for internal ADC data from pico
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FPGA_1BIT = 256,
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FPGA_2BIT,
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FPGA_3BIT,
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FPGA_4BIT,
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FPGA_5BIT,
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FPGA_6BIT,
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FPGA_7BIT,
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FPGA_8BIT,
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FPGA_8BIT_DUAL,
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FPGA_8BIT_DDR,
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FPGA_8BIT_IQ,
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FPGA_9BIT,
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FPGA_10BIT,
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FPGA_10BIT_DUAL,
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FPGA_10BIT_DDR,
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FPGA_10BIT_IQ,
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FPGA_11BIT,
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FPGA_12BIT,
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FPGA_12BIT_DUAL,
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FPGA_12BIT_DDR,
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FPGA_12BIT_IQ,
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};
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#endif
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