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lib: add code to control a data source via EDID RAM
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2 changed files with 47 additions and 0 deletions
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@ -130,6 +130,18 @@ HSDAOH_API int hsdaoh_start_stream(hsdaoh_dev_t *dev,
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*/
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*/
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HSDAOH_API int hsdaoh_stop_stream(hsdaoh_dev_t *dev);
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HSDAOH_API int hsdaoh_stop_stream(hsdaoh_dev_t *dev);
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/*!
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* Write a datagram to the EDID RAM to control a downstream data source.
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* A header with a sequence number and length is prepended to the mesage
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* by the library.
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*
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* \param dev the device handle given by hsdaoh_open()
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* \param data pointer to the datagram
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* \param len length of the datagram, must not exceed 256-2 = 254 bytes
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* due to the prepended header.
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* \return 0 on success
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*/
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HSDAOH_API int hsdaoh_write_edid_cmd_data(hsdaoh_dev_t *dev, uint8_t *data, uint8_t len);
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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@ -84,6 +84,7 @@ struct hsdaoh_dev {
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int hid_interface;
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int hid_interface;
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uint8_t edid_seq_cnt;
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int frames_since_error;
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int frames_since_error;
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int discard_start_frames;
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int discard_start_frames;
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uint16_t last_frame_cnt;
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uint16_t last_frame_cnt;
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@ -181,6 +182,40 @@ int hsdaoh_read_register(hsdaoh_dev_t *dev, uint16_t addr, uint8_t *val)
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return r;
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return r;
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}
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}
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/* Write a datagram to the EDID RAM to control a downstream data source */
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int hsdaoh_write_edid_cmd_data(hsdaoh_dev_t *dev, uint8_t *data, uint8_t len)
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{
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if (!dev || !data || (len > 254))
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return -1;
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/* increment sequence counter and avoid values 0x00 and 0xff */
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dev->edid_seq_cnt++;
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if (!dev->edid_seq_cnt || (dev->edid_seq_cnt == 0xff))
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dev->edid_seq_cnt = 1;
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/* disable I2C access to EDID RAM, reading via I2C will result in a NAK */
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hsdaoh_ms_write_register(dev, 0xf063, 0x00);
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/* switch EDID RAM to 8051 */
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hsdaoh_ms_write_register(dev, 0xf062, 0x80);
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/* store header with sequence counter and length of data */
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hsdaoh_ms_write_register(dev, 0xf900, dev->edid_seq_cnt);
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hsdaoh_ms_write_register(dev, 0xf901, len);
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/* store actual data to the EDID RAM */
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for (uint8_t i = 0; i < len; i++)
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hsdaoh_ms_write_register(dev, 0xf902 + i, data[i]);
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/* switch EDID RAM to DDC I2C slave */
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hsdaoh_ms_write_register(dev, 0xf062, 0x00);
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/* re-enable I2C access to EDID RAM */
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hsdaoh_ms_write_register(dev, 0xf063, 0x08);
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return 0;
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}
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/* Switch the MS2130 to a transparent mode, YUYV data received via HDMI
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/* Switch the MS2130 to a transparent mode, YUYV data received via HDMI
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* will be passed through unmodified */
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* will be passed through unmodified */
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void hsdaoh_ms_enable_transparent_mode(hsdaoh_dev_t *dev)
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void hsdaoh_ms_enable_transparent_mode(hsdaoh_dev_t *dev)
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