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lib: do not overclock flash chip

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Some of the chinese RP2350B boards seem to have issues
when overclocking the QSPI flash too much, so keep
the clock within limits.
This commit is contained in:
Steve Markgraf 2025-03-21 01:12:21 +01:00
parent 5f00c86805
commit 91dff299b5
8 changed files with 32 additions and 8 deletions
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2
apps/counter/counter.c
View file

@ -118,7 +118,7 @@ int main()
{ {
vreg_set_voltage(VREG_VOLTAGE_MAX); vreg_set_voltage(VREG_VOLTAGE_MAX);
sleep_ms(1); sleep_ms(1);
set_sys_clock_khz(SYS_CLK, true); hsdaoh_set_sys_clock_khz(SYS_CLK);
/* set HSTX clock to sysclk/1 */ /* set HSTX clock to sysclk/1 */
hw_write_masked( hw_write_masked(

2
apps/dual_external_adc/dual_external_adc.c
View file

@ -296,7 +296,7 @@ int main()
sleep_ms(1); sleep_ms(1);
#endif #endif
set_sys_clock_khz(SYS_CLK, true); hsdaoh_set_sys_clock_khz(SYS_CLK);
/* set HSTX clock to sysclk/1 */ /* set HSTX clock to sysclk/1 */
hw_write_masked( hw_write_masked(

2
apps/external_adc/external_adc.c
View file

@ -211,7 +211,7 @@ int main()
sleep_ms(1); sleep_ms(1);
#endif #endif
set_sys_clock_khz(SYS_CLK, true); hsdaoh_set_sys_clock_khz(SYS_CLK);
/* set HSTX clock to sysclk/1 */ /* set HSTX clock to sysclk/1 */
hw_write_masked( hw_write_masked(

2
apps/internal_adc/internal_adc.c
View file

@ -134,7 +134,7 @@ int main()
vreg_set_voltage(VREG_VOLTAGE_MAX); vreg_set_voltage(VREG_VOLTAGE_MAX);
sleep_ms(1); sleep_ms(1);
set_sys_clock_khz(SYS_CLK, true); hsdaoh_set_sys_clock_khz(SYS_CLK);
/* set HSTX clock to sysclk/3 */ /* set HSTX clock to sysclk/3 */
hw_write_masked( hw_write_masked(

2
apps/logic_analyzer/logic_analyzer.c
View file

@ -124,7 +124,7 @@ int main()
vreg_set_voltage(VREG_VOLTAGE_MAX); vreg_set_voltage(VREG_VOLTAGE_MAX);
sleep_ms(1); sleep_ms(1);
set_sys_clock_khz(SYS_CLK, true); hsdaoh_set_sys_clock_khz(SYS_CLK);
/* set HSTX clock to sysclk/2 */ /* set HSTX clock to sysclk/2 */
hw_write_masked( hw_write_masked(

2
apps/sdr/sdr.c
View file

@ -146,7 +146,7 @@ int main()
//vreg_set_voltage(VREG_VOLTAGE_1_80); //vreg_set_voltage(VREG_VOLTAGE_1_80);
sleep_ms(1); sleep_ms(1);
#endif #endif
set_sys_clock_khz(SYS_CLK, true); hsdaoh_set_sys_clock_khz(SYS_CLK);
int usbdiv; int usbdiv;
/* set USB clock to clk_sys/n */ /* set USB clock to clk_sys/n */

24
libpicohsdaoh/picohsdaoh.c
View file

@ -36,9 +36,11 @@
#include "hardware/dma.h" #include "hardware/dma.h"
#include "hardware/gpio.h" #include "hardware/gpio.h"
#include "hardware/irq.h" #include "hardware/irq.h"
#include "hardware/clocks.h"
#include "hardware/structs/bus_ctrl.h" #include "hardware/structs/bus_ctrl.h"
#include "hardware/structs/hstx_ctrl.h" #include "hardware/structs/hstx_ctrl.h"
#include "hardware/structs/hstx_fifo.h" #include "hardware/structs/hstx_fifo.h"
#include "hardware/structs/qmi.h"
#include "pico/multicore.h" #include "pico/multicore.h"
#include "pico/stdlib.h" #include "pico/stdlib.h"
#include "data_packet.h" #include "data_packet.h"
@ -309,6 +311,28 @@ int hsdaoh_add_stream(uint16_t stream_id, uint16_t format, uint32_t samplerate,
return 0; return 0;
} }
/* set system clock, without overclocking the QSPI flash */
void hsdaoh_set_sys_clock_khz(uint32_t freq_khz)
{
uint clkdiv = freq_khz/40000;
if (freq_khz % 40000)
clkdiv++;
if (clkdiv < 4)
clkdiv = 4;
else if (clkdiv > 8)
clkdiv = 8;
/* set QSPI clock divider */
hw_write_masked(&qmi_hw->m[0].timing,
clkdiv << QMI_M0_TIMING_CLKDIV_LSB,
QMI_M0_TIMING_CLKDIV_BITS
);
__asm__ __volatile__("dmb sy");
set_sys_clock_khz(freq_khz, true);
}
void hsdaoh_init(int dstrength, int slewrate) void hsdaoh_init(int dstrength, int slewrate)
{ {
for (uint i = 0; i < MAX_STREAMS; i++) for (uint i = 0; i < MAX_STREAMS; i++)

4
libpicohsdaoh/picohsdaoh.h
View file

@ -97,8 +97,8 @@ enum
}; };
void hsdaoh_start(void); void hsdaoh_start(void);
void hsdaoh_init(int dstrength, int slewrate);
void hsdaoh_update_head(int stream_id, int head); void hsdaoh_update_head(int stream_id, int head);
int hsdaoh_add_stream(uint16_t stream_id, uint16_t format, uint32_t samplerate, uint length, uint slices, uint16_t *ringbuf); int hsdaoh_add_stream(uint16_t stream_id, uint16_t format, uint32_t samplerate, uint length, uint slices, uint16_t *ringbuf);
void hsdaoh_set_sys_clock_khz(uint32_t freq_khz);
void hsdaoh_init(int dstrength, int slewrate);
#endif #endif