mirror/hsdaoh-rp2350
1
0
Fork 0
mirror of https://github.com/steve-m/hsdaoh-rp2350.git synced 2025-12-10 07:44:39 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

external_adc: Switch to GP20 for ADC clock

Browse source 
..so that more consecutive pins are available for
attaching an additional audio ADC module.
This commit is contained in:
Steve Markgraf 2024-11-28 21:10:50 +01:00
parent 2e644a593b
commit 371c59fc28
2 changed files with 3 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
README.md
View file

@ -38,7 +38,7 @@ The data from the internal ADC is streamed out via USB. Default configuration is
### external_adc ### external_adc
This app contains a PIO program that reads the data from a 12-bit ADC connected to GP0-GP11, outputs the ADC clock on GP22, and packs the 12 bit samples to 16-bit words to achieve maximum throughput. This app contains a PIO program that reads the data from a 12-bit ADC connected to GP0-GP11, outputs the ADC clock on GP20, and packs the 12 bit samples to 16-bit words to achieve maximum throughput.
It is meant to be used with cheap AD9226 ADC boards. The default setting is overclocking the RP2350 to 320 MHz and driving the ADC with a 40 MHz clock. With higher overclocking up to 50.25 MHz ADC clock can be used. It is meant to be used with cheap AD9226 ADC boards. The default setting is overclocking the RP2350 to 320 MHz and driving the ADC with a 40 MHz clock. With higher overclocking up to 50.25 MHz ADC clock can be used.
This can be used for sampling the IF of a tuner/downcoverter, as a direct-sampling HF SDR, or for capturing a video signal e.g. with [vhsdecode](https://github.com/oyvindln/vhs-decode). This can be used for sampling the IF of a tuner/downcoverter, as a direct-sampling HF SDR, or for capturing a video signal e.g. with [vhsdecode](https://github.com/oyvindln/vhs-decode).

4
apps/external_adc/external_adc.c
View file

@ -49,9 +49,9 @@
//#define SYS_CLK 384000 // 48 MHz ADC clock //#define SYS_CLK 384000 // 48 MHz ADC clock
//#define SYS_CLK 402000 // 50.25 MHz ADC clock, maximum that works on my Pico2 (with overvolting) //#define SYS_CLK 402000 // 50.25 MHz ADC clock, maximum that works on my Pico2 (with overvolting)
// ADC is attached to GP0 - GP11 with clock on GP22 // ADC is attached to GP0 - GP11 with clock on GP20
#define PIO_INPUT_PIN_BASE 0 #define PIO_INPUT_PIN_BASE 0
#define PIO_OUTPUT_CLK_PIN 22 #define PIO_OUTPUT_CLK_PIN 20
#define DMACH_PIO_PING 0 #define DMACH_PIO_PING 0
#define DMACH_PIO_PONG 1 #define DMACH_PIO_PONG 1