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https://github.com/steve-m/hsdaoh-fpga.git
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75 lines
1.7 KiB
Verilog
75 lines
1.7 KiB
Verilog
// TMDS serializer
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// By Sameer Puri https://github.com/sameer
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// source: https://github.com/hdl-util/hdmi/
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// Dual-licensed under Apache License 2.0 and MIT License.
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// converted to Verilog for hsdaoh
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// currently only contains the GOWIN OSER10 primitives
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// TODO: add back everything from https://github.com/hdl-util/hdmi/blob/master/src/serializer.sv
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module serializer (
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clk_pixel,
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clk_pixel_x5,
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reset,
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tmds_internal,
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tmds,
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tmds_clock
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);
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parameter signed [31:0] NUM_CHANNELS = 3;
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parameter real VIDEO_RATE = 0;
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input wire clk_pixel;
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input wire clk_pixel_x5;
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input wire reset;
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input wire [(NUM_CHANNELS * 10) - 1:0] tmds_internal;
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output wire [2:0] tmds;
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output wire tmds_clock;
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OSER10 gwSer0(
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.Q(tmds[0]),
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.D0(tmds_internal[0]),
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.D1(tmds_internal[1]),
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.D2(tmds_internal[2]),
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.D3(tmds_internal[3]),
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.D4(tmds_internal[4]),
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.D5(tmds_internal[5]),
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.D6(tmds_internal[6]),
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.D7(tmds_internal[7]),
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.D8(tmds_internal[8]),
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.D9(tmds_internal[9]),
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.PCLK(clk_pixel),
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.FCLK(clk_pixel_x5),
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.RESET(reset)
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);
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OSER10 gwSer1(
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.Q(tmds[1]),
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.D0(tmds_internal[10]),
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.D1(tmds_internal[11]),
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.D2(tmds_internal[12]),
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.D3(tmds_internal[13]),
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.D4(tmds_internal[14]),
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.D5(tmds_internal[15]),
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.D6(tmds_internal[16]),
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.D7(tmds_internal[17]),
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.D8(tmds_internal[18]),
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.D9(tmds_internal[19]),
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.PCLK(clk_pixel),
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.FCLK(clk_pixel_x5),
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.RESET(reset)
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);
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OSER10 gwSer2(
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.Q(tmds[2]),
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.D0(tmds_internal[20]),
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.D1(tmds_internal[21]),
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.D2(tmds_internal[22]),
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.D3(tmds_internal[23]),
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.D4(tmds_internal[24]),
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.D5(tmds_internal[25]),
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.D6(tmds_internal[26]),
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.D7(tmds_internal[27]),
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.D8(tmds_internal[28]),
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.D9(tmds_internal[29]),
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.PCLK(clk_pixel),
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.FCLK(clk_pixel_x5),
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.RESET(reset)
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);
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assign tmds_clock = clk_pixel;
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endmodule
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