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81 lines
2.5 KiB
Verilog
81 lines
2.5 KiB
Verilog
// Implementation of HDMI packet choice logic.
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// By Sameer Puri https://github.com/sameer
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// source: https://github.com/hdl-util/hdmi/
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// Dual-licensed under Apache License 2.0 and MIT License.
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// converted to Verilog and removed packets not required for hsdaoh
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module packet_picker (
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clk_pixel,
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reset,
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video_field_end,
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packet_enable,
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packet_pixel_counter,
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header,
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sub
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);
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parameter [6:0] VIDEO_ID_CODE = 4;
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parameter [0:0] IT_CONTENT = 1'b0;
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input wire clk_pixel;
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input wire reset;
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input wire video_field_end;
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input wire packet_enable;
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input wire [4:0] packet_pixel_counter;
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output wire [23:0] header;
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output wire [223:0] sub;
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// Connect the current packet type's data to the output.
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reg [7:0] packet_type = 8'd0;
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wire [23:0] headers [255:0];
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wire [223:0] subs [255:0];
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assign header = headers[packet_type];
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assign sub[0+:56] = subs[packet_type][0+:56];
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assign sub[56+:56] = subs[packet_type][56+:56];
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assign sub[112+:56] = subs[packet_type][112+:56];
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assign sub[168+:56] = subs[packet_type][168+:56];
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// NULL packet
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// "An HDMI Sink shall ignore bytes HB1 and HB2 of the Null Packet Header and all bytes of the Null Packet Body."
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assign headers[0] = 24'hxxxx00;
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assign subs[0][0+:56] = 56'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
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assign subs[0][56+:56] = 56'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
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assign subs[0][112+:56] = 56'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
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assign subs[0][168+:56] = 56'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
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reg [7:0] frame_counter = 8'd0;
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always @(posedge clk_pixel)
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begin
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if (reset)
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frame_counter <= 8'd0;
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else if ((packet_pixel_counter == 5'd31) && (packet_type == 8'h02)) begin
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frame_counter = frame_counter + 8'd4;
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if (frame_counter >= 8'd192)
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frame_counter = frame_counter - 8'd192;
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end
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end
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auxiliary_video_information_info_frame #(
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.VIDEO_ID_CODE(VIDEO_ID_CODE),
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.IT_CONTENT(IT_CONTENT)
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) auxiliary_video_information_info_frame(
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.header(headers[130]),
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.sub(subs[130])
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);
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reg auxiliary_video_information_info_frame_sent = 1'b0;
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always @(posedge clk_pixel)
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begin
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if (reset || video_field_end) begin
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auxiliary_video_information_info_frame_sent <= 1'b0;
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packet_type <= 8'bxxxxxxxx;
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end
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else if (packet_enable) begin
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if (!auxiliary_video_information_info_frame_sent) begin
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packet_type <= 8'h82;
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auxiliary_video_information_info_frame_sent <= 1'b1;
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end
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else
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packet_type <= 8'd0;
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end
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end
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endmodule
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