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92 lines
3.2 KiB
Verilog
92 lines
3.2 KiB
Verilog
// Implementation of HDMI packet ECC calculation.
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// By Sameer Puri https://github.com/sameer
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// source: https://github.com/hdl-util/hdmi/
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// Dual-licensed under Apache License 2.0 and MIT License.
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// converted to Verilog for hsdaoh
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module packet_assembler (
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clk_pixel,
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reset,
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data_island_period,
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header, // See Table 5-8 Packet Types
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sub,
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packet_data, // See Figure 5-4 Data Island Packet and ECC Structure
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counter
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);
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input wire clk_pixel;
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input wire reset;
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input wire data_island_period;
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input wire [23:0] header;
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input wire [223:0] sub;
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output wire [8:0] packet_data;
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output reg [4:0] counter = 5'd0;
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// 32 pixel wrap-around counter. See Section 5.2.3.4 for further information.
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always @(posedge clk_pixel)
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begin
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if (reset)
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counter <= 5'd0;
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else if (data_island_period)
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counter <= counter + 5'd1;
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end
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// BCH packets 0 to 3 are transferred two bits at a time, see Section 5.2.3.4 for further information.
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wire [5:0] counter_t2 = {counter, 1'b0};
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wire [5:0] counter_t2_p1 = {counter, 1'b1};
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// Initialize parity bits to 0
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reg [39:0] parity = 40'h0000000000;
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wire [63:0] bch [3:0];
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assign bch[0] = {parity[0+:8], sub[0+:56]};
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assign bch[1] = {parity[8+:8], sub[56+:56]};
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assign bch[2] = {parity[16+:8], sub[112+:56]};
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assign bch[3] = {parity[24+:8], sub[168+:56]};
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wire [31:0] bch4 = {parity[32+:8], header};
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assign packet_data = {bch[3][counter_t2_p1], bch[2][counter_t2_p1], bch[1][counter_t2_p1], bch[0][counter_t2_p1], bch[3][counter_t2], bch[2][counter_t2], bch[1][counter_t2], bch[0][counter_t2], bch4[counter]};
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// See Figure 5-5 Error Correction Code generator. Generalization of a CRC with binary BCH.
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// See https://web.archive.org/web/20190520020602/http://hamsterworks.co.nz/mediawiki/index.php/Minimal_HDMI#Computing_the_ECC for an explanation of the implementation.
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// See https://en.wikipedia.org/wiki/BCH_code#Systematic_encoding:_The_message_as_a_prefix for further information.
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function automatic [7:0] next_ecc;
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input [7:0] ecc, next_bch_bit;
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begin
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next_ecc = (ecc >> 1) ^ (ecc[0] ^ next_bch_bit ? 8'b10000011 : 8'd0);
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end
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endfunction
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wire [7:0] parity_next [4:0];
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// The parity needs to be calculated 2 bits at a time for blocks 0 to 3.
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// There's 56 bits being sent 2 bits at a time over TMDS channels 1 & 2, so the parity bits wouldn't be ready in time otherwise.
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wire [31:0] parity_next_next;
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genvar i;
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generate
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for (i = 0; i < 5; i = i + 1) begin : parity_calc
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if (i == 4) begin : genblk1
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assign parity_next[i] = next_ecc(parity[i * 8+:8], header[counter]);
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end
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else begin : genblk1
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assign parity_next[i] = next_ecc(parity[i * 8+:8], sub[(i * 56) + counter_t2]);
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assign parity_next_next[i * 8+:8] = next_ecc(parity_next[i], sub[(i * 56) + counter_t2_p1]);
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end
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end
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endgenerate
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always @(posedge clk_pixel)
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begin
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if (reset)
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parity <= 40'h0000000000;
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else if (data_island_period) begin
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if (counter < 5'd28) begin // Compute ECC only on subpacket data, not on itself
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parity[0+:32] <= parity_next_next;
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if (counter < 5'd24) // Header only has 24 bits, whereas subpackets have 56 and 56 / 2 = 28.
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parity[32+:8] <= parity_next[4];
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end
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else if (counter == 5'd31)
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parity <= 40'h0000000000; // Reset ECC for next packet
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end
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else
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parity <= 40'h0000000000;
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end
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endmodule
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