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29 lines
564 B
Verilog
29 lines
564 B
Verilog
module clk_div3(clk,reset, clk_out);
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input clk;
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input reset;
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output clk_out;
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reg [1:0] pos_count, neg_count;
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wire [1:0] r_nxt;
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always @(posedge clk) begin
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if (reset)
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pos_count <= 0;
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else if (pos_count == 2)
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pos_count <= 0;
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else
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pos_count <= pos_count + 1;
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end
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always @(negedge clk) begin
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if (reset)
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neg_count <=0;
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else if (neg_count == 2)
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neg_count <= 0;
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else
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neg_count<= neg_count +1;
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end
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assign clk_out = ~((pos_count == 2) | (neg_count == 2));
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endmodule
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