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133 lines
3.3 KiB
Verilog
133 lines
3.3 KiB
Verilog
// hsdaoh - High Speed Data Acquisition over HDMI
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// Implementation of data output
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// Copyright (C) 2024 by Steve Markgraf <steve@steve-m.de>
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// License: MIT
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module hsdaoh_core
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(
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input wire rstn,
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output wire tmds_clk_n,
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output wire tmds_clk_p,
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output wire [2:0] tmds_d_n,
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output wire [2:0] tmds_d_p,
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input wire clk_pixel_x5,
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input wire clk_pixel,
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input wire fifo_empty,
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input wire fifo_aempty,
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output reg fifo_read_en,
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input wire [15:0] data_in
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);
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localparam [31:0] MAGIC = 32'hda7acab1;
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reg [23:0] hdmi_data = 24'h000000;
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reg [15:0] frame_cnt = 16'h0000;
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reg [15:0] idle_counter = 16'h0000;
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reg [15:0] line_word_cnt = 16'h00;
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reg [3:0] status_nibble = 4'h0;
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wire [11:0] cx;
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wire [10:0] cy;
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wire [11:0] frame_width;
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wire [10:0] frame_height;
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wire [11:0] screen_width;
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wire [10:0] screen_height;
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always @(posedge clk_pixel) begin
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if ((cx == screen_width-1) && (cy < screen_height)) begin
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// last word of line contains counter of words per line
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hdmi_data <= {status_nibble[3:0], line_word_cnt[11:0], 8'h00};
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end else if ((cx < screen_width) && (cy < screen_height)) begin
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if (fifo_read_en && !fifo_empty) begin
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// regular output of FIFO data
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hdmi_data <= {data_in[15:0], 8'h00};
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// increment line payload counter
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line_word_cnt <= line_word_cnt + 1'b1;
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end else begin
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// output idle counter
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hdmi_data <= {idle_counter[15:8], idle_counter[7:0], 8'h00};
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// increment idle counter
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idle_counter <= idle_counter + 1'b1;
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end
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end else
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line_word_cnt <= 16'h0000;
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// Enable reading before beginning of next line
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if ((cx == frame_width-1) && (cy < screen_height-1) && !fifo_empty)
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fifo_read_en = 1'b1;
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// switch read off during blanking
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if (cy > screen_height)
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fifo_read_en = 1'b0;
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// switch read off at end of line before sending the word counter
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// -2 because the last word is reserved (line_word_cnt and metadata)
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if ((cx == screen_width-2) && (cy < screen_height))
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fifo_read_en = 1'b0;
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// switch read off when FIFO has only one word remaining
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if (fifo_aempty)
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fifo_read_en = 1'b0;
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// increment the frame counter at the end of the frame
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if ((cx == frame_width-1) && (cy == frame_height-1)) begin
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frame_cnt <= frame_cnt + 1'b1;
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line_word_cnt <= 16'h0000;
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// start FIFO readout
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if (!fifo_empty)
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fifo_read_en = 1'b1;
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end
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if (cx == 0) begin
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case (cy)
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0 : status_nibble <= MAGIC[3:0];
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1 : status_nibble <= MAGIC[7:4];
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2 : status_nibble <= MAGIC[11:8];
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3 : status_nibble <= MAGIC[15:12];
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4 : status_nibble <= MAGIC[19:16];
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5 : status_nibble <= MAGIC[23:20];
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6 : status_nibble <= MAGIC[27:24];
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7 : status_nibble <= MAGIC[31:28];
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8 : status_nibble <= frame_cnt[3:0];
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9 : status_nibble <= frame_cnt[7:4];
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10 : status_nibble <= frame_cnt[11:8];
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11 : status_nibble <= frame_cnt[15:12];
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default : status_nibble <= 4'h0;
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endcase
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end
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end
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wire tmds_clock;
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wire [2:0] tmds;
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hdmi #(
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.VIDEO_ID_CODE(16),
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.DVI_OUTPUT(0)
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) hdmi(
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.clk_pixel_x5(clk_pixel_x5),
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.clk_pixel(clk_pixel),
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.reset(!rstn),
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.rgb(hdmi_data),
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.tmds(tmds),
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.tmds_clock(tmds_clock),
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.cx(cx),
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.cy(cy),
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.frame_width(frame_width),
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.frame_height(frame_height),
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.screen_width(screen_width),
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.screen_height(screen_height)
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);
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ELVDS_OBUF tmds_bufds[3:0](
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.I({clk_pixel, tmds}),
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.O({tmds_clk_p, tmds_d_p}),
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.OB({tmds_clk_n, tmds_d_n})
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);
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endmodule
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