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32 lines
614 B
Verilog
32 lines
614 B
Verilog
// https://github.com/dpretet/async_fifo
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// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module sync_r2w
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#(
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parameter ASIZE = 4
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)(
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input wire wclk,
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input wire wrst_n,
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input wire [ASIZE:0] rptr,
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output reg [ASIZE:0] wq2_rptr
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);
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reg [ASIZE:0] wq1_rptr;
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always @(posedge wclk or negedge wrst_n) begin
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if (!wrst_n)
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{wq2_rptr,wq1_rptr} <= 0;
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else
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{wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
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end
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endmodule
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`resetall
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