mirror of
https://github.com/steve-m/hsdaoh-fpga.git
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195 lines
4 KiB
Verilog
195 lines
4 KiB
Verilog
// hsdaoh - High Speed Data Acquisition over HDMI
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// Test top design for Tang Primer 25K
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// Copyright (C) 2024 by Steve Markgraf <steve@steve-m.de>
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// License: MIT
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module top (
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sys_clk,
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sys_resetn,
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tmds_clk_n,
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tmds_clk_p,
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tmds_d_n,
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tmds_d_p
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);
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input sys_clk;
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input sys_resetn;
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output wire tmds_clk_n;
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output wire tmds_clk_p;
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output wire [2:0] tmds_d_n;
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output wire [2:0] tmds_d_p;
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wire [2:0] tmds;
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wire clk_pixel;
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wire clk_pixel_x5;
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wire pll_lock;
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wire clk_data;
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// 475 MHz, maximum that works with the primer 25K
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// 475/5 = 95 MHz
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// Data PLL output is 89.0625 MHz
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PLLA #(
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.FCLKIN ("50"),
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.IDIV_SEL (2),
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.FBDIV_SEL (1),
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.CLKFB_SEL ("INTERNAL"),
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.ODIV0_SEL (3),
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.ODIV0_FRAC_SEL (0),
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.ODIV1_SEL (16),
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.ODIV2_SEL (8),
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.ODIV3_SEL (8),
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.ODIV4_SEL (8),
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.ODIV5_SEL (8),
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.ODIV6_SEL (8),
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.MDIV_SEL (57),
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.MDIV_FRAC_SEL (0),
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.CLKOUT0_EN ("TRUE"),
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.CLKOUT1_EN ("TRUE"),
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.CLKOUT2_EN ("FALSE"),
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.CLKOUT3_EN ("FALSE"),
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.CLKOUT4_EN ("FALSE"),
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.CLKOUT5_EN ("FALSE"),
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.CLKOUT6_EN ("FALSE"),
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.CLKOUT0_DT_DIR (1'b1),
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.CLKOUT0_DT_DIR (1'b1),
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.CLKOUT1_DT_DIR (1'b1),
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.CLKOUT2_DT_DIR (1'b1),
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.CLKOUT3_DT_DIR (1'b1),
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.CLK0_IN_SEL (1'b0),
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.CLK0_OUT_SEL (1'b0),
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.CLK1_IN_SEL (1'b0),
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.CLK1_OUT_SEL (1'b0),
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.CLK2_IN_SEL (1'b0),
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.CLK2_OUT_SEL (1'b0),
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.CLK3_IN_SEL (1'b0),
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.CLK3_OUT_SEL (1'b0),
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.CLK4_IN_SEL (2'b00),
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.CLK4_OUT_SEL (1'b0),
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.CLK5_IN_SEL (1'b0),
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.CLK5_OUT_SEL (1'b0),
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.CLK6_IN_SEL (1'b0),
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.CLK6_OUT_SEL (1'b0),
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.CLKOUT0_PE_COARSE (0),
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.CLKOUT0_PE_FINE (0),
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.CLKOUT1_PE_COARSE (0),
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.CLKOUT1_PE_FINE (0),
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.CLKOUT2_PE_COARSE (0),
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.CLKOUT2_PE_FINE (0),
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.CLKOUT3_PE_COARSE (0),
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.CLKOUT3_PE_FINE (0),
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.CLKOUT4_PE_COARSE (0),
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.CLKOUT4_PE_FINE (0),
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.CLKOUT5_PE_COARSE (0),
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.CLKOUT5_PE_FINE (0),
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.CLKOUT6_PE_COARSE (0),
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.CLKOUT6_PE_FINE (0),
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.DE0_EN ("FALSE"),
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.DE1_EN ("FALSE"),
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.DE2_EN ("FALSE"),
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.DE3_EN ("FALSE"),
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.DE4_EN ("FALSE"),
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.DE5_EN ("FALSE"),
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.DE6_EN ("FALSE"),
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.DYN_DPA_EN ("FALSE"),
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.DYN_PE0_SEL ("FALSE"),
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.DYN_PE1_SEL ("FALSE"),
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.DYN_PE2_SEL ("FALSE"),
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.DYN_PE3_SEL ("FALSE"),
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.DYN_PE4_SEL ("FALSE"),
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.DYN_PE5_SEL ("FALSE"),
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.DYN_PE6_SEL ("FALSE"),
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.RESET_I_EN ("FALSE"),
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.RESET_O_EN ("FALSE"),
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.ICP_SEL (6'bXXXXXX),
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.LPF_RES (3'bXXX),
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.LPF_CAP (2'b00),
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.SSC_EN ("FALSE"),
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.CLKOUT0_DT_STEP (0),
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.CLKOUT1_DT_STEP (0),
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.CLKOUT2_DT_STEP (0),
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.CLKOUT3_DT_STEP (0)
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) pll (
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.LOCK(pll_lock),
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.CLKOUT0(clk_pixel_x5),
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.CLKOUT1(clk_data),
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.CLKIN(sys_clk),
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.CLKFB(1'b0),
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.RESET(1'b0),
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.PLLPWD(1'b0),
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.RESET_I(1'b0),
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.RESET_O(1'b0),
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.PSSEL(3'b0),
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.PSDIR(1'b0),
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.PSPULSE(1'b0),
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.SSCPOL(1'b0),
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.SSCON(1'b0),
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.SSCMDSEL(7'b0),
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.SSCMDSEL_FRAC(3'b0),
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.MDCLK(1'b0),
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.MDOPC(2'b0),
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.MDAINC(1'b0),
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.MDWDI(8'b0)
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);
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CLKDIV #(
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.DIV_MODE(5)
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) div_5 (
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.CLKOUT(clk_pixel),
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.HCLKIN(clk_pixel_x5),
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.RESETN(1'b1),
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.CALIB(1'b0)
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);
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reg [15:0] counter = 16'h0000;
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reg [15:0] fifo_in;
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wire write_enable;
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wire [15:0] fifo_out;
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wire fifo_empty;
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wire fifo_aempty;
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wire Full_o;
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wire FifoHalfFull;
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wire FifoFull;
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wire fifo_rd_en_i;
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async_fifo #(
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.DSIZE(16),
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.ASIZE($clog2(16384)), // 3 + (1982 * 4) = 7931 => at least 8K entries to buffer 4 lines during VSYNC
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.FALLTHROUGH("FALSE")
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) fifo (
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.wclk(clk_data),
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.wrst_n(pll_lock),
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.winc(write_enable),
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.wdata(fifo_in),
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.wfull(FifoFull),
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.awfull(FifoHalfFull),
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.rclk(clk_pixel),
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.rrst_n(pll_lock),
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.rinc(fifo_rd_en_i),
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.rdata(fifo_out),
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.rempty(fifo_empty),
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.arempty(fifo_aempty)
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);
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hsdaoh_core hsdaoh (
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.rstn(pll_lock),
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.tmds_clk_n(tmds_clk_n),
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.tmds_clk_p(tmds_clk_p),
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.tmds_d_n(tmds_d_n),
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.tmds_d_p(tmds_d_p),
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.clk_pixel_x5(clk_pixel_x5),
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.clk_pixel(clk_pixel),
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.fifo_empty(fifo_empty),
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.fifo_aempty(fifo_aempty),
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.fifo_read_en(fifo_rd_en_i),
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.data_in(fifo_out)
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);
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assign write_enable = 1'b1;
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always @(posedge clk_data) begin
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fifo_in <= counter[15:0];
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counter <= counter + 1'b1;
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end
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endmodule
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