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@ -21,3 +21,7 @@ Here is an example commandline for loading the bitfile on a Tang Nano 20K:
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## Testing the design
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After loading the bitfile, connect the FPGA board to a MS2130 HDMI grabber and confirm that the video output is working. You then can use hsdaoh_test to verify the counter values.
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## Credits
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The hsdaoh FPGA design was developed by Steve Markgraf, and is heavily based on the [HDMI IP core](https://github.com/hdl-util/hdmi) by Sameer Puri and also uses the [asynchronous FIFO](https://github.com/dpretet/async_fifo) by Damien Pretet.
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