mirror of
https://github.com/steve-m/hsdaoh-fpga.git
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hsdaoh_core: add CRC16 checksum support
Output is identical to the implementation in hsdaoh-rp2350.
This commit is contained in:
Steve Markgraf
parent
8b9e1457ea
commit
1b2d011581
7 changed files with 149 additions and 27 deletions
86
common/hsdaoh/crc16_ccitt.v
Normal file
86
common/hsdaoh/crc16_ccitt.v
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@ -0,0 +1,86 @@
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/* -----------------------------------------------------------------------------------
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* Module Name : crc16_ccitt
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* Generated by : https://github.com/PXVI/ip_parallel_custom_crc_gerator_verilog
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* Author : pxvi
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* Description : Parallel CRC( 16-bit ) module with 16-bit data input.
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* Polynomial Degrees [ 16 12 5 0 ]
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* -----------------------------------------------------------------------------------
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*
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* MIT License
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*
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* Copyright (c) 2024 k-sva
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the Software), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* ----------------------------------------------------------------------------------- */
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module crc16_ccitt #( parameter RESET_SEED = 'hffff )(
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input wire CLK,
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input wire RSTn,
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input wire [15:0] data_in,
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input wire enable,
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input wire clear,
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output [15:0] CRC
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);
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reg [16-1:0] Mout_p, Mout_n;
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always@( posedge CLK )
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begin
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Mout_p <= Mout_n;
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if( !RSTn )
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begin
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Mout_p <= RESET_SEED;
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end
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end
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always@( * )
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begin
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Mout_n = Mout_p;
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if( clear )
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begin
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Mout_n = RESET_SEED;
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end
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else if( enable )
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begin
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Mout_n[0] = data_in[0] ^ data_in[4] ^ data_in[8] ^ data_in[11] ^ data_in[12] ^ Mout_p[0] ^ Mout_p[4] ^ Mout_p[8] ^ Mout_p[11] ^ Mout_p[12] ;
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Mout_n[1] = data_in[1] ^ data_in[5] ^ data_in[9] ^ data_in[12] ^ data_in[13] ^ Mout_p[1] ^ Mout_p[5] ^ Mout_p[9] ^ Mout_p[12] ^ Mout_p[13] ;
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Mout_n[2] = data_in[2] ^ data_in[6] ^ data_in[10] ^ data_in[13] ^ data_in[14] ^ Mout_p[2] ^ Mout_p[6] ^ Mout_p[10] ^ Mout_p[13] ^ Mout_p[14] ;
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Mout_n[3] = data_in[3] ^ data_in[7] ^ data_in[11] ^ data_in[14] ^ data_in[15] ^ Mout_p[3] ^ Mout_p[7] ^ Mout_p[11] ^ Mout_p[14] ^ Mout_p[15] ;
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Mout_n[4] = data_in[4] ^ data_in[8] ^ data_in[12] ^ data_in[15] ^ Mout_p[4] ^ Mout_p[8] ^ Mout_p[12] ^ Mout_p[15] ;
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Mout_n[5] = data_in[0] ^ data_in[4] ^ data_in[5] ^ data_in[8] ^ data_in[9] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ Mout_p[0] ^ Mout_p[4] ^ Mout_p[5] ^ Mout_p[8] ^ Mout_p[9] ^ Mout_p[11] ^ Mout_p[12] ^ Mout_p[13] ;
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Mout_n[6] = data_in[1] ^ data_in[5] ^ data_in[6] ^ data_in[9] ^ data_in[10] ^ data_in[12] ^ data_in[13] ^ data_in[14] ^ Mout_p[1] ^ Mout_p[5] ^ Mout_p[6] ^ Mout_p[9] ^ Mout_p[10] ^ Mout_p[12] ^ Mout_p[13] ^ Mout_p[14] ;
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Mout_n[7] = data_in[2] ^ data_in[6] ^ data_in[7] ^ data_in[10] ^ data_in[11] ^ data_in[13] ^ data_in[14] ^ data_in[15] ^ Mout_p[2] ^ Mout_p[6] ^ Mout_p[7] ^ Mout_p[10] ^ Mout_p[11] ^ Mout_p[13] ^ Mout_p[14] ^ Mout_p[15] ;
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Mout_n[8] = data_in[3] ^ data_in[7] ^ data_in[8] ^ data_in[11] ^ data_in[12] ^ data_in[14] ^ data_in[15] ^ Mout_p[3] ^ Mout_p[7] ^ Mout_p[8] ^ Mout_p[11] ^ Mout_p[12] ^ Mout_p[14] ^ Mout_p[15] ;
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Mout_n[9] = data_in[4] ^ data_in[8] ^ data_in[9] ^ data_in[12] ^ data_in[13] ^ data_in[15] ^ Mout_p[4] ^ Mout_p[8] ^ Mout_p[9] ^ Mout_p[12] ^ Mout_p[13] ^ Mout_p[15] ;
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Mout_n[10] = data_in[5] ^ data_in[9] ^ data_in[10] ^ data_in[13] ^ data_in[14] ^ Mout_p[5] ^ Mout_p[9] ^ Mout_p[10] ^ Mout_p[13] ^ Mout_p[14] ;
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Mout_n[11] = data_in[6] ^ data_in[10] ^ data_in[11] ^ data_in[14] ^ data_in[15] ^ Mout_p[6] ^ Mout_p[10] ^ Mout_p[11] ^ Mout_p[14] ^ Mout_p[15] ;
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Mout_n[12] = data_in[0] ^ data_in[4] ^ data_in[7] ^ data_in[8] ^ data_in[15] ^ Mout_p[0] ^ Mout_p[4] ^ Mout_p[7] ^ Mout_p[8] ^ Mout_p[15] ;
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Mout_n[13] = data_in[1] ^ data_in[5] ^ data_in[8] ^ data_in[9] ^ Mout_p[1] ^ Mout_p[5] ^ Mout_p[8] ^ Mout_p[9] ;
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Mout_n[14] = data_in[2] ^ data_in[6] ^ data_in[9] ^ data_in[10] ^ Mout_p[2] ^ Mout_p[6] ^ Mout_p[9] ^ Mout_p[10] ;
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Mout_n[15] = data_in[3] ^ data_in[7] ^ data_in[10] ^ data_in[11] ^ Mout_p[3] ^ Mout_p[7] ^ Mout_p[10] ^ Mout_p[11] ;
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end
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end
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assign CRC = Mout_p;
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endmodule
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@ -18,6 +18,21 @@ module hsdaoh_core
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input wire [15:0] data_in
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);
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parameter USE_CRC = 1;
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reg crc_enable = 1'b0;
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wire [15:0] crc_out;
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reg [15:0] last_line_crc;
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crc16_ccitt crc16_ccitt (
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.CLK(clk_pixel),
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.RSTn(rstn),
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.data_in({hdmi_data[15:8], hdmi_data[23:16]}),
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.enable(crc_enable),
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.clear(!crc_enable),
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.CRC(crc_out)
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);
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localparam [31:0] MAGIC = 32'hda7acab1;
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reg [23:0] hdmi_data = 24'h000000;
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@ -35,11 +50,24 @@ module hsdaoh_core
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always @(posedge clk_pixel) begin
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if ((cx == screen_width-1) && (cy < screen_height)) begin
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if (cy < screen_height) begin
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if (USE_CRC && (cx == 0))
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crc_enable <= 1'b1;
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if (USE_CRC && (cx == screen_width+1)) begin
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last_line_crc <= crc_out;
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crc_enable <= 1'b0;
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end
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if (cx == screen_width-1) begin
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// last word of line contains counter of words per line
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hdmi_data <= {status_nibble[3:0], line_word_cnt[11:0], 8'h00};
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end else if ((cx < screen_width) && (cy < screen_height)) begin
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end else if (USE_CRC && (cx == screen_width-2)) begin
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// second last word contains CRC
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hdmi_data <= {last_line_crc, 8'h00};
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end else if (cx < screen_width) begin
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if (fifo_read_en && !fifo_empty) begin
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// regular output of FIFO data
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hdmi_data <= {data_in[15:0], 8'h00};
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@ -57,16 +85,19 @@ always @(posedge clk_pixel) begin
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line_word_cnt <= 16'h0000;
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// Enable reading before beginning of next line
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if ((cx == frame_width-1) && (cy < screen_height-1) && !fifo_empty)
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if ((cx == frame_width-1) && (cy != screen_height-1)) begin
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if (!fifo_empty)
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fifo_read_en = 1'b1;
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// switch read off during blanking
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if (cy > screen_height)
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fifo_read_en = 1'b0;
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end
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// switch read off at end of line before sending the word counter
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// -2 because the last word is reserved (line_word_cnt and metadata)
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if ((cx == screen_width-2) && (cy < screen_height))
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if (cx == screen_width-2-USE_CRC)
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fifo_read_en = 1'b0;
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end
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// switch read off during blanking
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if (cy > screen_height)
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fifo_read_en = 1'b0;
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// switch read off when FIFO has only one word remaining
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@ -97,10 +128,10 @@ always @(posedge clk_pixel) begin
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9 : status_nibble <= frame_cnt[7:4];
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10 : status_nibble <= frame_cnt[11:8];
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11 : status_nibble <= frame_cnt[15:12];
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14 : status_nibble <= { 3'b000, USE_CRC };
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default : status_nibble <= 4'h0;
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endcase
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end
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end
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wire tmds_clock;
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@ -17,6 +17,7 @@
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<File path="common/hdmi/packet_picker.v" type="file.verilog" enable="1"/>
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<File path="common/hdmi/serializer.v" type="file.verilog" enable="1"/>
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<File path="common/hdmi/tmds_channel.v" type="file.verilog" enable="1"/>
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<File path="common/hsdaoh/crc16_ccitt.v" type="file.verilog" enable="1"/>
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<File path="common/hsdaoh/hsdaoh_core.v" type="file.verilog" enable="1"/>
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<File path="hsdaoh_nano20k_test/top.v" type="file.verilog" enable="1"/>
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<File path="hsdaoh_nano20k_test/hsdaoh_nano20k_test.cst" type="file.cst" enable="1"/>
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@ -17,6 +17,7 @@
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<File path="common/hdmi/packet_picker.v" type="file.verilog" enable="1"/>
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<File path="common/hdmi/serializer.v" type="file.verilog" enable="1"/>
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<File path="common/hdmi/tmds_channel.v" type="file.verilog" enable="1"/>
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<File path="common/hsdaoh/crc16_ccitt.v" type="file.verilog" enable="1"/>
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<File path="common/hsdaoh/hsdaoh_core.v" type="file.verilog" enable="1"/>
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<File path="hsdaoh_nano4k_test/fifo_hs/fifo_hs.v" type="file.verilog" enable="1"/>
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<File path="hsdaoh_nano4k_test/top.v" type="file.verilog" enable="1"/>
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@ -17,6 +17,7 @@
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<File path="common/hdmi/packet_picker.v" type="file.verilog" enable="1"/>
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<File path="common/hdmi/serializer.v" type="file.verilog" enable="1"/>
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<File path="common/hdmi/tmds_channel.v" type="file.verilog" enable="1"/>
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<File path="common/hsdaoh/crc16_ccitt.v" type="file.verilog" enable="1"/>
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<File path="common/hsdaoh/hsdaoh_core.v" type="file.verilog" enable="1"/>
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<File path="hsdaoh_nano9k_test/fifo_hs/fifo_hs.v" type="file.verilog" enable="1"/>
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<File path="hsdaoh_nano9k_test/top.v" type="file.verilog" enable="1"/>
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@ -17,6 +17,7 @@
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<File path="common/hdmi/packet_picker.v" type="file.verilog" enable="1"/>
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<File path="common/hdmi/serializer.v" type="file.verilog" enable="1"/>
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<File path="common/hdmi/tmds_channel.v" type="file.verilog" enable="1"/>
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<File path="common/hsdaoh/crc16_ccitt.v" type="file.verilog" enable="1"/>
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<File path="common/hsdaoh/hsdaoh_core.v" type="file.verilog" enable="1"/>
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<File path="hsdaoh_primer20k_test/top.v" type="file.verilog" enable="1"/>
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<File path="hsdaoh_primer20k_test/hsdaoh_primer20k_test.cst" type="file.cst" enable="1"/>
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@ -17,6 +17,7 @@
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<File path="common/hdmi/packet_picker.v" type="file.verilog" enable="1"/>
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<File path="common/hdmi/serializer.v" type="file.verilog" enable="1"/>
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<File path="common/hdmi/tmds_channel.v" type="file.verilog" enable="1"/>
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<File path="common/hsdaoh/crc16_ccitt.v" type="file.verilog" enable="1"/>
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<File path="common/hsdaoh/hsdaoh_core.v" type="file.verilog" enable="1"/>
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<File path="hsdaoh_primer25k_test/top.v" type="file.verilog" enable="1"/>
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<File path="hsdaoh_primer25k_test/hsdaoh_primer25k_test.cst" type="file.cst" enable="1"/>
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