commit 12fd93fa44c7e5c02429f37bdff68d27036d936a Author: Steve Markgraf Date: Sat May 4 23:56:54 2024 +0200 initial commit diff --git a/common/async_fifo/async_fifo.v b/common/async_fifo/async_fifo.v new file mode 100644 index 0000000..479baf3 --- /dev/null +++ b/common/async_fifo/async_fifo.v @@ -0,0 +1,99 @@ +// https://github.com/dpretet/async_fifo +// distributed under the mit license +// https://opensource.org/licenses/mit-license.php + +`timescale 1 ns / 1 ps +`default_nettype none + +module async_fifo + + #( + parameter DSIZE = 8, + parameter ASIZE = 4, + parameter FALLTHROUGH = "TRUE" // First word fall-through without latency + )( + input wire wclk, + input wire wrst_n, + input wire winc, + input wire [DSIZE-1:0] wdata, + output wire wfull, + output wire awfull, + input wire rclk, + input wire rrst_n, + input wire rinc, + output wire [DSIZE-1:0] rdata, + output wire rempty, + output wire arempty + ); + + wire [ASIZE-1:0] waddr, raddr; + wire [ASIZE :0] wptr, rptr, wq2_rptr, rq2_wptr; + + // The module synchronizing the read point + // from read to write domain + sync_r2w + #(ASIZE) + sync_r2w ( + .wq2_rptr (wq2_rptr), + .rptr (rptr), + .wclk (wclk), + .wrst_n (wrst_n) + ); + + // The module synchronizing the write point + // from write to read domain + sync_w2r + #(ASIZE) + sync_w2r ( + .rq2_wptr (rq2_wptr), + .wptr (wptr), + .rclk (rclk), + .rrst_n (rrst_n) + ); + + // The module handling the write requests + wptr_full + #(ASIZE) + wptr_full ( + .awfull (awfull), + .wfull (wfull), + .waddr (waddr), + .wptr (wptr), + .wq2_rptr (wq2_rptr), + .winc (winc), + .wclk (wclk), + .wrst_n (wrst_n) + ); + + // The DC-RAM + fifomem + #(DSIZE, ASIZE, FALLTHROUGH) + fifomem ( + .rclken (rinc), + .rclk (rclk), + .rdata (rdata), + .wdata (wdata), + .waddr (waddr), + .raddr (raddr), + .wclken (winc), + .wfull (wfull), + .wclk (wclk) + ); + + // The module handling read requests + rptr_empty + #(ASIZE) + rptr_empty ( + .arempty (arempty), + .rempty (rempty), + .raddr (raddr), + .rptr (rptr), + .rq2_wptr (rq2_wptr), + .rinc (rinc), + .rclk (rclk), + .rrst_n (rrst_n) + ); + +endmodule + +`resetall diff --git a/common/async_fifo/fifomem.v b/common/async_fifo/fifomem.v new file mode 100644 index 0000000..8393b64 --- /dev/null +++ b/common/async_fifo/fifomem.v @@ -0,0 +1,53 @@ +// https://github.com/dpretet/async_fifo +// distributed under the mit license +// https://opensource.org/licenses/mit-license.php + +`timescale 1 ns / 1 ps +`default_nettype none + +module fifomem + + #( + parameter DATASIZE = 8, // Memory data word width + parameter ADDRSIZE = 4, // Number of mem address bits + parameter FALLTHROUGH = "TRUE" // First word fall-through + ) ( + input wire wclk, + input wire wclken, + input wire [ADDRSIZE-1:0] waddr, + input wire [DATASIZE-1:0] wdata, + input wire wfull, + input wire rclk, + input wire rclken, + input wire [ADDRSIZE-1:0] raddr, + output wire [DATASIZE-1:0] rdata + ); + + localparam DEPTH = 1<> 1) ^ rbinnext; + assign rgraynextm1 = ((rbinnext + 1'b1) >> 1) ^ (rbinnext + 1'b1); + + //--------------------------------------------------------------- + // FIFO empty when the next rptr == synchronized wptr or on reset + //--------------------------------------------------------------- + assign rempty_val = (rgraynext == rq2_wptr); + assign arempty_val = (rgraynextm1 == rq2_wptr); + + always @ (posedge rclk or negedge rrst_n) begin + + if (!rrst_n) begin + arempty <= 1'b0; + rempty <= 1'b1; + end + else begin + arempty <= arempty_val; + rempty <= rempty_val; + end + + end + +endmodule + +`resetall diff --git a/common/async_fifo/sync_r2w.v b/common/async_fifo/sync_r2w.v new file mode 100644 index 0000000..8aa0bb4 --- /dev/null +++ b/common/async_fifo/sync_r2w.v @@ -0,0 +1,32 @@ +// https://github.com/dpretet/async_fifo +// distributed under the mit license +// https://opensource.org/licenses/mit-license.php + +`timescale 1 ns / 1 ps +`default_nettype none + +module sync_r2w + + #( + parameter ASIZE = 4 + )( + input wire wclk, + input wire wrst_n, + input wire [ASIZE:0] rptr, + output reg [ASIZE:0] wq2_rptr + ); + + reg [ASIZE:0] wq1_rptr; + + always @(posedge wclk or negedge wrst_n) begin + + if (!wrst_n) + {wq2_rptr,wq1_rptr} <= 0; + else + {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr}; + + end + +endmodule + +`resetall diff --git a/common/async_fifo/sync_w2r.v b/common/async_fifo/sync_w2r.v new file mode 100644 index 0000000..e8c56e9 --- /dev/null +++ b/common/async_fifo/sync_w2r.v @@ -0,0 +1,32 @@ +// https://github.com/dpretet/async_fifo +// distributed under the mit license +// https://opensource.org/licenses/mit-license.php + +`timescale 1 ns / 1 ps +`default_nettype none + +module sync_w2r + + #( + parameter ASIZE = 4 + )( + input wire rclk, + input wire rrst_n, + output reg [ASIZE:0] rq2_wptr, + input wire [ASIZE:0] wptr + ); + + reg [ASIZE:0] rq1_wptr; + + always @(posedge rclk or negedge rrst_n) begin + + if (!rrst_n) + {rq2_wptr,rq1_wptr} <= 0; + else + {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr}; + + end + +endmodule + +`resetall diff --git a/common/async_fifo/wptr_full.v b/common/async_fifo/wptr_full.v new file mode 100644 index 0000000..2462a19 --- /dev/null +++ b/common/async_fifo/wptr_full.v @@ -0,0 +1,66 @@ +// https://github.com/dpretet/async_fifo +// distributed under the mit license +// https://opensource.org/licenses/mit-license.php + +`timescale 1 ns / 1 ps +`default_nettype none + +module wptr_full + + #( + parameter ADDRSIZE = 4 + )( + input wire wclk, + input wire wrst_n, + input wire winc, + input wire [ADDRSIZE :0] wq2_rptr, + output reg wfull, + output reg awfull, + output wire [ADDRSIZE-1:0] waddr, + output reg [ADDRSIZE :0] wptr + ); + + reg [ADDRSIZE:0] wbin; + wire [ADDRSIZE:0] wgraynext, wbinnext, wgraynextp1; + wire awfull_val, wfull_val; + + // GRAYSTYLE2 pointer + always @(posedge wclk or negedge wrst_n) begin + + if (!wrst_n) + {wbin, wptr} <= 0; + else + {wbin, wptr} <= {wbinnext, wgraynext}; + + end + + // Memory write-address pointer (okay to use binary to address memory) + assign waddr = wbin[ADDRSIZE-1:0]; + assign wbinnext = wbin + (winc & ~wfull); + assign wgraynext = (wbinnext >> 1) ^ wbinnext; + assign wgraynextp1 = ((wbinnext + 1'b1) >> 1) ^ (wbinnext + 1'b1); + + //------------------------------------------------------------------ + // Simplified version of the three necessary full-tests: + // assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) && + // (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) && + // (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0])); + //------------------------------------------------------------------ + + assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]}); + assign awfull_val = (wgraynextp1 == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]}); + + always @(posedge wclk or negedge wrst_n) begin + + if (!wrst_n) begin + awfull <= 1'b0; + wfull <= 1'b0; + end else begin + awfull <= awfull_val; + wfull <= wfull_val; + end + end + +endmodule + +`resetall diff --git a/common/hdmi/auxiliary_video_information_info_frame.v b/common/hdmi/auxiliary_video_information_info_frame.v new file mode 100644 index 0000000..00a5213 --- /dev/null +++ b/common/hdmi/auxiliary_video_information_info_frame.v @@ -0,0 +1,80 @@ +// Implementation of HDMI Auxiliary Video InfoFrame packet. +// By Sameer Puri https://github.com/sameer +// source: https://github.com/hdl-util/hdmi/ +// Dual-licensed under Apache License 2.0 and MIT License. + +// converted to Verilog and changed to YCbCr 4:2:2 for hsdaoh + +// See Section 8.2.1 +module auxiliary_video_information_info_frame ( + header, + sub +); + parameter [1:0] VIDEO_FORMAT = 2'b01; // 00 = RGB, 01 = YCbCr 4:2:2, 10 = YCbCr 4:4:4 + parameter [0:0] ACTIVE_FORMAT_INFO_PRESENT = 1'b0; // Not valid + parameter [1:0] BAR_INFO = 2'b00; // Not valid + parameter [1:0] SCAN_INFO = 2'b00; // No data + parameter [1:0] COLORIMETRY = 2'b00; // No data + parameter [1:0] PICTURE_ASPECT_RATIO = 2'b00; // No data, See CEA-CEB16 for more information about Active Format Description processing. + parameter [3:0] ACTIVE_FORMAT_ASPECT_RATIO = 4'b1000; // Not valid unless ACTIVE_FORMAT_INFO_PRESENT = 1'b1, then Same as picture aspect ratio + parameter [0:0] IT_CONTENT = 1'b0; // The IT content bit indicates when picture content is composed according to common IT practice (i.e. without regard to Nyquist criterion) and is unsuitable for analog reconstruction or filtering. When the IT content bit is set to 1, downstream processors should pass pixel data unfiltered and without analog reconstruction. + parameter [2:0] EXTENDED_COLORIMETRY = 3'b000; // Not valid unless COLORIMETRY = 2'b11. The extended colorimetry bits, EC2, EC1, and EC0, describe optional colorimetry encoding that may be applicable to some implementations and are always present, whether their information is valid or not (see CEA 861-D Section 7.5.5). + parameter [1:0] RGB_QUANTIZATION_RANGE = 2'b00; // Default. Displays conforming to CEA-861-D accept both a limited quantization range of 220 levels (16 to 235) anda full range of 256 levels (0 to 255) when receiving video with RGB color space (see CEA 861-D Sections 5.1, Section 5.2, Section 5.3 and Section 5.4). By default, RGB pixel data values should be assumed to have the limited range when receiving a CE video format, and the full range when receiving an IT format. The quantization bits allow the source to override this default and to explicitly indicate the current RGB quantization range. + parameter [1:0] NON_UNIFORM_PICTURE_SCALING = 2'b00; // None. The Nonuniform Picture Scaling bits shall be set if the source device scales the picture or has determined that scaling has been performed in a specific direction. + parameter [6:0] VIDEO_ID_CODE = 4; // Same as the one from the HDMI module + parameter [1:0] YCC_QUANTIZATION_RANGE = 2'b00; // 00 = Limited, 01 = Full + parameter [1:0] CONTENT_TYPE = 2'b00; // No data, becomes Graphics if IT_CONTENT = 1'b1. + parameter [3:0] PIXEL_REPETITION = 4'b0000; // None + + output wire [23:0] header; + output wire [223:0] sub; + + localparam [4:0] LENGTH = 5'd13; + localparam [7:0] VERSION = 8'd2; + localparam [6:0] TYPE = 7'd2; + + assign header = {{3'b000, LENGTH}, VERSION, {1'b1, TYPE}}; + + // PB0-PB6 = sub0 + // PB7-13 = sub1 + // PB14-20 = sub2 + // PB21-27 = sub3 + wire [7:0] packet_bytes [27:0]; + + assign packet_bytes[0] = 8'd1 + ~(((((((((((((((header[23:16] + header[15:8]) + header[7:0]) + packet_bytes[13]) + packet_bytes[12]) + packet_bytes[11]) + packet_bytes[10]) + packet_bytes[9]) + packet_bytes[8]) + packet_bytes[7]) + packet_bytes[6]) + packet_bytes[5]) + packet_bytes[4]) + packet_bytes[3]) + packet_bytes[2]) + packet_bytes[1]); + assign packet_bytes[1] = {1'b0, VIDEO_FORMAT, ACTIVE_FORMAT_INFO_PRESENT, BAR_INFO, SCAN_INFO}; + assign packet_bytes[2] = {COLORIMETRY, PICTURE_ASPECT_RATIO, ACTIVE_FORMAT_ASPECT_RATIO}; + assign packet_bytes[3] = {IT_CONTENT, EXTENDED_COLORIMETRY, RGB_QUANTIZATION_RANGE, NON_UNIFORM_PICTURE_SCALING}; + assign packet_bytes[4] = {1'b0, VIDEO_ID_CODE}; + assign packet_bytes[5] = {YCC_QUANTIZATION_RANGE, CONTENT_TYPE, PIXEL_REPETITION}; + + genvar i; + generate + if (BAR_INFO != 2'b00) begin + assign packet_bytes[6] = 8'hff; + assign packet_bytes[7] = 8'hff; + assign packet_bytes[8] = 8'h00; + assign packet_bytes[9] = 8'h00; + assign packet_bytes[10] = 8'hff; + assign packet_bytes[11] = 8'hff; + assign packet_bytes[12] = 8'h00; + assign packet_bytes[13] = 8'h00; + end + else begin + assign packet_bytes[6] = 8'h00; + assign packet_bytes[7] = 8'h00; + assign packet_bytes[8] = 8'h00; + assign packet_bytes[9] = 8'h00; + assign packet_bytes[10] = 8'h00; + assign packet_bytes[11] = 8'h00; + assign packet_bytes[12] = 8'h00; + assign packet_bytes[13] = 8'h00; + end + for (i = 14; i < 28; i = i + 1) begin : pb_reserved + assign packet_bytes[i] = 8'd0; + end + for (i = 0; i < 4; i = i + 1) begin : pb_to_sub + assign sub[i * 56+:56] = {packet_bytes[6 + (i * 7)], packet_bytes[5 + (i * 7)], packet_bytes[4 + (i * 7)], packet_bytes[3 + (i * 7)], packet_bytes[2 + (i * 7)], packet_bytes[1 + (i * 7)], packet_bytes[i * 7]}; + end + endgenerate +endmodule diff --git a/common/hdmi/hdmi.v b/common/hdmi/hdmi.v new file mode 100644 index 0000000..28d7256 --- /dev/null +++ b/common/hdmi/hdmi.v @@ -0,0 +1,306 @@ +// Implementation of HDMI Spec v1.4a +// By Sameer Puri https://github.com/sameer +// source: https://github.com/hdl-util/hdmi/ +// Dual-licensed under Apache License 2.0 and MIT License. + +// converted to Verilog and stripped down for hsdaoh, +// changed VIDEO_ID_CODE 16 to minimal timings the MS2130 accepts + +module hdmi ( + clk_pixel_x5, + clk_pixel, + reset, + rgb, + tmds, + tmds_clock, + cx, + cy, + frame_width, + frame_height, + screen_width, + screen_height +); + // Defaults to 640x480 which should be supported by almost if not all HDMI sinks. + // See README.md or CEA-861-D for enumeration of video id codes. + // Pixel repetition, interlaced scans and other special output modes are not implemented (yet). + parameter [6:0] VIDEO_ID_CODE = 1; + + // The IT content bit indicates that image samples are generated in an ad-hoc + // manner (e.g. directly from values in a framebuffer, as by a PC video + // card) and therefore aren't suitable for filtering or analog + // reconstruction. This is probably what you want if you treat pixels + // as "squares". If you generate a properly bandlimited signal or obtain + // one from elsewhere (e.g. a camera), this can be turned off. + // + // This flag also tends to cause receivers to treat RGB values as full + // range (0-255). + parameter [0:0] IT_CONTENT = 1'b1; + + // Defaults to minimum bit lengths required to represent positions. + // Modify these parameters if you have alternate desired bit lengths. + parameter [12:0] BIT_WIDTH = (VIDEO_ID_CODE < 4 ? 10 : (VIDEO_ID_CODE == 4 ? 11 : 12)); + parameter [12:0] BIT_HEIGHT = (VIDEO_ID_CODE == 16 ? 11 : 10); + + // A true HDMI signal sends auxiliary data (i.e. audio, preambles) which prevents it from being parsed by DVI signal sinks. + // HDMI signal sinks are fortunately backwards-compatible with DVI signals. + // Enable this flag if the output should be a DVI signal. You might want to do this to reduce resource usage or if you're only outputting video. + parameter [0:0] DVI_OUTPUT = 1'b0; + + // **All parameters below matter ONLY IF you plan on sending auxiliary data (DVI_OUTPUT == 1'b0)** + + // Starting screen coordinate when module comes out of reset. + // + // Setting these to something other than (0, 0) is useful when positioning + // an external video signal within a larger overall frame (e.g. + // letterboxing an input video signal). This allows you to synchronize the + // negative edge of reset directly to the start of the external signal + // instead of to some number of clock cycles before. + // + // You probably don't need to change these parameters if you are + // generating a signal from scratch instead of processing an + // external signal. + parameter [12:0] START_X = 0; + parameter [12:0] START_Y = 0; + + input wire clk_pixel_x5; + input wire clk_pixel; + // synchronous reset back to 0,0 + input wire reset; + input wire [23:0] rgb; + + // These outputs go to your HDMI port + output wire [2:0] tmds; + output wire tmds_clock; + + // All outputs below this line stay inside the FPGA + // They are used (by you) to pick the color each pixel should have + // i.e. always_ff @(posedge pixel_clk) rgb <= {8'd0, 8'(cx), 8'(cy)}; + output reg [BIT_WIDTH - 1:0] cx = START_X; + output reg [BIT_HEIGHT - 1:0] cy = START_Y; + + // The screen is at the upper left corner of the frame. + // 0,0 = 0,0 in video + // the frame includes extra space for sending auxiliary data + output wire [BIT_WIDTH - 1:0] frame_width; + output wire [BIT_HEIGHT - 1:0] frame_height; + output wire [BIT_WIDTH - 1:0] screen_width; + output wire [BIT_HEIGHT - 1:0] screen_height; + + localparam signed [31:0] NUM_CHANNELS = 3; + reg hsync; + reg vsync; + + wire [BIT_WIDTH - 1:0] hsync_pulse_start, hsync_pulse_size; + wire [BIT_HEIGHT - 1:0] vsync_pulse_start, vsync_pulse_size; + wire invert; + + // See CEA-861-D for more specifics formats described below. + generate + case (VIDEO_ID_CODE) + 16, 34: begin : genblk1 + // Those are the patched, minimal timings for video mode 16 that + // work with the MS2130. The inactive video period has been reduced + // significantly. See below (mode 99) for the original timings for + // 1080p + assign frame_width = 1982; + assign frame_height = 1084; + assign screen_width = 1920; + assign screen_height = 1080; + assign hsync_pulse_start = 6; + assign hsync_pulse_size = 4; + assign vsync_pulse_start = 0; + assign vsync_pulse_size = 1; + assign invert = 0; + end + 99: begin : genblk1 + assign frame_width = 2200; + assign frame_height = 1125; + assign screen_width = 1920; + assign screen_height = 1080; + assign hsync_pulse_start = 88; + assign hsync_pulse_size = 44; + assign vsync_pulse_start = 4; + assign vsync_pulse_size = 5; + assign invert = 0; + end + endcase + endgenerate + always @(*) begin + hsync <= invert ^ ((cx >= (screen_width + hsync_pulse_start)) && (cx < ((screen_width + hsync_pulse_start) + hsync_pulse_size))); + // vsync pulses should begin and end at the start of hsync, so special + // handling is required for the lines on which vsync starts and ends + if (cy == ((screen_height + vsync_pulse_start) - 1)) + vsync <= invert ^ (cx >= (screen_width + hsync_pulse_start)); + else if (cy == (((screen_height + vsync_pulse_start) + vsync_pulse_size) - 1)) + vsync <= invert ^ (cx < (screen_width + hsync_pulse_start)); + else + vsync <= invert ^ ((cy >= (screen_height + vsync_pulse_start)) && (cy < ((screen_height + vsync_pulse_start) + vsync_pulse_size))); + end + + // Wrap-around pixel position counters indicating the pixel to be generated by the user in THIS clock and sent out in the NEXT clock. + always @(posedge clk_pixel) + begin + if (reset) begin + cx <= START_X; + cy <= START_Y; + end + else begin + cx <= (cx == (frame_width - 1'b1) ? 0 : cx + 1'b1); + cy <= (cx == (frame_width - 1'b1) ? (cy == (frame_height - 1'b1) ? 0 : cy + 1'b1) : cy); + end + end + + // See Section 5.2 + reg video_data_period = 0; + always @(posedge clk_pixel) + begin + if (reset) + video_data_period <= 0; + else + video_data_period <= (cx < screen_width) && (cy < screen_height); + end + + reg [2:0] mode = 3'd1; + reg [23:0] video_data = 24'd0; + reg [5:0] control_data = 6'd0; + reg [11:0] data_island_data = 12'd0; + + function automatic [4:0] sv2v_cast_5; + input reg [4:0] inp; + sv2v_cast_5 = inp; + endfunction + + generate + if (!DVI_OUTPUT) begin : true_hdmi_output + reg video_guard = 1; + reg video_preamble = 0; + always @(posedge clk_pixel) + begin + if (reset) begin + video_guard <= 1; + video_preamble <= 0; + end + else begin + video_guard <= ((cx >= (frame_width - 2)) && (cx < frame_width)) && ((cy == (frame_height - 1)) || (cy < (screen_height - 1))); + video_preamble <= ((cx >= (frame_width - 10)) && (cx < (frame_width - 2))) && ((cy == (frame_height - 1)) || (cy < (screen_height - 1))); + end + end + + reg [4:0] num_packets_alongside = 1; // patched for hsdaoh: set to minimum required number + + wire data_island_period_instantaneous; + assign data_island_period_instantaneous = ((num_packets_alongside > 0) && (cx >= (screen_width + 14))) && (cx < ((screen_width + 14) + (num_packets_alongside * 32))); + wire packet_enable; + assign packet_enable = data_island_period_instantaneous && (sv2v_cast_5((cx + screen_width) + 18) == 5'd0); + + reg data_island_guard = 0; + reg data_island_preamble = 0; + reg data_island_period = 0; + always @(posedge clk_pixel) + begin + if (reset) begin + data_island_guard <= 0; + data_island_preamble <= 0; + data_island_period <= 0; + end + else begin + data_island_guard <= num_packets_alongside > 0 && ( + (cx >= screen_width + 12 && cx < screen_width + 14) /* leading guard */ || + (cx >= screen_width + 14 + num_packets_alongside * 32 && cx < screen_width + 14 + num_packets_alongside * 32 + 2) /* trailing guard */ + ); + data_island_preamble <= num_packets_alongside > 0 && cx >= screen_width + 4 && cx < screen_width + 12; + data_island_period <= data_island_period_instantaneous; + end + end + + // See Section 5.2.3.4 + wire [23:0] header; + wire [223:0] sub; + wire video_field_end; + assign video_field_end = (cx == (screen_width - 1'b1)) && (cy == (screen_height - 1'b1)); + wire [4:0] packet_pixel_counter; + packet_picker #( + .VIDEO_ID_CODE(VIDEO_ID_CODE) + ) packet_picker( + .clk_pixel(clk_pixel), + .reset(reset), + .video_field_end(video_field_end), + .packet_enable(packet_enable), + .packet_pixel_counter(packet_pixel_counter), + .header(header), + .sub(sub) + ); + wire [8:0] packet_data; + packet_assembler packet_assembler( + .clk_pixel(clk_pixel), + .reset(reset), + .data_island_period(data_island_period), + .header(header), + .sub(sub), + .packet_data(packet_data), + .counter(packet_pixel_counter) + ); + always @(posedge clk_pixel) + if (reset) begin + mode <= 3'd2; + video_data <= 24'd0; + control_data = 6'd0; + data_island_data <= 12'd0; + end + else begin + mode <= (data_island_guard ? 3'd4 : (data_island_period ? 3'd3 : (video_guard ? 3'd2 : (video_data_period ? 3'd1 : 3'd0)))); + video_data <= rgb; + control_data <= {1'b0, data_island_preamble, 1'b0, video_preamble || data_island_preamble, vsync, hsync}; + data_island_data[11:4] <= packet_data[8:1]; + data_island_data[3] <= cx != 0; + data_island_data[2] <= packet_data[0]; + data_island_data[1:0] <= {vsync, hsync}; + end + end + else begin : genblk2 // DVI_OUTPUT = 1 + reg video_guard = 1; + reg video_preamble = 0; + always @(posedge clk_pixel) + if (reset) begin + video_guard <= 1; + mode <= 3'd0; + video_data <= 24'd0; + control_data <= 6'd0; + end + else begin + video_guard <= ((cx >= (frame_width - 2)) && (cx < frame_width)) && ((cy == (frame_height - 1)) || (cy < (screen_height - 1))); + video_preamble <= ((cx >= (frame_width - 10)) && (cx < (frame_width - 2))) && ((cy == (frame_height - 1)) || (cy < (screen_height - 1))); + mode <= (video_data_period ? 3'd1 : (video_guard ? 3'd2 : 3'd0)); + video_data <= rgb; + control_data <= {4'b0000, vsync, hsync}; // ctrl3, ctrl2, ctrl1, ctrl0, vsync, hsync + end + end + endgenerate + + // All logic below relates to the production and output of the 10-bit TMDS code. + wire [29:0] tmds_internal; + genvar i; + generate + // TMDS code production. + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin : tmds_gen + tmds_channel #(.CN(i)) tmds_channel( + .clk_pixel(clk_pixel), + .video_data(video_data[(i * 8) + 7:i * 8]), + .data_island_data(data_island_data[(i * 4) + 3:i * 4]), + .control_data(control_data[(i * 2) + 1:i * 2]), + .mode(mode), + .tmds(tmds_internal[i * 10+:10]) + ); + end + endgenerate + serializer #( + .NUM_CHANNELS(NUM_CHANNELS) + ) serializer( + .clk_pixel(clk_pixel), + .clk_pixel_x5(clk_pixel_x5), + .reset(reset), + .tmds_internal(tmds_internal), + .tmds(tmds), + .tmds_clock(tmds_clock) + ); +endmodule diff --git a/common/hdmi/packet_assembler.v b/common/hdmi/packet_assembler.v new file mode 100644 index 0000000..642ebe0 --- /dev/null +++ b/common/hdmi/packet_assembler.v @@ -0,0 +1,92 @@ +// Implementation of HDMI packet ECC calculation. +// By Sameer Puri https://github.com/sameer +// source: https://github.com/hdl-util/hdmi/ +// Dual-licensed under Apache License 2.0 and MIT License. + +// converted to Verilog for hsdaoh + +module packet_assembler ( + clk_pixel, + reset, + data_island_period, + header, // See Table 5-8 Packet Types + sub, + packet_data, // See Figure 5-4 Data Island Packet and ECC Structure + counter +); + input wire clk_pixel; + input wire reset; + input wire data_island_period; + input wire [23:0] header; + input wire [223:0] sub; + output wire [8:0] packet_data; + output reg [4:0] counter = 5'd0; + + // 32 pixel wrap-around counter. See Section 5.2.3.4 for further information. + always @(posedge clk_pixel) + begin + if (reset) + counter <= 5'd0; + else if (data_island_period) + counter <= counter + 5'd1; + end + // BCH packets 0 to 3 are transferred two bits at a time, see Section 5.2.3.4 for further information. + wire [5:0] counter_t2 = {counter, 1'b0}; + wire [5:0] counter_t2_p1 = {counter, 1'b1}; + + // Initialize parity bits to 0 + reg [39:0] parity = 40'h0000000000; + + wire [63:0] bch [3:0]; + assign bch[0] = {parity[0+:8], sub[0+:56]}; + assign bch[1] = {parity[8+:8], sub[56+:56]}; + assign bch[2] = {parity[16+:8], sub[112+:56]}; + assign bch[3] = {parity[24+:8], sub[168+:56]}; + wire [31:0] bch4 = {parity[32+:8], header}; + assign packet_data = {bch[3][counter_t2_p1], bch[2][counter_t2_p1], bch[1][counter_t2_p1], bch[0][counter_t2_p1], bch[3][counter_t2], bch[2][counter_t2], bch[1][counter_t2], bch[0][counter_t2], bch4[counter]}; + + // See Figure 5-5 Error Correction Code generator. Generalization of a CRC with binary BCH. + // See https://web.archive.org/web/20190520020602/http://hamsterworks.co.nz/mediawiki/index.php/Minimal_HDMI#Computing_the_ECC for an explanation of the implementation. + // See https://en.wikipedia.org/wiki/BCH_code#Systematic_encoding:_The_message_as_a_prefix for further information. + function automatic [7:0] next_ecc; + input [7:0] ecc, next_bch_bit; + begin + next_ecc = (ecc >> 1) ^ (ecc[0] ^ next_bch_bit ? 8'b10000011 : 8'd0); + end + endfunction + + wire [7:0] parity_next [4:0]; + + // The parity needs to be calculated 2 bits at a time for blocks 0 to 3. + // There's 56 bits being sent 2 bits at a time over TMDS channels 1 & 2, so the parity bits wouldn't be ready in time otherwise. + wire [31:0] parity_next_next; + + genvar i; + generate + for (i = 0; i < 5; i = i + 1) begin : parity_calc + if (i == 4) begin : genblk1 + assign parity_next[i] = next_ecc(parity[i * 8+:8], header[counter]); + end + else begin : genblk1 + assign parity_next[i] = next_ecc(parity[i * 8+:8], sub[(i * 56) + counter_t2]); + assign parity_next_next[i * 8+:8] = next_ecc(parity_next[i], sub[(i * 56) + counter_t2_p1]); + end + end + endgenerate + always @(posedge clk_pixel) + begin + if (reset) + parity <= 40'h0000000000; + else if (data_island_period) begin + if (counter < 5'd28) begin // Compute ECC only on subpacket data, not on itself + parity[0+:32] <= parity_next_next; + if (counter < 5'd24) // Header only has 24 bits, whereas subpackets have 56 and 56 / 2 = 28. + parity[32+:8] <= parity_next[4]; + end + else if (counter == 5'd31) + parity <= 40'h0000000000; // Reset ECC for next packet + end + else + parity <= 40'h0000000000; + end +endmodule diff --git a/common/hdmi/packet_picker.v b/common/hdmi/packet_picker.v new file mode 100644 index 0000000..1f38d2d --- /dev/null +++ b/common/hdmi/packet_picker.v @@ -0,0 +1,81 @@ +// Implementation of HDMI packet choice logic. +// By Sameer Puri https://github.com/sameer +// source: https://github.com/hdl-util/hdmi/ +// Dual-licensed under Apache License 2.0 and MIT License. + +// converted to Verilog and removed packets not required for hsdaoh + +module packet_picker ( + clk_pixel, + reset, + video_field_end, + packet_enable, + packet_pixel_counter, + header, + sub +); + parameter [6:0] VIDEO_ID_CODE = 4; + parameter [0:0] IT_CONTENT = 1'b0; + input wire clk_pixel; + input wire reset; + input wire video_field_end; + input wire packet_enable; + input wire [4:0] packet_pixel_counter; + output wire [23:0] header; + output wire [223:0] sub; + + // Connect the current packet type's data to the output. + reg [7:0] packet_type = 8'd0; + wire [23:0] headers [255:0]; + wire [223:0] subs [255:0]; + assign header = headers[packet_type]; + assign sub[0+:56] = subs[packet_type][0+:56]; + assign sub[56+:56] = subs[packet_type][56+:56]; + assign sub[112+:56] = subs[packet_type][112+:56]; + assign sub[168+:56] = subs[packet_type][168+:56]; + + // NULL packet + // "An HDMI Sink shall ignore bytes HB1 and HB2 of the Null Packet Header and all bytes of the Null Packet Body." + assign headers[0] = 24'hxxxx00; + assign subs[0][0+:56] = 56'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign subs[0][56+:56] = 56'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign subs[0][112+:56] = 56'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign subs[0][168+:56] = 56'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + + reg [7:0] frame_counter = 8'd0; + always @(posedge clk_pixel) + begin + if (reset) + frame_counter <= 8'd0; + else if ((packet_pixel_counter == 5'd31) && (packet_type == 8'h02)) begin + frame_counter = frame_counter + 8'd4; + if (frame_counter >= 8'd192) + frame_counter = frame_counter - 8'd192; + end + end + + auxiliary_video_information_info_frame #( + .VIDEO_ID_CODE(VIDEO_ID_CODE), + .IT_CONTENT(IT_CONTENT) + ) auxiliary_video_information_info_frame( + .header(headers[130]), + .sub(subs[130]) + ); + + reg auxiliary_video_information_info_frame_sent = 1'b0; + always @(posedge clk_pixel) + begin + if (reset || video_field_end) begin + auxiliary_video_information_info_frame_sent <= 1'b0; + packet_type <= 8'bxxxxxxxx; + end + else if (packet_enable) begin + if (!auxiliary_video_information_info_frame_sent) begin + packet_type <= 8'h82; + auxiliary_video_information_info_frame_sent <= 1'b1; + end + else + packet_type <= 8'd0; + end + end +endmodule diff --git a/common/hdmi/serializer.v b/common/hdmi/serializer.v new file mode 100644 index 0000000..88e4fc4 --- /dev/null +++ b/common/hdmi/serializer.v @@ -0,0 +1,75 @@ +// TMDS serializer +// By Sameer Puri https://github.com/sameer +// source: https://github.com/hdl-util/hdmi/ +// Dual-licensed under Apache License 2.0 and MIT License. + +// converted to Verilog for hsdaoh +// currently only contains the GOWIN OSER10 primitives +// TODO: add back everything from https://github.com/hdl-util/hdmi/blob/master/src/serializer.sv + +module serializer ( + clk_pixel, + clk_pixel_x5, + reset, + tmds_internal, + tmds, + tmds_clock +); + parameter signed [31:0] NUM_CHANNELS = 3; + parameter real VIDEO_RATE = 0; + input wire clk_pixel; + input wire clk_pixel_x5; + input wire reset; + input wire [(NUM_CHANNELS * 10) - 1:0] tmds_internal; + output wire [2:0] tmds; + output wire tmds_clock; + OSER10 gwSer0( + .Q(tmds[0]), + .D0(tmds_internal[0]), + .D1(tmds_internal[1]), + .D2(tmds_internal[2]), + .D3(tmds_internal[3]), + .D4(tmds_internal[4]), + .D5(tmds_internal[5]), + .D6(tmds_internal[6]), + .D7(tmds_internal[7]), + .D8(tmds_internal[8]), + .D9(tmds_internal[9]), + .PCLK(clk_pixel), + .FCLK(clk_pixel_x5), + .RESET(reset) + ); + OSER10 gwSer1( + .Q(tmds[1]), + .D0(tmds_internal[10]), + .D1(tmds_internal[11]), + .D2(tmds_internal[12]), + .D3(tmds_internal[13]), + .D4(tmds_internal[14]), + .D5(tmds_internal[15]), + .D6(tmds_internal[16]), + .D7(tmds_internal[17]), + .D8(tmds_internal[18]), + .D9(tmds_internal[19]), + .PCLK(clk_pixel), + .FCLK(clk_pixel_x5), + .RESET(reset) + ); + OSER10 gwSer2( + .Q(tmds[2]), + .D0(tmds_internal[20]), + .D1(tmds_internal[21]), + .D2(tmds_internal[22]), + .D3(tmds_internal[23]), + .D4(tmds_internal[24]), + .D5(tmds_internal[25]), + .D6(tmds_internal[26]), + .D7(tmds_internal[27]), + .D8(tmds_internal[28]), + .D9(tmds_internal[29]), + .PCLK(clk_pixel), + .FCLK(clk_pixel_x5), + .RESET(reset) + ); + assign tmds_clock = clk_pixel; +endmodule diff --git a/common/hdmi/tmds_channel.v b/common/hdmi/tmds_channel.v new file mode 100644 index 0000000..6fee6cd --- /dev/null +++ b/common/hdmi/tmds_channel.v @@ -0,0 +1,161 @@ +// Implementation of HDMI Spec v1.4a Section 5.4: Encoding, Section 5.2.2.1: Video Guard Band, Section 5.2.3.3: Data Island Guard Bands. +// By Sameer Puri https://github.com/sameer +// source: https://github.com/hdl-util/hdmi/ +// Dual-licensed under Apache License 2.0 and MIT License. + +// converted to Verilog for hsdaoh + +module tmds_channel ( + clk_pixel, + video_data, + data_island_data, + control_data, + mode, + tmds +); + // TMDS Channel number. + // There are only 3 possible channel numbers in HDMI 1.4a: 0, 1, 2. + parameter [1:0] CN = 0; + + input wire clk_pixel; + input wire [7:0] video_data; + input wire [3:0] data_island_data; + input wire [1:0] control_data; + input wire [2:0] mode; // Mode select (0 = control, 1 = video, 2 = video guard, 3 = island, 4 = island guard) + output reg [9:0] tmds = 10'b1101010100; + + // See Section 5.4.4.1 + // Below is a direct implementation of Figure 5-7, using the same variable names. + reg signed [4:0] acc = 5'sd0; + + reg [8:0] q_m; + reg [9:0] q_out; + wire [9:0] video_coding; + assign video_coding = q_out; + + reg [3:0] N1D; + reg signed [4:0] N1q_m07; + reg signed [4:0] N0q_m07; + always @(*) begin + N1D = video_data[0] + video_data[1] + video_data[2] + video_data[3] + video_data[4] + video_data[5] + video_data[6] + video_data[7]; + case (q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7]) + 4'b0000: N1q_m07 = 5'sd0; + 4'b0001: N1q_m07 = 5'sd1; + 4'b0010: N1q_m07 = 5'sd2; + 4'b0011: N1q_m07 = 5'sd3; + 4'b0100: N1q_m07 = 5'sd4; + 4'b0101: N1q_m07 = 5'sd5; + 4'b0110: N1q_m07 = 5'sd6; + 4'b0111: N1q_m07 = 5'sd7; + 4'b1000: N1q_m07 = 5'sd8; + default: N1q_m07 = 5'sd0; + endcase + N0q_m07 = 5'sd8 - N1q_m07; + end + reg signed [4:0] acc_add; + integer i; + always @(*) begin + if ((N1D > 4'd4) || ((N1D == 4'd4) && (video_data[0] == 1'd0))) begin + q_m[0] = video_data[0]; + for (i = 0; i < 7; i = i + 1) + q_m[i + 1] = q_m[i] ~^ video_data[i + 1]; + q_m[8] = 1'b0; + end + else begin + q_m[0] = video_data[0]; + for (i = 0; i < 7; i = i + 1) + q_m[i + 1] = q_m[i] ^ video_data[i + 1]; + q_m[8] = 1'b1; + end + if ((acc == 5'sd0) || (N1q_m07 == N0q_m07)) begin + if (q_m[8]) begin + acc_add = N1q_m07 - N0q_m07; + q_out = {~q_m[8], q_m[8], q_m[7:0]}; + end + else begin + acc_add = N0q_m07 - N1q_m07; + q_out = {~q_m[8], q_m[8], ~q_m[7:0]}; + end + end + else if (((acc > 5'sd0) && (N1q_m07 > N0q_m07)) || ((acc < 5'sd0) && (N1q_m07 < N0q_m07))) begin + q_out = {1'b1, q_m[8], ~q_m[7:0]}; + acc_add = (N0q_m07 - N1q_m07) + (q_m[8] ? 5'sd2 : 5'sd0); + end + else begin + q_out = {1'b0, q_m[8], q_m[7:0]}; + acc_add = (N1q_m07 - N0q_m07) - (~q_m[8] ? 5'sd2 : 5'sd0); + end + end + + always @(posedge clk_pixel) acc <= (mode != 3'd1 ? 5'sd0 : acc + acc_add); + + // See Section 5.4.2 + reg [9:0] control_coding; + always @(*) + begin + case (control_data) + 2'b00: control_coding = 10'b1101010100; + 2'b01: control_coding = 10'b0010101011; + 2'b10: control_coding = 10'b0101010100; + 2'b11: control_coding = 10'b1010101011; + endcase + end + + // See Section 5.4.3 + reg [9:0] terc4_coding; + always @(*) + begin + case (data_island_data) + 4'b0000: terc4_coding = 10'b1010011100; + 4'b0001: terc4_coding = 10'b1001100011; + 4'b0010: terc4_coding = 10'b1011100100; + 4'b0011: terc4_coding = 10'b1011100010; + 4'b0100: terc4_coding = 10'b0101110001; + 4'b0101: terc4_coding = 10'b0100011110; + 4'b0110: terc4_coding = 10'b0110001110; + 4'b0111: terc4_coding = 10'b0100111100; + 4'b1000: terc4_coding = 10'b1011001100; + 4'b1001: terc4_coding = 10'b0100111001; + 4'b1010: terc4_coding = 10'b0110011100; + 4'b1011: terc4_coding = 10'b1011000110; + 4'b1100: terc4_coding = 10'b1010001110; + 4'b1101: terc4_coding = 10'b1001110001; + 4'b1110: terc4_coding = 10'b0101100011; + 4'b1111: terc4_coding = 10'b1011000011; + endcase + end + + // See Section 5.2.2.1 + wire [9:0] video_guard_band; + generate + if ((CN == 0) || (CN == 2)) begin : genblk1 + assign video_guard_band = 10'b1011001100; + end + else begin : genblk1 + assign video_guard_band = 10'b0100110011; + end + endgenerate + + // See Section 5.2.3.3 + wire [9:0] data_guard_band; + generate + if ((CN == 1) || (CN == 2)) begin : genblk2 + assign data_guard_band = 10'b0100110011; + end + else begin : genblk2 + assign data_guard_band = (control_data == 2'b00 ? 10'b1010001110 : (control_data == 2'b01 ? 10'b1001110001 : (control_data == 2'b10 ? 10'b0101100011 : 10'b1011000011))); + end + endgenerate + + // Apply selected mode. + always @(posedge clk_pixel) + begin + case (mode) + 3'd0: tmds <= control_coding; + 3'd1: tmds <= video_coding; + 3'd2: tmds <= video_guard_band; + 3'd3: tmds <= terc4_coding; + 3'd4: tmds <= data_guard_band; + endcase + end +endmodule diff --git a/common/hsdaoh/hsdaoh_core.v b/common/hsdaoh/hsdaoh_core.v new file mode 100644 index 0000000..8bafc62 --- /dev/null +++ b/common/hsdaoh/hsdaoh_core.v @@ -0,0 +1,133 @@ +// hsdaoh - High Speed Data Acquisition over HDMI +// Implementation of data output +// Copyright (C) 2024 by Steve Markgraf +// License: MIT + +module hsdaoh_core +( + input wire rstn, + output wire tmds_clk_n, + output wire tmds_clk_p, + output wire [2:0] tmds_d_n, + output wire [2:0] tmds_d_p, + input wire clk_pixel_x5, + input wire clk_pixel, + input wire fifo_empty, + input wire fifo_aempty, + output reg fifo_read_en, + input wire [15:0] data_in +); + + localparam [31:0] MAGIC = 32'hda7acab1; + + reg [23:0] hdmi_data = 24'h000000; + reg [15:0] frame_cnt = 16'h0000; + reg [15:0] idle_counter = 16'h0000; + reg [15:0] line_word_cnt = 16'h00; + reg [3:0] status_nibble = 4'h0; + + wire [11:0] cx; + wire [10:0] cy; + wire [11:0] frame_width; + wire [10:0] frame_height; + wire [11:0] screen_width; + wire [10:0] screen_height; + +always @(posedge clk_pixel) begin + + if ((cx == screen_width-1) && (cy < screen_height)) begin + // last word of line contains counter of words per line + hdmi_data <= {status_nibble[3:0], line_word_cnt[11:0], 8'h00}; + + end else if ((cx < screen_width) && (cy < screen_height)) begin + if (fifo_read_en && !fifo_empty) begin + // regular output of FIFO data + hdmi_data <= {data_in[15:0], 8'h00}; + + // increment line payload counter + line_word_cnt <= line_word_cnt + 1'b1; + end else begin + // output idle counter + hdmi_data <= {idle_counter[15:8], idle_counter[7:0], 8'h00}; + + // increment idle counter + idle_counter <= idle_counter + 1'b1; + end + + end else + line_word_cnt <= 16'h0000; + + // Enable reading before beginning of next line + if ((cx == frame_width-1) && (cy < screen_height-1) && !fifo_empty) + fifo_read_en = 1'b1; + + // switch read off during blanking + if (cy > screen_height) + fifo_read_en = 1'b0; + + // switch read off at end of line before sending the word counter + // -2 because the last word is reserved (line_word_cnt and metadata) + if ((cx == screen_width-2) && (cy < screen_height)) + fifo_read_en = 1'b0; + + // switch read off when FIFO has only one word remaining + if (fifo_aempty) + fifo_read_en = 1'b0; + + // increment the frame counter at the end of the frame + if ((cx == frame_width-1) && (cy == frame_height-1)) begin + frame_cnt <= frame_cnt + 1'b1; + line_word_cnt <= 16'h0000; + + // start FIFO readout + if (!fifo_empty) + fifo_read_en = 1'b1; + end + + if (cx == 0) begin + case (cy) + 0 : status_nibble <= MAGIC[3:0]; + 1 : status_nibble <= MAGIC[7:4]; + 2 : status_nibble <= MAGIC[11:8]; + 3 : status_nibble <= MAGIC[15:12]; + 4 : status_nibble <= MAGIC[19:16]; + 5 : status_nibble <= MAGIC[23:20]; + 6 : status_nibble <= MAGIC[27:24]; + 7 : status_nibble <= MAGIC[31:28]; + 8 : status_nibble <= frame_cnt[3:0]; + 9 : status_nibble <= frame_cnt[7:4]; + 10 : status_nibble <= frame_cnt[11:8]; + 11 : status_nibble <= frame_cnt[15:12]; + default : status_nibble <= 4'h0; + endcase + end + +end + + wire tmds_clock; + wire [2:0] tmds; + + hdmi #( + .VIDEO_ID_CODE(16), + .DVI_OUTPUT(0) + ) hdmi( + .clk_pixel_x5(clk_pixel_x5), + .clk_pixel(clk_pixel), + .reset(!rstn), + .rgb(hdmi_data), + .tmds(tmds), + .tmds_clock(tmds_clock), + .cx(cx), + .cy(cy), + .frame_width(frame_width), + .frame_height(frame_height), + .screen_width(screen_width), + .screen_height(screen_height) + ); + ELVDS_OBUF tmds_bufds[3:0]( + .I({clk_pixel, tmds}), + .O({tmds_clk_p, tmds_d_p}), + .OB({tmds_clk_n, tmds_d_n}) + ); + +endmodule diff --git a/hsdaoh_nano20k_test.gprj b/hsdaoh_nano20k_test.gprj new file mode 100644 index 0000000..32a8ed6 --- /dev/null +++ b/hsdaoh_nano20k_test.gprj @@ -0,0 +1,25 @@ + + + + + 5 + gw2ar18c-000 + + + + + + + + + + + + + + + + + + + diff --git a/hsdaoh_nano20k_test/hsdaoh_nano20k_test.cst b/hsdaoh_nano20k_test/hsdaoh_nano20k_test.cst new file mode 100644 index 0000000..c23997b --- /dev/null +++ b/hsdaoh_nano20k_test/hsdaoh_nano20k_test.cst @@ -0,0 +1,47 @@ +//IO_LOC "led[5]" 15; +//IO_PORT "led[5]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; +//IO_LOC "led[4]" 13; +//IO_PORT "led[4]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; +//IO_LOC "led[3]" 10; +//IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; +//IO_LOC "led[2]" 16; +//IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; +//IO_LOC "led[1]" 14; +//IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; +//IO_LOC "led[0]" 11; +//IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; + +IO_LOC "sys_resetn" 88; +IO_PORT "sys_resetn" PULL_MODE=UP; +IO_LOC "sys_clk" 4; + +//IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP; +IO_PORT "sys_clk" PULL_MODE=UP; +IO_LOC "tmds_d_p[0]" 35,36; +IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=8; +IO_LOC "tmds_d_p[1]" 37,38; +IO_PORT "tmds_d_p[1]" PULL_MODE=NONE DRIVE=8; +IO_LOC "tmds_d_p[2]" 39,40; +IO_PORT "tmds_d_p[2]" PULL_MODE=NONE DRIVE=8; +IO_LOC "tmds_clk_p" 33,34; +IO_PORT "tmds_clk_p" PULL_MODE=NONE DRIVE=8; + + + + + + + + + +// 20k example: +//IO_LOC "O_tmds_clk_p" 33,34; +//IO_PORT "O_tmds_clk_p" PULL_MODE=NONE DRIVE=8; +//IO_LOC "O_tmds_data_p[0]" 35,36; +//IO_PORT "O_tmds_data_p[0]" PULL_MODE=NONE DRIVE=8; +//IO_LOC "O_tmds_data_p[1]" 37,38; +//IO_PORT "O_tmds_data_p[1]" PULL_MODE=NONE DRIVE=8; +//IO_LOC "O_tmds_data_p[2]" 39,40; +//IO_PORT "O_tmds_data_p[2]" PULL_MODE=NONE DRIVE=8; +//IO_LOC "I_clk" 4; +//IO_PORT "I_clk" PULL_MODE=UP; \ No newline at end of file diff --git a/hsdaoh_nano20k_test/hsdaoh_nano20k_test.sdc b/hsdaoh_nano20k_test/hsdaoh_nano20k_test.sdc new file mode 100644 index 0000000..55afe1c --- /dev/null +++ b/hsdaoh_nano20k_test/hsdaoh_nano20k_test.sdc @@ -0,0 +1,2 @@ +create_clock -name sys_clk -period 37.04 [get_ports {sys_clk}] -add +//create_clock -name adc_clkout -period 12.3 [get_ports {adc_clkout}] -add \ No newline at end of file diff --git a/hsdaoh_nano20k_test/top.v b/hsdaoh_nano20k_test/top.v new file mode 100644 index 0000000..a172d73 --- /dev/null +++ b/hsdaoh_nano20k_test/top.v @@ -0,0 +1,157 @@ +// hsdaoh - High Speed Data Acquisition over HDMI +// Test top design for Tang Nano 20K +// Copyright (C) 2024 by Steve Markgraf +// License: MIT + +module top ( + sys_clk, + sys_resetn, + enable, + tmds_clk_n, + tmds_clk_p, + tmds_d_n, + tmds_d_p +); + input sys_clk; + input sys_resetn; + input wire enable; + output wire tmds_clk_n; + output wire tmds_clk_p; + output wire [2:0] tmds_d_n; + output wire [2:0] tmds_d_p; + + wire [2:0] tmds; + wire clk_pixel; + wire clk_pixel_x5; + wire hdmi_pll_lock; + + wire clk_data; + wire data_pll_lock; + + // 477 MHz, maximum that works with the nano 20K + // 477/5 = 95.4 MHz + localparam HDMI_PLL_IDIV = 2; + localparam HDMI_PLL_FBDIV = 52; + localparam HDMI_PLL_ODIV = 2; + + // PLL for HDMI clock + rPLL #( + .FCLKIN (27), + .IDIV_SEL (HDMI_PLL_IDIV), + .FBDIV_SEL (HDMI_PLL_FBDIV), + .ODIV_SEL (HDMI_PLL_ODIV), + .DEVICE ("GW2AR-18C") + ) hdmi_pll ( + .CLKIN (sys_clk), + .CLKFB (1'b0), + .RESET (1'b0), + .RESET_P (1'b0), + .FBDSEL (6'b0), + .IDSEL (6'b0), + .ODSEL (6'b0), + .DUTYDA (4'b0), + .PSDA (4'b0), + .FDLY (4'b0), + .CLKOUT (clk_pixel_x5), + .LOCK (hdmi_pll_lock), + .CLKOUTP (), + .CLKOUTD (), + .CLKOUTD3 () + ); + + CLKDIV #( + .DIV_MODE(5), + .GSREN("false") + ) div_5 ( + .CLKOUT(clk_pixel), + .HCLKIN(clk_pixel_x5), + .RESETN(hdmi_pll_lock), + .CALIB(1'b0) + ); + + // 91.8 MHz clock for data + localparam DATA_PLL_IDIV = 4; + localparam DATA_PLL_FBDIV = 16; + localparam DATA_PLL_ODIV = 8; + + // PLL for data clock + rPLL #( + .FCLKIN (27), + .IDIV_SEL (DATA_PLL_IDIV), + .FBDIV_SEL (DATA_PLL_FBDIV), + .ODIV_SEL (DATA_PLL_ODIV), + .DEVICE ("GW2AR-18C") + ) data_pll ( + .CLKIN(sys_clk), + .CLKFB(1'b0), + .RESET(rst), + .RESET_P(1'b0), + .FBDSEL(6'b0), + .IDSEL(6'b0), + .ODSEL(6'b0), + .DUTYDA(4'b0), + .PSDA(4'b0), + .FDLY(4'b0), + .CLKOUT(clk_data), + .LOCK(data_pll_lock), + .CLKOUTP(), + .CLKOUTD(), + .CLKOUTD3() + ); + + reg [15:0] counter = 16'h0000; + + reg [15:0] fifo_in; + + wire write_enable; + + wire [15:0] fifo_out; + wire fifo_empty; + wire fifo_aempty; + wire Full_o; + + wire FifoHalfFull; + wire FifoFull; + + wire fifo_rd_en_i; + async_fifo #( + .DSIZE(16), + .ASIZE($clog2(8192)), // 3 + (1982 * 4) = 7931 => at least 8K entries to buffer 4 lines during VSYNC + .FALLTHROUGH("FALSE") + ) fifo ( + .wclk(clk_data), + .wrst_n(hdmi_pll_lock), + .winc(write_enable), + .wdata(fifo_in), + .wfull(FifoFull), + .awfull(FifoHalfFull), //fixme + .rclk(clk_pixel), + .rrst_n(hdmi_pll_lock), + .rinc(fifo_rd_en_i), + .rdata(fifo_out), + .rempty(fifo_empty), + .arempty(fifo_aempty) + ); + + hsdaoh_core hsdaoh ( + .rstn(hdmi_pll_lock), + .tmds_clk_n(tmds_clk_n), + .tmds_clk_p(tmds_clk_p), + .tmds_d_n(tmds_d_n), + .tmds_d_p(tmds_d_p), + .clk_pixel_x5(clk_pixel_x5), + .clk_pixel(clk_pixel), + .fifo_empty(fifo_empty), + .fifo_aempty(fifo_aempty), + .fifo_read_en(fifo_rd_en_i), + .data_in(fifo_out) + ); + + assign write_enable = 1'b1; + + always @(posedge clk_data) begin + fifo_in <= counter[15:0]; + counter <= counter + 1'b1; + end + +endmodule diff --git a/hsdaoh_nano4k_test.gprj b/hsdaoh_nano4k_test.gprj new file mode 100644 index 0000000..dcb9f28 --- /dev/null +++ b/hsdaoh_nano4k_test.gprj @@ -0,0 +1,26 @@ + + + + + 5 + gw1nsr4c-000 + + + + + + + + + + + + + + + + + + + + diff --git a/hsdaoh_nano4k_test/fifo_hs/fifo_hs.ipc b/hsdaoh_nano4k_test/fifo_hs/fifo_hs.ipc new file mode 100644 index 0000000..9982435 --- /dev/null +++ b/hsdaoh_nano4k_test/fifo_hs/fifo_hs.ipc @@ -0,0 +1,35 @@ +[General] +ipc_version=4 +file=fifo_hs +module=FIFO_HS_Top +target_device=gw1nsr4c-000 +type=fifo_hs +version=1.0 + +[Config] +AlmostEmptyFlag=true +AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter +AlmostFullFlag=false +AlmostFullFlagItem=Full_Single Threshold Constant Parameter +BSRAM=true +ControlledByRdEn=false +ECCSelected=false +EmptyClear=1 +EmptySet=1 +EnReset=false +FirstWordFallThrough=false +FullClear=1 +FullSet=1 +LANG=0 +OutputRegistersSelected=false +REG=false +ReadDataNum=false +ReadDataWidth=16 +ReadDepth=8192 +ResetSynchronization=false +SSRAM=false +StandardFIFO=true +Synthesis_tool=GowinSynthesis +WriteDataNum=false +WriteDataWidth=16 +WriteDepth=8192 diff --git a/hsdaoh_nano4k_test/fifo_hs/fifo_hs.v b/hsdaoh_nano4k_test/fifo_hs/fifo_hs.v new file mode 100644 index 0000000..5a5b68d --- /dev/null +++ b/hsdaoh_nano4k_test/fifo_hs/fifo_hs.v @@ -0,0 +1,841 @@ +// +//Written by GowinSynthesis +//Product Version "V1.9.9 Beta-4 Education" +//Tue Apr 30 20:19:43 2024 + +//Source file index table: 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+qP6gYKeAlaL2DbVnPCBCoCjl0loXzST3wnSNi/CHJ3vEWvFEx0PaxjHg8qbxioj2DchxIzMMWV+K +P1fGC7njrLyxmeW1G0WGW4OPsyHNa5WXusSq54akYJIvvkSHzyM8EhoXFaHx1QRbxW7AvckCJX3l +vu+G6oMlOPW2tXqy45P3aiFQJBCy42jYh8+jvd+n98PRHb9TUDC7SaBB1FR7DxDFPK5JXxM7SY3+ +Ip71ZBnkHCXp5LW1I3EoSlkb1hnL38jUZ56b0mbvdMn/D82xWYiSd0GHay4QQbxMcHhc79Wi2m+b +tsL/Ggk20LhoE3N1UPtr6XvE4kDcGNYhtwRZyI7XAxLnsWM/iMJF8waR39M/pjZB7eBHHyc+dXZk +Shj59SHOSiULHxIdrEhrZOT7CBF1cl0G6QsAzdiqhz2fsegxDBfUPa+WSaAc/7qzoG06PZzlxmO1 +tCnkadwwwR4kHZ0X3C6oQjvpAO8uUSjanKHTBwxA2+yaw54+oqmljLSXIVjCAH/Ali/5n+lvFP50 +zsHHYI/z0QRz4WjfvTUru6g0TjmkhYNaxc/mSTVCMlPgdh7T9aAK/AcRkusqTyG3o9KqTOlq/iuw ++WRxUR1Z2pFdedDCuNLDdEmvZr5ecA8vx0ldsCMtcbjmKHlbEewojlRimG8lrrYRGAEYML0nXJid +17fe+AXTsg/eaxx1MZbJQ2F5XPpXuTN/z/MFBDDvuw5DYw79f3zcEqqM1/Cip9Wj9TkELHvNdu8r +O1dT5ZocJ66yzm+zIxbbBEyDk8t2lgW33ejVSMex37et1BV7LgvfuRXlF0Q8D5plTyhtuT6+meQ1 +5LW4TueSC1+TF1AnusomCNeVpvaxgoWyb+QT8PFUDWgLF0raxo0bzJ/dczbQzRfr9BXJiG2LpqRF +uJdCWRuNEI2BCxI98DYRw7jGy7VKUBeYRVgcwLViEKokXvDy0Jy+u7GEh8ip2r6QxqSraYJWxjaX +TtrxG0dOJZlE9nlkuXmBK72KhCb3KSUaIroYZVC7dCTh3xY2kaReBfucixAVJJs8LuFK2LymL+Qx ++y1S7R9dmsc3CA8yckEmk/zqKGEAKa6c7juURcWYdkWNCebrAF0mlVJfDq6C9dgmsf39zvBWtz8i +Lbnf/fsdE5ogLNm8RhznOkMUpiZ9y1FYvFPCaCJEnfbzNNocaqu8iGLMdimAMLQKZdIhXo6Rdk8r +5glpMWJhADRwOIo78nhOYHj7TKQpzXQqIsCPVax8XQ8rasUqjkVnTLvRBnQTI56oJYjYRw3iE7tt +aMG9qsygvwpjnuhfcMOALj2yPq7Z2YOyIYVlYn05a2bKKGQ74DJ+MHWSoo+LdhYui6tEAEfqMBiA +d5OP1FJwyDr3B8lvdS9G9GMqcBe2PA6IA57Qvmz8LCTvX77ZGj49QcL03tDKuxv0WdZSQvgs8jo6 +OYPumf5eumzGrEoXbo3Nvx3GwQ02PLtWUHxLrQ2+GklXE5lOod1tjifWnATWuLzCWJ/zjF2u83ie +RWHE2e6zLqz+hyxfzc7vk/qqiuxplzGfq9Qj/ICVD3+mbjrcBVnOuUyYKzBhN3kK3HLJUGLGcf2G +Mgic4/PD +`pragma protect end_protected diff --git a/hsdaoh_nano4k_test/fifo_hs/fifo_hs.vo b/hsdaoh_nano4k_test/fifo_hs/fifo_hs.vo new file mode 100644 index 0000000..e28f19f --- /dev/null +++ b/hsdaoh_nano4k_test/fifo_hs/fifo_hs.vo @@ -0,0 +1,2070 @@ +//Copyright (C)2014-2023 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: Post-PnR Simulation Model file +//GOWIN Version: V1.9.9 Beta-4 Education +//Created Time: Tue Apr 30 20:19:43 2024 + +`timescale 100 ps/100 ps +module FIFO_HS_Top( + Data, + WrClk, + RdClk, + WrEn, + RdEn, + Almost_Empty, + Q, + Empty, + Full +); +input [15:0] Data; +input WrClk; +input RdClk; +input WrEn; +input RdEn; +output Almost_Empty; +output [15:0] Q; +output Empty; +output Full; +wire Almost_Empty; +wire [15:0] Data; +wire Empty; +wire Full; +wire GND; +wire [15:0] Q; +wire RdClk; +wire RdEn; +wire VCC; +wire WrClk; +wire WrEn; +wire \fifo_inst/n24_5 ; +wire \fifo_inst/n28_3 ; +wire \fifo_inst/n166_3 ; +wire \fifo_inst/wfull_val ; +wire \fifo_inst/n476_3 ; +wire \fifo_inst/Equal.rgraynext_2_4 ; +wire \fifo_inst/Equal.rgraynext_3_4 ; +wire \fifo_inst/Equal.rgraynext_6_4 ; +wire \fifo_inst/Equal.rgraynext_8_4 ; +wire \fifo_inst/Equal.rgraynext_10_4 ; +wire \fifo_inst/Equal.rgraynext_11_4 ; +wire \fifo_inst/Equal.rgraynext_12_4 ; +wire \fifo_inst/Equal.wcount_r_6_4 ; +wire \fifo_inst/Equal.wcount_r_2_4 ; +wire \fifo_inst/Equal.wgraynext_3_4 ; +wire \fifo_inst/Equal.wgraynext_6_4 ; +wire \fifo_inst/Equal.wgraynext_8_4 ; +wire \fifo_inst/Equal.wgraynext_10_4 ; +wire \fifo_inst/Equal.wgraynext_11_4 ; +wire \fifo_inst/Equal.wgraynext_12_4 ; +wire \fifo_inst/wfull_val_4 ; +wire \fifo_inst/wfull_val_5 ; +wire \fifo_inst/wfull_val_6 ; +wire \fifo_inst/wfull_val_7 ; +wire \fifo_inst/n476_4 ; +wire \fifo_inst/Equal.wbinnext_2_8 ; +wire \fifo_inst/Equal.rgraynext_6_5 ; +wire \fifo_inst/Equal.rgraynext_12_5 ; +wire \fifo_inst/Equal.wgraynext_6_5 ; +wire \fifo_inst/Equal.wgraynext_12_5 ; +wire \fifo_inst/wfull_val_8 ; +wire \fifo_inst/wfull_val_9 ; +wire \fifo_inst/wfull_val_10 ; +wire \fifo_inst/wfull_val_11 ; +wire \fifo_inst/n476_5 ; +wire \fifo_inst/n476_6 ; +wire \fifo_inst/n476_7 ; +wire \fifo_inst/Equal.wcount_r_1_6 ; +wire \fifo_inst/n473_61 ; +wire \fifo_inst/Equal.rgraynext_9_6 ; +wire \fifo_inst/Equal.wgraynext_9_6 ; +wire \fifo_inst/Equal.wbinnext_0_9 ; +wire \fifo_inst/rbin_num_next_0_9 ; +wire \fifo_inst/rempty_val ; +wire \fifo_inst/rempty_val1 ; +wire \fifo_inst/wfull_val1 ; +wire \fifo_inst/rcnt_sub_0_3 ; +wire \fifo_inst/rcnt_sub_1_3 ; +wire \fifo_inst/rcnt_sub_2_3 ; +wire \fifo_inst/rcnt_sub_3_3 ; +wire \fifo_inst/rcnt_sub_4_3 ; +wire \fifo_inst/rcnt_sub_5_3 ; +wire \fifo_inst/rcnt_sub_6_3 ; +wire \fifo_inst/rcnt_sub_7_3 ; +wire \fifo_inst/rcnt_sub_8_3 ; +wire \fifo_inst/rcnt_sub_9_3 ; +wire \fifo_inst/rcnt_sub_10_3 ; +wire \fifo_inst/rcnt_sub_11_3 ; +wire \fifo_inst/rcnt_sub_12_3 ; +wire \fifo_inst/rcnt_sub_13_0_COUT ; +wire \fifo_inst/n106_1_SUM ; +wire \fifo_inst/n106_3 ; +wire \fifo_inst/n107_1_SUM ; +wire \fifo_inst/n107_3 ; +wire \fifo_inst/n108_1_SUM ; +wire \fifo_inst/n108_3 ; +wire \fifo_inst/n109_1_SUM ; +wire \fifo_inst/n109_3 ; +wire \fifo_inst/n110_1_SUM ; +wire \fifo_inst/n110_3 ; +wire \fifo_inst/n111_1_SUM ; +wire \fifo_inst/n111_3 ; +wire \fifo_inst/n112_1_SUM ; +wire \fifo_inst/n112_3 ; +wire \fifo_inst/n113_1_SUM ; +wire \fifo_inst/n113_3 ; +wire \fifo_inst/n114_1_SUM ; +wire \fifo_inst/n114_3 ; +wire \fifo_inst/n115_1_SUM ; +wire \fifo_inst/n115_3 ; +wire \fifo_inst/n116_1_SUM ; +wire \fifo_inst/n116_3 ; +wire \fifo_inst/n117_1_SUM ; +wire \fifo_inst/n117_3 ; +wire \fifo_inst/n118_1_SUM ; +wire \fifo_inst/n118_3 ; +wire [12:0] \fifo_inst/Equal.rgraynext ; +wire [12:0] \fifo_inst/Equal.wcount_r ; +wire [12:0] \fifo_inst/Equal.wgraynext ; +wire [13:1] \fifo_inst/rbin_num_next ; +wire [13:1] \fifo_inst/Equal.wbinnext ; +wire [12:0] \fifo_inst/rbin_num ; +wire [13:0] \fifo_inst/Equal.rq1_wptr ; +wire [13:0] \fifo_inst/Equal.rq2_wptr ; +wire [13:0] \fifo_inst/rptr ; +wire [13:0] \fifo_inst/wptr ; +wire [12:0] \fifo_inst/Equal.wbin ; +wire [13:0] \fifo_inst/Equal.wcount_r_d ; +wire [13:0] \fifo_inst/rcnt_sub_d ; +wire [13:0] \fifo_inst/rcnt_sub ; +wire [31:2] \fifo_inst/DO ; +wire [31:2] \fifo_inst/DO_0 ; +wire [31:2] \fifo_inst/DO_1 ; +wire [31:2] \fifo_inst/DO_2 ; +wire [31:2] \fifo_inst/DO_3 ; +wire [31:2] \fifo_inst/DO_4 ; +wire [31:2] \fifo_inst/DO_5 ; +wire [31:2] \fifo_inst/DO_6 ; +VCC VCC_cZ ( + .V(VCC) +); +GND GND_cZ ( + .G(GND) +); +GSR GSR ( + .GSRI(VCC) +); +LUT2 \fifo_inst/n24_s1 ( + .I0(Full), + .I1(WrEn), + .F(\fifo_inst/n24_5 ) +); +defparam \fifo_inst/n24_s1 .INIT=4'h4; +LUT2 \fifo_inst/n28_s0 ( + .I0(Empty), + .I1(RdEn), + .F(\fifo_inst/n28_3 ) +); +defparam \fifo_inst/n28_s0 .INIT=4'h4; +LUT3 \fifo_inst/Equal.rgraynext_2_s0 ( + .I0(\fifo_inst/rbin_num [2]), + .I1(\fifo_inst/Equal.rgraynext_2_4 ), + .I2(\fifo_inst/rbin_num [3]), + .F(\fifo_inst/Equal.rgraynext [2]) +); +defparam \fifo_inst/Equal.rgraynext_2_s0 .INIT=8'h1E; +LUT3 \fifo_inst/Equal.rgraynext_3_s0 ( + .I0(\fifo_inst/rbin_num [4]), + .I1(\fifo_inst/rbin_num_next [3]), + .I2(\fifo_inst/Equal.rgraynext_3_4 ), + .F(\fifo_inst/Equal.rgraynext [3]) +); +defparam \fifo_inst/Equal.rgraynext_3_s0 .INIT=8'h96; +LUT3 \fifo_inst/Equal.rgraynext_4_s0 ( + .I0(\fifo_inst/rbin_num [4]), + .I1(\fifo_inst/Equal.rgraynext_3_4 ), + .I2(\fifo_inst/rbin_num [5]), + .F(\fifo_inst/Equal.rgraynext [4]) +); +defparam \fifo_inst/Equal.rgraynext_4_s0 .INIT=8'h1E; +LUT4 \fifo_inst/Equal.rgraynext_5_s0 ( + .I0(\fifo_inst/rbin_num [4]), + .I1(\fifo_inst/Equal.rgraynext_3_4 ), + .I2(\fifo_inst/rbin_num [5]), + .I3(\fifo_inst/rbin_num [6]), + .F(\fifo_inst/Equal.rgraynext [5]) +); +defparam \fifo_inst/Equal.rgraynext_5_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.rgraynext_7_s0 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/Equal.rgraynext_6_4 ), + .I2(\fifo_inst/rbin_num [7]), + .I3(\fifo_inst/rbin_num [8]), + .F(\fifo_inst/Equal.rgraynext [7]) +); +defparam \fifo_inst/Equal.rgraynext_7_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.rgraynext_8_s0 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/Equal.rgraynext_8_4 ), + .I2(\fifo_inst/rbin_num [8]), + .I3(\fifo_inst/rbin_num [9]), + .F(\fifo_inst/Equal.rgraynext [8]) +); +defparam \fifo_inst/Equal.rgraynext_8_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.rgraynext_9_s0 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/Equal.rgraynext_9_6 ), + .I2(\fifo_inst/rbin_num [9]), + .I3(\fifo_inst/rbin_num [10]), + .F(\fifo_inst/Equal.rgraynext [9]) +); +defparam \fifo_inst/Equal.rgraynext_9_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.rgraynext_10_s0 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/Equal.rgraynext_10_4 ), + .I2(\fifo_inst/rbin_num [10]), + .I3(\fifo_inst/rbin_num [11]), + .F(\fifo_inst/Equal.rgraynext [10]) +); +defparam \fifo_inst/Equal.rgraynext_10_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.rgraynext_11_s0 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/Equal.rgraynext_11_4 ), + .I2(\fifo_inst/rbin_num [11]), + .I3(\fifo_inst/rbin_num [12]), + .F(\fifo_inst/Equal.rgraynext [11]) +); +defparam \fifo_inst/Equal.rgraynext_11_s0 .INIT=16'h07F8; +LUT3 \fifo_inst/Equal.rgraynext_12_s0 ( + .I0(\fifo_inst/rbin_num [12]), + .I1(\fifo_inst/Equal.rgraynext_12_4 ), + .I2(\fifo_inst/rptr [13]), + .F(\fifo_inst/Equal.rgraynext [12]) +); +defparam \fifo_inst/Equal.rgraynext_12_s0 .INIT=8'h1E; +LUT2 \fifo_inst/Equal.wcount_r_12_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [13]), + .I1(\fifo_inst/Equal.rq2_wptr [12]), + .F(\fifo_inst/Equal.wcount_r [12]) +); +defparam \fifo_inst/Equal.wcount_r_12_s0 .INIT=4'h6; +LUT4 \fifo_inst/Equal.wcount_r_10_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [13]), + .I1(\fifo_inst/Equal.rq2_wptr [12]), + .I2(\fifo_inst/Equal.rq2_wptr [11]), + .I3(\fifo_inst/Equal.rq2_wptr [10]), + .F(\fifo_inst/Equal.wcount_r [10]) +); +defparam \fifo_inst/Equal.wcount_r_10_s0 .INIT=16'h6996; +LUT2 \fifo_inst/Equal.wcount_r_9_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [9]), + .I1(\fifo_inst/Equal.wcount_r [10]), + .F(\fifo_inst/Equal.wcount_r [9]) +); +defparam \fifo_inst/Equal.wcount_r_9_s0 .INIT=4'h6; +LUT3 \fifo_inst/Equal.wcount_r_6_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [9]), + .I1(\fifo_inst/Equal.wcount_r [10]), + .I2(\fifo_inst/Equal.wcount_r_6_4 ), + .F(\fifo_inst/Equal.wcount_r [6]) +); +defparam \fifo_inst/Equal.wcount_r_6_s0 .INIT=8'h69; +LUT3 \fifo_inst/Equal.wcount_r_4_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [5]), + .I1(\fifo_inst/Equal.rq2_wptr [4]), + .I2(\fifo_inst/Equal.wcount_r [6]), + .F(\fifo_inst/Equal.wcount_r [4]) +); +defparam \fifo_inst/Equal.wcount_r_4_s0 .INIT=8'h96; +LUT4 \fifo_inst/Equal.wcount_r_3_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [5]), + .I1(\fifo_inst/Equal.rq2_wptr [4]), + .I2(\fifo_inst/Equal.rq2_wptr [3]), + .I3(\fifo_inst/Equal.wcount_r [6]), + .F(\fifo_inst/Equal.wcount_r [3]) +); +defparam \fifo_inst/Equal.wcount_r_3_s0 .INIT=16'h6996; +LUT3 \fifo_inst/Equal.wcount_r_2_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [5]), + .I1(\fifo_inst/Equal.wcount_r [6]), + .I2(\fifo_inst/Equal.wcount_r_2_4 ), + .F(\fifo_inst/Equal.wcount_r [2]) +); +defparam \fifo_inst/Equal.wcount_r_2_s0 .INIT=8'h69; +LUT3 \fifo_inst/Equal.wcount_r_1_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [5]), + .I1(\fifo_inst/Equal.wcount_r [6]), + .I2(\fifo_inst/Equal.wcount_r_1_6 ), + .F(\fifo_inst/Equal.wcount_r [1]) +); +defparam \fifo_inst/Equal.wcount_r_1_s0 .INIT=8'h96; +LUT4 \fifo_inst/Equal.wcount_r_0_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [5]), + .I1(\fifo_inst/Equal.rq2_wptr [0]), + .I2(\fifo_inst/Equal.wcount_r [6]), + .I3(\fifo_inst/Equal.wcount_r_1_6 ), + .F(\fifo_inst/Equal.wcount_r [0]) +); +defparam \fifo_inst/Equal.wcount_r_0_s0 .INIT=16'h6996; +LUT2 \fifo_inst/n166_s0 ( + .I0(\fifo_inst/rptr [13]), + .I1(\fifo_inst/Equal.wcount_r_d [13]), + .F(\fifo_inst/n166_3 ) +); +defparam \fifo_inst/n166_s0 .INIT=4'h6; +LUT3 \fifo_inst/Equal.wgraynext_3_s0 ( + .I0(\fifo_inst/Equal.wbin [4]), + .I1(\fifo_inst/Equal.wbinnext [3]), + .I2(\fifo_inst/Equal.wgraynext_3_4 ), + .F(\fifo_inst/Equal.wgraynext [3]) +); +defparam \fifo_inst/Equal.wgraynext_3_s0 .INIT=8'h96; +LUT3 \fifo_inst/Equal.wgraynext_4_s0 ( + .I0(\fifo_inst/Equal.wbin [4]), + .I1(\fifo_inst/Equal.wgraynext_3_4 ), + .I2(\fifo_inst/Equal.wbin [5]), + .F(\fifo_inst/Equal.wgraynext [4]) +); +defparam \fifo_inst/Equal.wgraynext_4_s0 .INIT=8'h1E; +LUT4 \fifo_inst/Equal.wgraynext_5_s0 ( + .I0(\fifo_inst/Equal.wbin [4]), + .I1(\fifo_inst/Equal.wgraynext_3_4 ), + .I2(\fifo_inst/Equal.wbin [5]), + .I3(\fifo_inst/Equal.wbin [6]), + .F(\fifo_inst/Equal.wgraynext [5]) +); +defparam \fifo_inst/Equal.wgraynext_5_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.wgraynext_7_s0 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wgraynext_6_4 ), + .I2(\fifo_inst/Equal.wbin [7]), + .I3(\fifo_inst/Equal.wbin [8]), + .F(\fifo_inst/Equal.wgraynext [7]) +); +defparam \fifo_inst/Equal.wgraynext_7_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.wgraynext_8_s0 ( + .I0(\fifo_inst/Equal.wgraynext_6_4 ), + .I1(\fifo_inst/Equal.wgraynext_8_4 ), + .I2(\fifo_inst/Equal.wbin [8]), + .I3(\fifo_inst/Equal.wbin [9]), + .F(\fifo_inst/Equal.wgraynext [8]) +); +defparam \fifo_inst/Equal.wgraynext_8_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.wgraynext_9_s0 ( + .I0(\fifo_inst/Equal.wgraynext_6_4 ), + .I1(\fifo_inst/Equal.wgraynext_9_6 ), + .I2(\fifo_inst/Equal.wbin [9]), + .I3(\fifo_inst/Equal.wbin [10]), + .F(\fifo_inst/Equal.wgraynext [9]) +); +defparam \fifo_inst/Equal.wgraynext_9_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.wgraynext_10_s0 ( + .I0(\fifo_inst/Equal.wgraynext_6_4 ), + .I1(\fifo_inst/Equal.wgraynext_10_4 ), + .I2(\fifo_inst/Equal.wbin [10]), + .I3(\fifo_inst/Equal.wbin [11]), + .F(\fifo_inst/Equal.wgraynext [10]) +); +defparam \fifo_inst/Equal.wgraynext_10_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.wgraynext_11_s0 ( + .I0(\fifo_inst/Equal.wgraynext_6_4 ), + .I1(\fifo_inst/Equal.wgraynext_11_4 ), + .I2(\fifo_inst/Equal.wbin [11]), + .I3(\fifo_inst/Equal.wbin [12]), + .F(\fifo_inst/Equal.wgraynext [11]) +); +defparam \fifo_inst/Equal.wgraynext_11_s0 .INIT=16'h07F8; +LUT3 \fifo_inst/Equal.wgraynext_12_s0 ( + .I0(\fifo_inst/Equal.wbin [12]), + .I1(\fifo_inst/Equal.wgraynext_12_4 ), + .I2(\fifo_inst/wptr [13]), + .F(\fifo_inst/Equal.wgraynext [12]) +); +defparam \fifo_inst/Equal.wgraynext_12_s0 .INIT=8'h1E; +LUT4 \fifo_inst/wfull_val_s0 ( + .I0(\fifo_inst/wfull_val_4 ), + .I1(\fifo_inst/wfull_val_5 ), + .I2(\fifo_inst/wfull_val_6 ), + .I3(\fifo_inst/wfull_val_7 ), + .F(\fifo_inst/wfull_val ) +); +defparam \fifo_inst/wfull_val_s0 .INIT=16'h8000; +LUT4 \fifo_inst/n476_s0 ( + .I0(\fifo_inst/rcnt_sub_d [0]), + .I1(RdEn), + .I2(\fifo_inst/rcnt_sub_d [1]), + .I3(\fifo_inst/n476_4 ), + .F(\fifo_inst/n476_3 ) +); +defparam \fifo_inst/n476_s0 .INIT=16'h4000; +LUT2 \fifo_inst/rbin_num_next_2_s3 ( + .I0(\fifo_inst/rbin_num [2]), + .I1(\fifo_inst/Equal.rgraynext_2_4 ), + .F(\fifo_inst/rbin_num_next [2]) +); +defparam \fifo_inst/rbin_num_next_2_s3 .INIT=4'h6; +LUT3 \fifo_inst/rbin_num_next_3_s3 ( + .I0(\fifo_inst/rbin_num [2]), + .I1(\fifo_inst/Equal.rgraynext_2_4 ), + .I2(\fifo_inst/rbin_num [3]), + .F(\fifo_inst/rbin_num_next [3]) +); +defparam \fifo_inst/rbin_num_next_3_s3 .INIT=8'h78; +LUT3 \fifo_inst/rbin_num_next_5_s3 ( + .I0(\fifo_inst/rbin_num [4]), + .I1(\fifo_inst/Equal.rgraynext_3_4 ), + .I2(\fifo_inst/rbin_num [5]), + .F(\fifo_inst/rbin_num_next [5]) +); +defparam \fifo_inst/rbin_num_next_5_s3 .INIT=8'h78; +LUT2 \fifo_inst/rbin_num_next_12_s3 ( + .I0(\fifo_inst/rbin_num [12]), + .I1(\fifo_inst/Equal.rgraynext_12_4 ), + .F(\fifo_inst/rbin_num_next [12]) +); +defparam \fifo_inst/rbin_num_next_12_s3 .INIT=4'h6; +LUT3 \fifo_inst/rbin_num_next_13_s2 ( + .I0(\fifo_inst/rbin_num [12]), + .I1(\fifo_inst/Equal.rgraynext_12_4 ), + .I2(\fifo_inst/rptr [13]), + .F(\fifo_inst/rbin_num_next [13]) +); +defparam \fifo_inst/rbin_num_next_13_s2 .INIT=8'h78; +LUT2 \fifo_inst/Equal.wbinnext_2_s3 ( + .I0(\fifo_inst/Equal.wbin [2]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .F(\fifo_inst/Equal.wbinnext [2]) +); +defparam \fifo_inst/Equal.wbinnext_2_s3 .INIT=4'h6; +LUT3 \fifo_inst/Equal.wbinnext_3_s3 ( + .I0(\fifo_inst/Equal.wbin [2]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wbin [3]), + .F(\fifo_inst/Equal.wbinnext [3]) +); +defparam \fifo_inst/Equal.wbinnext_3_s3 .INIT=8'h78; +LUT3 \fifo_inst/Equal.wbinnext_5_s3 ( + .I0(\fifo_inst/Equal.wbin [4]), + .I1(\fifo_inst/Equal.wgraynext_3_4 ), + .I2(\fifo_inst/Equal.wbin [5]), + .F(\fifo_inst/Equal.wbinnext [5]) +); +defparam \fifo_inst/Equal.wbinnext_5_s3 .INIT=8'h78; +LUT2 \fifo_inst/Equal.wbinnext_12_s3 ( + .I0(\fifo_inst/Equal.wbin [12]), + .I1(\fifo_inst/Equal.wgraynext_12_4 ), + .F(\fifo_inst/Equal.wbinnext [12]) +); +defparam \fifo_inst/Equal.wbinnext_12_s3 .INIT=4'h6; +LUT3 \fifo_inst/Equal.wbinnext_13_s2 ( + .I0(\fifo_inst/Equal.wbin [12]), + .I1(\fifo_inst/Equal.wgraynext_12_4 ), + .I2(\fifo_inst/wptr [13]), + .F(\fifo_inst/Equal.wbinnext [13]) +); +defparam \fifo_inst/Equal.wbinnext_13_s2 .INIT=8'h78; +LUT4 \fifo_inst/Equal.rgraynext_2_s1 ( + .I0(Empty), + .I1(RdEn), + .I2(\fifo_inst/rbin_num [0]), + .I3(\fifo_inst/rbin_num [1]), + .F(\fifo_inst/Equal.rgraynext_2_4 ) +); +defparam \fifo_inst/Equal.rgraynext_2_s1 .INIT=16'h4000; +LUT3 \fifo_inst/Equal.rgraynext_3_s1 ( + .I0(\fifo_inst/rbin_num [2]), + .I1(\fifo_inst/rbin_num [3]), + .I2(\fifo_inst/Equal.rgraynext_2_4 ), + .F(\fifo_inst/Equal.rgraynext_3_4 ) +); +defparam \fifo_inst/Equal.rgraynext_3_s1 .INIT=8'h80; +LUT2 \fifo_inst/Equal.rgraynext_6_s1 ( + .I0(\fifo_inst/Equal.rgraynext_2_4 ), + .I1(\fifo_inst/Equal.rgraynext_6_5 ), + .F(\fifo_inst/Equal.rgraynext_6_4 ) +); +defparam \fifo_inst/Equal.rgraynext_6_s1 .INIT=4'h8; +LUT2 \fifo_inst/Equal.rgraynext_8_s1 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/rbin_num [7]), + .F(\fifo_inst/Equal.rgraynext_8_4 ) +); +defparam \fifo_inst/Equal.rgraynext_8_s1 .INIT=4'h8; +LUT4 \fifo_inst/Equal.rgraynext_10_s1 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/rbin_num [7]), + .I2(\fifo_inst/rbin_num [8]), + .I3(\fifo_inst/rbin_num [9]), + .F(\fifo_inst/Equal.rgraynext_10_4 ) +); +defparam \fifo_inst/Equal.rgraynext_10_s1 .INIT=16'h8000; +LUT2 \fifo_inst/Equal.rgraynext_11_s1 ( + .I0(\fifo_inst/rbin_num [10]), + .I1(\fifo_inst/Equal.rgraynext_10_4 ), + .F(\fifo_inst/Equal.rgraynext_11_4 ) +); +defparam \fifo_inst/Equal.rgraynext_11_s1 .INIT=4'h8; +LUT4 \fifo_inst/Equal.rgraynext_12_s1 ( + .I0(\fifo_inst/Equal.rgraynext_2_4 ), + .I1(\fifo_inst/Equal.rgraynext_6_5 ), + .I2(\fifo_inst/Equal.rgraynext_12_5 ), + .I3(\fifo_inst/Equal.rgraynext_10_4 ), + .F(\fifo_inst/Equal.rgraynext_12_4 ) +); +defparam \fifo_inst/Equal.rgraynext_12_s1 .INIT=16'h8000; +LUT3 \fifo_inst/Equal.wcount_r_6_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [8]), + .I1(\fifo_inst/Equal.rq2_wptr [7]), + .I2(\fifo_inst/Equal.rq2_wptr [6]), + .F(\fifo_inst/Equal.wcount_r_6_4 ) +); +defparam \fifo_inst/Equal.wcount_r_6_s1 .INIT=8'h69; +LUT3 \fifo_inst/Equal.wcount_r_2_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [4]), + .I1(\fifo_inst/Equal.rq2_wptr [3]), + .I2(\fifo_inst/Equal.rq2_wptr [2]), + .F(\fifo_inst/Equal.wcount_r_2_4 ) +); +defparam \fifo_inst/Equal.wcount_r_2_s1 .INIT=8'h69; +LUT3 \fifo_inst/Equal.wgraynext_3_s1 ( + .I0(\fifo_inst/Equal.wbin [2]), + .I1(\fifo_inst/Equal.wbin [3]), + .I2(\fifo_inst/Equal.wbinnext_2_8 ), + .F(\fifo_inst/Equal.wgraynext_3_4 ) +); +defparam \fifo_inst/Equal.wgraynext_3_s1 .INIT=8'h80; +LUT2 \fifo_inst/Equal.wgraynext_6_s1 ( + .I0(\fifo_inst/Equal.wbinnext_2_8 ), + .I1(\fifo_inst/Equal.wgraynext_6_5 ), + .F(\fifo_inst/Equal.wgraynext_6_4 ) +); +defparam \fifo_inst/Equal.wgraynext_6_s1 .INIT=4'h8; +LUT2 \fifo_inst/Equal.wgraynext_8_s1 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbin [7]), + .F(\fifo_inst/Equal.wgraynext_8_4 ) +); +defparam \fifo_inst/Equal.wgraynext_8_s1 .INIT=4'h8; +LUT4 \fifo_inst/Equal.wgraynext_10_s1 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbin [7]), + .I2(\fifo_inst/Equal.wbin [8]), + .I3(\fifo_inst/Equal.wbin [9]), + .F(\fifo_inst/Equal.wgraynext_10_4 ) +); +defparam \fifo_inst/Equal.wgraynext_10_s1 .INIT=16'h8000; +LUT2 \fifo_inst/Equal.wgraynext_11_s1 ( + .I0(\fifo_inst/Equal.wbin [10]), + .I1(\fifo_inst/Equal.wgraynext_10_4 ), + .F(\fifo_inst/Equal.wgraynext_11_4 ) +); +defparam \fifo_inst/Equal.wgraynext_11_s1 .INIT=4'h8; +LUT4 \fifo_inst/Equal.wgraynext_12_s1 ( + .I0(\fifo_inst/Equal.wbinnext_2_8 ), + .I1(\fifo_inst/Equal.wgraynext_6_5 ), + .I2(\fifo_inst/Equal.wgraynext_12_5 ), + .I3(\fifo_inst/Equal.wgraynext_10_4 ), + .F(\fifo_inst/Equal.wgraynext_12_4 ) +); +defparam \fifo_inst/Equal.wgraynext_12_s1 .INIT=16'h8000; +LUT4 \fifo_inst/wfull_val_s1 ( + .I0(\fifo_inst/wptr [2]), + .I1(\fifo_inst/rptr [2]), + .I2(\fifo_inst/wptr [13]), + .I3(\fifo_inst/rptr [13]), + .F(\fifo_inst/wfull_val_4 ) +); +defparam \fifo_inst/wfull_val_s1 .INIT=16'h0990; +LUT4 \fifo_inst/wfull_val_s2 ( + .I0(\fifo_inst/wptr [0]), + .I1(\fifo_inst/rptr [0]), + .I2(\fifo_inst/wptr [8]), + .I3(\fifo_inst/rptr [8]), + .F(\fifo_inst/wfull_val_5 ) +); +defparam \fifo_inst/wfull_val_s2 .INIT=16'h9009; +LUT4 \fifo_inst/wfull_val_s3 ( + .I0(\fifo_inst/wptr [6]), + .I1(\fifo_inst/rptr [6]), + .I2(\fifo_inst/wptr [10]), + .I3(\fifo_inst/rptr [10]), + .F(\fifo_inst/wfull_val_6 ) +); +defparam \fifo_inst/wfull_val_s3 .INIT=16'h9009; +LUT4 \fifo_inst/wfull_val_s4 ( + .I0(\fifo_inst/wfull_val_8 ), + .I1(\fifo_inst/wfull_val_9 ), + .I2(\fifo_inst/wfull_val_10 ), + .I3(\fifo_inst/wfull_val_11 ), + .F(\fifo_inst/wfull_val_7 ) +); +defparam \fifo_inst/wfull_val_s4 .INIT=16'h8000; +LUT3 \fifo_inst/n476_s1 ( + .I0(\fifo_inst/n476_5 ), + .I1(\fifo_inst/n476_6 ), + .I2(\fifo_inst/n476_7 ), + .F(\fifo_inst/n476_4 ) +); +defparam \fifo_inst/n476_s1 .INIT=8'h80; +LUT4 \fifo_inst/Equal.wbinnext_2_s4 ( + .I0(Full), + .I1(WrEn), + .I2(\fifo_inst/Equal.wbin [0]), + .I3(\fifo_inst/Equal.wbin [1]), + .F(\fifo_inst/Equal.wbinnext_2_8 ) +); +defparam \fifo_inst/Equal.wbinnext_2_s4 .INIT=16'h4000; +LUT4 \fifo_inst/Equal.rgraynext_6_s2 ( + .I0(\fifo_inst/rbin_num [2]), + .I1(\fifo_inst/rbin_num [3]), + .I2(\fifo_inst/rbin_num [4]), + .I3(\fifo_inst/rbin_num [5]), + .F(\fifo_inst/Equal.rgraynext_6_5 ) +); +defparam \fifo_inst/Equal.rgraynext_6_s2 .INIT=16'h8000; +LUT4 \fifo_inst/Equal.rgraynext_12_s2 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/rbin_num [7]), + .I2(\fifo_inst/rbin_num [10]), + .I3(\fifo_inst/rbin_num [11]), + .F(\fifo_inst/Equal.rgraynext_12_5 ) +); +defparam \fifo_inst/Equal.rgraynext_12_s2 .INIT=16'h8000; +LUT4 \fifo_inst/Equal.wgraynext_6_s2 ( + .I0(\fifo_inst/Equal.wbin [2]), + .I1(\fifo_inst/Equal.wbin [3]), + .I2(\fifo_inst/Equal.wbin [4]), + .I3(\fifo_inst/Equal.wbin [5]), + .F(\fifo_inst/Equal.wgraynext_6_5 ) +); +defparam \fifo_inst/Equal.wgraynext_6_s2 .INIT=16'h8000; +LUT4 \fifo_inst/Equal.wgraynext_12_s2 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbin [7]), + .I2(\fifo_inst/Equal.wbin [10]), + .I3(\fifo_inst/Equal.wbin [11]), + .F(\fifo_inst/Equal.wgraynext_12_5 ) +); +defparam \fifo_inst/Equal.wgraynext_12_s2 .INIT=16'h8000; +LUT4 \fifo_inst/wfull_val_s5 ( + .I0(\fifo_inst/wptr [3]), + .I1(\fifo_inst/rptr [3]), + .I2(\fifo_inst/wptr [4]), + .I3(\fifo_inst/rptr [4]), + .F(\fifo_inst/wfull_val_8 ) +); +defparam \fifo_inst/wfull_val_s5 .INIT=16'h9009; +LUT4 \fifo_inst/wfull_val_s6 ( + .I0(\fifo_inst/wptr [5]), + .I1(\fifo_inst/rptr [5]), + .I2(\fifo_inst/wptr [9]), + .I3(\fifo_inst/rptr [9]), + .F(\fifo_inst/wfull_val_9 ) +); +defparam \fifo_inst/wfull_val_s6 .INIT=16'h9009; +LUT4 \fifo_inst/wfull_val_s7 ( + .I0(\fifo_inst/wptr [7]), + .I1(\fifo_inst/rptr [7]), + .I2(\fifo_inst/wptr [11]), + .I3(\fifo_inst/rptr [11]), + .F(\fifo_inst/wfull_val_10 ) +); +defparam \fifo_inst/wfull_val_s7 .INIT=16'h9009; +LUT4 \fifo_inst/wfull_val_s8 ( + .I0(\fifo_inst/wptr [1]), + .I1(\fifo_inst/rptr [1]), + .I2(\fifo_inst/wptr [12]), + .I3(\fifo_inst/rptr [12]), + .F(\fifo_inst/wfull_val_11 ) +); +defparam \fifo_inst/wfull_val_s8 .INIT=16'h0990; +LUT4 \fifo_inst/n476_s2 ( + .I0(\fifo_inst/rcnt_sub_d [10]), + .I1(\fifo_inst/rcnt_sub_d [11]), + .I2(\fifo_inst/rcnt_sub_d [12]), + .I3(\fifo_inst/rcnt_sub_d [13]), + .F(\fifo_inst/n476_5 ) +); +defparam \fifo_inst/n476_s2 .INIT=16'h0001; +LUT4 \fifo_inst/n476_s3 ( + .I0(\fifo_inst/rcnt_sub_d [6]), + .I1(\fifo_inst/rcnt_sub_d [7]), + .I2(\fifo_inst/rcnt_sub_d [8]), + .I3(\fifo_inst/rcnt_sub_d [9]), + .F(\fifo_inst/n476_6 ) +); +defparam \fifo_inst/n476_s3 .INIT=16'h0001; +LUT4 \fifo_inst/n476_s4 ( + .I0(\fifo_inst/rcnt_sub_d [2]), + .I1(\fifo_inst/rcnt_sub_d [3]), + .I2(\fifo_inst/rcnt_sub_d [4]), + .I3(\fifo_inst/rcnt_sub_d [5]), + .F(\fifo_inst/n476_7 ) +); +defparam \fifo_inst/n476_s4 .INIT=16'h0001; +LUT4 \fifo_inst/rbin_num_next_11_s4 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/rbin_num [10]), + .I2(\fifo_inst/Equal.rgraynext_10_4 ), + .I3(\fifo_inst/rbin_num [11]), + .F(\fifo_inst/rbin_num_next [11]) +); +defparam \fifo_inst/rbin_num_next_11_s4 .INIT=16'h7F80; +LUT3 \fifo_inst/Equal.wcount_r_11_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [11]), + .I1(\fifo_inst/Equal.rq2_wptr [13]), + .I2(\fifo_inst/Equal.rq2_wptr [12]), + .F(\fifo_inst/Equal.wcount_r [11]) +); +defparam \fifo_inst/Equal.wcount_r_11_s1 .INIT=8'h96; +LUT4 \fifo_inst/Equal.wcount_r_1_s2 ( + .I0(\fifo_inst/Equal.rq2_wptr [1]), + .I1(\fifo_inst/Equal.rq2_wptr [4]), + .I2(\fifo_inst/Equal.rq2_wptr [3]), + .I3(\fifo_inst/Equal.rq2_wptr [2]), + .F(\fifo_inst/Equal.wcount_r_1_6 ) +); +defparam \fifo_inst/Equal.wcount_r_1_s2 .INIT=16'h6996; +LUT4 \fifo_inst/Equal.wbinnext_11_s4 ( + .I0(\fifo_inst/Equal.wgraynext_6_4 ), + .I1(\fifo_inst/Equal.wbin [10]), + .I2(\fifo_inst/Equal.wgraynext_10_4 ), + .I3(\fifo_inst/Equal.wbin [11]), + .F(\fifo_inst/Equal.wbinnext [11]) +); +defparam \fifo_inst/Equal.wbinnext_11_s4 .INIT=16'h7F80; +LUT4 \fifo_inst/n473_s43 ( + .I0(\fifo_inst/rcnt_sub_d [1]), + .I1(\fifo_inst/n476_5 ), + .I2(\fifo_inst/n476_6 ), + .I3(\fifo_inst/n476_7 ), + .F(\fifo_inst/n473_61 ) +); +defparam \fifo_inst/n473_s43 .INIT=16'h4000; +LUT3 \fifo_inst/Equal.rgraynext_1_s1 ( + .I0(\fifo_inst/rbin_num_next [1]), + .I1(\fifo_inst/rbin_num [2]), + .I2(\fifo_inst/Equal.rgraynext_2_4 ), + .F(\fifo_inst/Equal.rgraynext [1]) +); +defparam \fifo_inst/Equal.rgraynext_1_s1 .INIT=8'h96; +LUT3 \fifo_inst/Equal.rgraynext_9_s2 ( + .I0(\fifo_inst/rbin_num [8]), + .I1(\fifo_inst/rbin_num [6]), + .I2(\fifo_inst/rbin_num [7]), + .F(\fifo_inst/Equal.rgraynext_9_6 ) +); +defparam \fifo_inst/Equal.rgraynext_9_s2 .INIT=8'h80; +LUT4 \fifo_inst/rbin_num_next_8_s4 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/rbin_num [6]), + .I2(\fifo_inst/rbin_num [7]), + .I3(\fifo_inst/rbin_num [8]), + .F(\fifo_inst/rbin_num_next [8]) +); +defparam \fifo_inst/rbin_num_next_8_s4 .INIT=16'h7F80; +LUT3 \fifo_inst/Equal.wgraynext_2_s1 ( + .I0(\fifo_inst/Equal.wbin [2]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wbinnext [3]), + .F(\fifo_inst/Equal.wgraynext [2]) +); +defparam \fifo_inst/Equal.wgraynext_2_s1 .INIT=8'h96; +LUT3 \fifo_inst/Equal.wgraynext_1_s1 ( + .I0(\fifo_inst/Equal.wbinnext [1]), + .I1(\fifo_inst/Equal.wbin [2]), + .I2(\fifo_inst/Equal.wbinnext_2_8 ), + .F(\fifo_inst/Equal.wgraynext [1]) +); +defparam \fifo_inst/Equal.wgraynext_1_s1 .INIT=8'h96; +LUT4 \fifo_inst/Equal.wcount_r_7_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [8]), + .I1(\fifo_inst/Equal.rq2_wptr [7]), + .I2(\fifo_inst/Equal.rq2_wptr [9]), + .I3(\fifo_inst/Equal.wcount_r [10]), + .F(\fifo_inst/Equal.wcount_r [7]) +); +defparam \fifo_inst/Equal.wcount_r_7_s1 .INIT=16'h6996; +LUT3 \fifo_inst/Equal.wcount_r_8_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [8]), + .I1(\fifo_inst/Equal.rq2_wptr [9]), + .I2(\fifo_inst/Equal.wcount_r [10]), + .F(\fifo_inst/Equal.wcount_r [8]) +); +defparam \fifo_inst/Equal.wcount_r_8_s1 .INIT=8'h96; +LUT3 \fifo_inst/Equal.wgraynext_9_s2 ( + .I0(\fifo_inst/Equal.wbin [8]), + .I1(\fifo_inst/Equal.wbin [6]), + .I2(\fifo_inst/Equal.wbin [7]), + .F(\fifo_inst/Equal.wgraynext_9_6 ) +); +defparam \fifo_inst/Equal.wgraynext_9_s2 .INIT=8'h80; +LUT4 \fifo_inst/Equal.wbinnext_8_s4 ( + .I0(\fifo_inst/Equal.wgraynext_6_4 ), + .I1(\fifo_inst/Equal.wbin [6]), + .I2(\fifo_inst/Equal.wbin [7]), + .I3(\fifo_inst/Equal.wbin [8]), + .F(\fifo_inst/Equal.wbinnext [8]) +); +defparam \fifo_inst/Equal.wbinnext_8_s4 .INIT=16'h7F80; +LUT4 \fifo_inst/rbin_num_next_4_s4 ( + .I0(\fifo_inst/rbin_num [4]), + .I1(\fifo_inst/rbin_num [2]), + .I2(\fifo_inst/rbin_num [3]), + .I3(\fifo_inst/Equal.rgraynext_2_4 ), + .F(\fifo_inst/rbin_num_next [4]) +); +defparam \fifo_inst/rbin_num_next_4_s4 .INIT=16'h6AAA; +LUT4 \fifo_inst/Equal.wbinnext_4_s4 ( + .I0(\fifo_inst/Equal.wbin [4]), + .I1(\fifo_inst/Equal.wbin [2]), + .I2(\fifo_inst/Equal.wbin [3]), + .I3(\fifo_inst/Equal.wbinnext_2_8 ), + .F(\fifo_inst/Equal.wbinnext [4]) +); +defparam \fifo_inst/Equal.wbinnext_4_s4 .INIT=16'h6AAA; +LUT4 \fifo_inst/Equal.wcount_r_5_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [5]), + .I1(\fifo_inst/Equal.rq2_wptr [9]), + .I2(\fifo_inst/Equal.wcount_r [10]), + .I3(\fifo_inst/Equal.wcount_r_6_4 ), + .F(\fifo_inst/Equal.wcount_r [5]) +); +defparam \fifo_inst/Equal.wcount_r_5_s1 .INIT=16'h9669; +LUT4 \fifo_inst/Equal.wbinnext_1_s4 ( + .I0(\fifo_inst/Equal.wbin [0]), + .I1(Full), + .I2(WrEn), + .I3(\fifo_inst/Equal.wbin [1]), + .F(\fifo_inst/Equal.wbinnext [1]) +); +defparam \fifo_inst/Equal.wbinnext_1_s4 .INIT=16'hDF20; +LUT3 \fifo_inst/Equal.wbinnext_0_s4 ( + .I0(\fifo_inst/Equal.wbin [0]), + .I1(Full), + .I2(WrEn), + .F(\fifo_inst/Equal.wbinnext_0_9 ) +); +defparam \fifo_inst/Equal.wbinnext_0_s4 .INIT=8'h9A; +LUT4 \fifo_inst/rbin_num_next_1_s4 ( + .I0(\fifo_inst/rbin_num [0]), + .I1(Empty), + .I2(RdEn), + .I3(\fifo_inst/rbin_num [1]), + .F(\fifo_inst/rbin_num_next [1]) +); +defparam \fifo_inst/rbin_num_next_1_s4 .INIT=16'hDF20; +LUT3 \fifo_inst/rbin_num_next_0_s4 ( + .I0(\fifo_inst/rbin_num [0]), + .I1(Empty), + .I2(RdEn), + .F(\fifo_inst/rbin_num_next_0_9 ) +); +defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'h9A; +LUT4 \fifo_inst/rbin_num_next_10_s4 ( + .I0(\fifo_inst/Equal.rgraynext_2_4 ), + .I1(\fifo_inst/Equal.rgraynext_6_5 ), + .I2(\fifo_inst/Equal.rgraynext_10_4 ), + .I3(\fifo_inst/rbin_num [10]), + .F(\fifo_inst/rbin_num_next [10]) +); +defparam \fifo_inst/rbin_num_next_10_s4 .INIT=16'h7F80; +LUT4 \fifo_inst/rbin_num_next_9_s4 ( + .I0(\fifo_inst/Equal.rgraynext_2_4 ), + .I1(\fifo_inst/Equal.rgraynext_6_5 ), + .I2(\fifo_inst/Equal.rgraynext_9_6 ), + .I3(\fifo_inst/rbin_num [9]), + .F(\fifo_inst/rbin_num_next [9]) +); +defparam \fifo_inst/rbin_num_next_9_s4 .INIT=16'h7F80; +LUT4 \fifo_inst/rbin_num_next_7_s4 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/Equal.rgraynext_2_4 ), + .I2(\fifo_inst/Equal.rgraynext_6_5 ), + .I3(\fifo_inst/rbin_num [7]), + .F(\fifo_inst/rbin_num_next [7]) +); +defparam \fifo_inst/rbin_num_next_7_s4 .INIT=16'h7F80; +LUT3 \fifo_inst/rbin_num_next_6_s4 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/Equal.rgraynext_2_4 ), + .I2(\fifo_inst/Equal.rgraynext_6_5 ), + .F(\fifo_inst/rbin_num_next [6]) +); +defparam \fifo_inst/rbin_num_next_6_s4 .INIT=8'h6A; +LUT4 \fifo_inst/Equal.rgraynext_6_s3 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/Equal.rgraynext_2_4 ), + .I2(\fifo_inst/Equal.rgraynext_6_5 ), + .I3(\fifo_inst/rbin_num [7]), + .F(\fifo_inst/Equal.rgraynext [6]) +); +defparam \fifo_inst/Equal.rgraynext_6_s3 .INIT=16'h15EA; +LUT4 \fifo_inst/Equal.wbinnext_10_s4 ( + .I0(\fifo_inst/Equal.wbinnext_2_8 ), + .I1(\fifo_inst/Equal.wgraynext_6_5 ), + .I2(\fifo_inst/Equal.wgraynext_10_4 ), + .I3(\fifo_inst/Equal.wbin [10]), + .F(\fifo_inst/Equal.wbinnext [10]) +); +defparam \fifo_inst/Equal.wbinnext_10_s4 .INIT=16'h7F80; +LUT4 \fifo_inst/Equal.wbinnext_9_s4 ( + .I0(\fifo_inst/Equal.wbinnext_2_8 ), + .I1(\fifo_inst/Equal.wgraynext_6_5 ), + .I2(\fifo_inst/Equal.wgraynext_9_6 ), + .I3(\fifo_inst/Equal.wbin [9]), + .F(\fifo_inst/Equal.wbinnext [9]) +); +defparam \fifo_inst/Equal.wbinnext_9_s4 .INIT=16'h7F80; +LUT4 \fifo_inst/Equal.wbinnext_7_s4 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wgraynext_6_5 ), + .I3(\fifo_inst/Equal.wbin [7]), + .F(\fifo_inst/Equal.wbinnext [7]) +); +defparam \fifo_inst/Equal.wbinnext_7_s4 .INIT=16'h7F80; +LUT3 \fifo_inst/Equal.wbinnext_6_s4 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wgraynext_6_5 ), + .F(\fifo_inst/Equal.wbinnext [6]) +); +defparam \fifo_inst/Equal.wbinnext_6_s4 .INIT=8'h6A; +LUT4 \fifo_inst/Equal.wgraynext_6_s3 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wgraynext_6_5 ), + .I3(\fifo_inst/Equal.wbin [7]), + .F(\fifo_inst/Equal.wgraynext [6]) +); +defparam \fifo_inst/Equal.wgraynext_6_s3 .INIT=16'h15EA; +LUT3 \fifo_inst/rempty_val_s2 ( + .I0(\fifo_inst/wptr [13]), + .I1(\fifo_inst/rptr [13]), + .I2(\fifo_inst/n118_3 ), + .F(\fifo_inst/rempty_val ) +); +defparam \fifo_inst/rempty_val_s2 .INIT=8'h09; +LUT4 \fifo_inst/Equal.wgraynext_0_s1 ( + .I0(\fifo_inst/Equal.wbinnext [1]), + .I1(\fifo_inst/Equal.wbin [0]), + .I2(Full), + .I3(WrEn), + .F(\fifo_inst/Equal.wgraynext [0]) +); +defparam \fifo_inst/Equal.wgraynext_0_s1 .INIT=16'h6966; +LUT4 \fifo_inst/Equal.rgraynext_0_s1 ( + .I0(\fifo_inst/rbin_num_next [1]), + .I1(\fifo_inst/rbin_num [0]), + .I2(Empty), + .I3(RdEn), + .F(\fifo_inst/Equal.rgraynext [0]) +); +defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h6966; +DFF \fifo_inst/rbin_num_12_s0 ( + .D(\fifo_inst/rbin_num_next [12]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [12]) +); +defparam \fifo_inst/rbin_num_12_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_11_s0 ( + .D(\fifo_inst/rbin_num_next [11]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [11]) +); +defparam \fifo_inst/rbin_num_11_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_10_s0 ( + .D(\fifo_inst/rbin_num_next [10]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [10]) +); +defparam \fifo_inst/rbin_num_10_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_9_s0 ( + .D(\fifo_inst/rbin_num_next [9]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [9]) +); +defparam \fifo_inst/rbin_num_9_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_8_s0 ( + .D(\fifo_inst/rbin_num_next [8]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [8]) +); +defparam \fifo_inst/rbin_num_8_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_7_s0 ( + .D(\fifo_inst/rbin_num_next [7]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [7]) +); +defparam \fifo_inst/rbin_num_7_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_6_s0 ( + .D(\fifo_inst/rbin_num_next [6]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [6]) +); +defparam \fifo_inst/rbin_num_6_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_5_s0 ( + .D(\fifo_inst/rbin_num_next [5]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [5]) +); +defparam \fifo_inst/rbin_num_5_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_4_s0 ( + .D(\fifo_inst/rbin_num_next [4]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [4]) +); +defparam \fifo_inst/rbin_num_4_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_3_s0 ( + .D(\fifo_inst/rbin_num_next [3]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [3]) +); +defparam \fifo_inst/rbin_num_3_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_2_s0 ( + .D(\fifo_inst/rbin_num_next [2]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [2]) +); +defparam \fifo_inst/rbin_num_2_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_1_s0 ( + .D(\fifo_inst/rbin_num_next [1]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [1]) +); +defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_0_s0 ( + .D(\fifo_inst/rbin_num_next_0_9 ), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [0]) +); +defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_13_s0 ( + .D(\fifo_inst/wptr [13]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [13]) +); +defparam \fifo_inst/Equal.rq1_wptr_13_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_12_s0 ( + .D(\fifo_inst/wptr [12]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [12]) +); +defparam \fifo_inst/Equal.rq1_wptr_12_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_11_s0 ( + .D(\fifo_inst/wptr [11]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [11]) +); +defparam \fifo_inst/Equal.rq1_wptr_11_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_10_s0 ( + .D(\fifo_inst/wptr [10]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [10]) +); +defparam \fifo_inst/Equal.rq1_wptr_10_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_9_s0 ( + .D(\fifo_inst/wptr [9]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [9]) +); +defparam \fifo_inst/Equal.rq1_wptr_9_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_8_s0 ( + .D(\fifo_inst/wptr [8]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [8]) +); +defparam \fifo_inst/Equal.rq1_wptr_8_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_7_s0 ( + .D(\fifo_inst/wptr [7]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [7]) +); +defparam \fifo_inst/Equal.rq1_wptr_7_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_6_s0 ( + .D(\fifo_inst/wptr [6]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [6]) +); +defparam \fifo_inst/Equal.rq1_wptr_6_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_5_s0 ( + .D(\fifo_inst/wptr [5]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [5]) +); +defparam \fifo_inst/Equal.rq1_wptr_5_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_4_s0 ( + .D(\fifo_inst/wptr [4]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [4]) +); +defparam \fifo_inst/Equal.rq1_wptr_4_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_3_s0 ( + .D(\fifo_inst/wptr [3]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [3]) +); +defparam \fifo_inst/Equal.rq1_wptr_3_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_2_s0 ( + .D(\fifo_inst/wptr [2]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [2]) +); +defparam \fifo_inst/Equal.rq1_wptr_2_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_1_s0 ( + .D(\fifo_inst/wptr [1]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [1]) +); +defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq1_wptr_0_s0 ( + .D(\fifo_inst/wptr [0]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr [0]) +); +defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_13_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [13]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [13]) +); +defparam \fifo_inst/Equal.rq2_wptr_13_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_12_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [12]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [12]) +); +defparam \fifo_inst/Equal.rq2_wptr_12_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_11_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [11]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [11]) +); +defparam \fifo_inst/Equal.rq2_wptr_11_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_10_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [10]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [10]) +); +defparam \fifo_inst/Equal.rq2_wptr_10_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_9_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [9]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [9]) +); +defparam \fifo_inst/Equal.rq2_wptr_9_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_8_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [8]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [8]) +); +defparam \fifo_inst/Equal.rq2_wptr_8_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_7_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [7]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [7]) +); +defparam \fifo_inst/Equal.rq2_wptr_7_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_6_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [6]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [6]) +); +defparam \fifo_inst/Equal.rq2_wptr_6_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_5_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [5]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [5]) +); +defparam \fifo_inst/Equal.rq2_wptr_5_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_4_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [4]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [4]) +); +defparam \fifo_inst/Equal.rq2_wptr_4_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_3_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [3]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [3]) +); +defparam \fifo_inst/Equal.rq2_wptr_3_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_2_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [2]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [2]) +); +defparam \fifo_inst/Equal.rq2_wptr_2_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_1_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [1]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [1]) +); +defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.rq2_wptr_0_s0 ( + .D(\fifo_inst/Equal.rq1_wptr [0]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq2_wptr [0]) +); +defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_13_s0 ( + .D(\fifo_inst/rbin_num_next [13]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [13]) +); +defparam \fifo_inst/rptr_13_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_12_s0 ( + .D(\fifo_inst/Equal.rgraynext [12]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [12]) +); +defparam \fifo_inst/rptr_12_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_11_s0 ( + .D(\fifo_inst/Equal.rgraynext [11]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [11]) +); +defparam \fifo_inst/rptr_11_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_10_s0 ( + .D(\fifo_inst/Equal.rgraynext [10]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [10]) +); +defparam \fifo_inst/rptr_10_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_9_s0 ( + .D(\fifo_inst/Equal.rgraynext [9]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [9]) +); +defparam \fifo_inst/rptr_9_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_8_s0 ( + .D(\fifo_inst/Equal.rgraynext [8]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [8]) +); +defparam \fifo_inst/rptr_8_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_7_s0 ( + .D(\fifo_inst/Equal.rgraynext [7]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [7]) +); +defparam \fifo_inst/rptr_7_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_6_s0 ( + .D(\fifo_inst/Equal.rgraynext [6]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [6]) +); +defparam \fifo_inst/rptr_6_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_5_s0 ( + .D(\fifo_inst/Equal.rgraynext [5]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [5]) +); +defparam \fifo_inst/rptr_5_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_4_s0 ( + .D(\fifo_inst/Equal.rgraynext [4]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [4]) +); +defparam \fifo_inst/rptr_4_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_3_s0 ( + .D(\fifo_inst/Equal.rgraynext [3]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [3]) +); +defparam \fifo_inst/rptr_3_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_2_s0 ( + .D(\fifo_inst/Equal.rgraynext [2]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [2]) +); +defparam \fifo_inst/rptr_2_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_1_s0 ( + .D(\fifo_inst/Equal.rgraynext [1]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [1]) +); +defparam \fifo_inst/rptr_1_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_0_s0 ( + .D(\fifo_inst/Equal.rgraynext [0]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [0]) +); +defparam \fifo_inst/rptr_0_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_13_s0 ( + .D(\fifo_inst/Equal.wbinnext [13]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [13]) +); +defparam \fifo_inst/wptr_13_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_12_s0 ( + .D(\fifo_inst/Equal.wgraynext [12]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [12]) +); +defparam \fifo_inst/wptr_12_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_11_s0 ( + .D(\fifo_inst/Equal.wgraynext [11]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [11]) +); +defparam \fifo_inst/wptr_11_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_10_s0 ( + .D(\fifo_inst/Equal.wgraynext [10]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [10]) +); +defparam \fifo_inst/wptr_10_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_9_s0 ( + .D(\fifo_inst/Equal.wgraynext [9]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [9]) +); +defparam \fifo_inst/wptr_9_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_8_s0 ( + .D(\fifo_inst/Equal.wgraynext [8]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [8]) +); +defparam \fifo_inst/wptr_8_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_7_s0 ( + .D(\fifo_inst/Equal.wgraynext [7]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [7]) +); +defparam \fifo_inst/wptr_7_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_6_s0 ( + .D(\fifo_inst/Equal.wgraynext [6]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [6]) +); +defparam \fifo_inst/wptr_6_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_5_s0 ( + .D(\fifo_inst/Equal.wgraynext [5]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [5]) +); +defparam \fifo_inst/wptr_5_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_4_s0 ( + .D(\fifo_inst/Equal.wgraynext [4]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [4]) +); +defparam \fifo_inst/wptr_4_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_3_s0 ( + .D(\fifo_inst/Equal.wgraynext [3]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [3]) +); +defparam \fifo_inst/wptr_3_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_2_s0 ( + .D(\fifo_inst/Equal.wgraynext [2]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [2]) +); +defparam \fifo_inst/wptr_2_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_1_s0 ( + .D(\fifo_inst/Equal.wgraynext [1]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [1]) +); +defparam \fifo_inst/wptr_1_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_0_s0 ( + .D(\fifo_inst/Equal.wgraynext [0]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [0]) +); +defparam \fifo_inst/wptr_0_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_12_s0 ( + .D(\fifo_inst/Equal.wbinnext [12]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [12]) +); +defparam \fifo_inst/Equal.wbin_12_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_11_s0 ( + .D(\fifo_inst/Equal.wbinnext [11]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [11]) +); +defparam \fifo_inst/Equal.wbin_11_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_10_s0 ( + .D(\fifo_inst/Equal.wbinnext [10]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [10]) +); +defparam \fifo_inst/Equal.wbin_10_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_9_s0 ( + .D(\fifo_inst/Equal.wbinnext [9]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [9]) +); +defparam \fifo_inst/Equal.wbin_9_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_8_s0 ( + .D(\fifo_inst/Equal.wbinnext [8]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [8]) +); +defparam \fifo_inst/Equal.wbin_8_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_7_s0 ( + .D(\fifo_inst/Equal.wbinnext [7]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [7]) +); +defparam \fifo_inst/Equal.wbin_7_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_6_s0 ( + .D(\fifo_inst/Equal.wbinnext [6]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [6]) +); +defparam \fifo_inst/Equal.wbin_6_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_5_s0 ( + .D(\fifo_inst/Equal.wbinnext [5]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [5]) +); +defparam \fifo_inst/Equal.wbin_5_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_4_s0 ( + .D(\fifo_inst/Equal.wbinnext [4]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [4]) +); +defparam \fifo_inst/Equal.wbin_4_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_3_s0 ( + .D(\fifo_inst/Equal.wbinnext [3]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [3]) +); +defparam \fifo_inst/Equal.wbin_3_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_2_s0 ( + .D(\fifo_inst/Equal.wbinnext [2]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [2]) +); +defparam \fifo_inst/Equal.wbin_2_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_1_s0 ( + .D(\fifo_inst/Equal.wbinnext [1]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [1]) +); +defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_0_s0 ( + .D(\fifo_inst/Equal.wbinnext_0_9 ), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [0]) +); +defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_13_s0 ( + .D(\fifo_inst/Equal.rq2_wptr [13]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [13]) +); +defparam \fifo_inst/Equal.wcount_r_d_13_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_12_s0 ( + .D(\fifo_inst/Equal.wcount_r [12]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [12]) +); +defparam \fifo_inst/Equal.wcount_r_d_12_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_11_s0 ( + .D(\fifo_inst/Equal.wcount_r [11]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [11]) +); +defparam \fifo_inst/Equal.wcount_r_d_11_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_10_s0 ( + .D(\fifo_inst/Equal.wcount_r [10]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [10]) +); +defparam \fifo_inst/Equal.wcount_r_d_10_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_9_s0 ( + .D(\fifo_inst/Equal.wcount_r [9]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [9]) +); +defparam \fifo_inst/Equal.wcount_r_d_9_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_8_s0 ( + .D(\fifo_inst/Equal.wcount_r [8]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [8]) +); +defparam \fifo_inst/Equal.wcount_r_d_8_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_7_s0 ( + .D(\fifo_inst/Equal.wcount_r [7]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [7]) +); +defparam \fifo_inst/Equal.wcount_r_d_7_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_6_s0 ( + .D(\fifo_inst/Equal.wcount_r [6]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [6]) +); +defparam \fifo_inst/Equal.wcount_r_d_6_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_5_s0 ( + .D(\fifo_inst/Equal.wcount_r [5]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [5]) +); +defparam \fifo_inst/Equal.wcount_r_d_5_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_4_s0 ( + .D(\fifo_inst/Equal.wcount_r [4]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [4]) +); +defparam \fifo_inst/Equal.wcount_r_d_4_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_3_s0 ( + .D(\fifo_inst/Equal.wcount_r [3]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [3]) +); +defparam \fifo_inst/Equal.wcount_r_d_3_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_2_s0 ( + .D(\fifo_inst/Equal.wcount_r [2]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [2]) +); +defparam \fifo_inst/Equal.wcount_r_d_2_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_1_s0 ( + .D(\fifo_inst/Equal.wcount_r [1]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [1]) +); +defparam \fifo_inst/Equal.wcount_r_d_1_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_0_s0 ( + .D(\fifo_inst/Equal.wcount_r [0]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [0]) +); +defparam \fifo_inst/Equal.wcount_r_d_0_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_13_s0 ( + .D(\fifo_inst/rcnt_sub [13]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [13]) +); +defparam \fifo_inst/rcnt_sub_d_13_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_12_s0 ( + .D(\fifo_inst/rcnt_sub [12]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [12]) +); +defparam \fifo_inst/rcnt_sub_d_12_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_11_s0 ( + .D(\fifo_inst/rcnt_sub [11]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [11]) +); +defparam \fifo_inst/rcnt_sub_d_11_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_10_s0 ( + .D(\fifo_inst/rcnt_sub [10]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [10]) +); +defparam \fifo_inst/rcnt_sub_d_10_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_9_s0 ( + .D(\fifo_inst/rcnt_sub [9]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [9]) +); +defparam \fifo_inst/rcnt_sub_d_9_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_8_s0 ( + .D(\fifo_inst/rcnt_sub [8]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [8]) +); +defparam \fifo_inst/rcnt_sub_d_8_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_7_s0 ( + .D(\fifo_inst/rcnt_sub [7]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [7]) +); +defparam \fifo_inst/rcnt_sub_d_7_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_6_s0 ( + .D(\fifo_inst/rcnt_sub [6]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [6]) +); +defparam \fifo_inst/rcnt_sub_d_6_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_5_s0 ( + .D(\fifo_inst/rcnt_sub [5]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [5]) +); +defparam \fifo_inst/rcnt_sub_d_5_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_4_s0 ( + .D(\fifo_inst/rcnt_sub [4]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [4]) +); +defparam \fifo_inst/rcnt_sub_d_4_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_3_s0 ( + .D(\fifo_inst/rcnt_sub [3]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [3]) +); +defparam \fifo_inst/rcnt_sub_d_3_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_2_s0 ( + .D(\fifo_inst/rcnt_sub [2]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [2]) +); +defparam \fifo_inst/rcnt_sub_d_2_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_1_s0 ( + .D(\fifo_inst/rcnt_sub [1]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [1]) +); +defparam \fifo_inst/rcnt_sub_d_1_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_0_s0 ( + .D(\fifo_inst/rcnt_sub [0]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [0]) +); +defparam \fifo_inst/rcnt_sub_d_0_s0 .INIT=1'b0; +DFFP \fifo_inst/rempty_val1_s0 ( + .D(\fifo_inst/rempty_val ), + .CLK(RdClk), + .PRESET(\fifo_inst/rempty_val ), + .Q(\fifo_inst/rempty_val1 ) +); +defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1; +DFFP \fifo_inst/Empty_s0 ( + .D(\fifo_inst/rempty_val1 ), + .CLK(RdClk), + .PRESET(\fifo_inst/rempty_val ), + .Q(Empty) +); +defparam \fifo_inst/Empty_s0 .INIT=1'b1; +DFFS \fifo_inst/Almost_Empty_s0 ( + .D(\fifo_inst/n476_3 ), + .CLK(RdClk), + .SET(\fifo_inst/n473_61 ), + .Q(Almost_Empty) +); +defparam \fifo_inst/Almost_Empty_s0 .INIT=1'b1; +DFFP \fifo_inst/wfull_val1_s0 ( + .D(\fifo_inst/wfull_val ), + .CLK(WrClk), + .PRESET(\fifo_inst/wfull_val ), + .Q(\fifo_inst/wfull_val1 ) +); +defparam \fifo_inst/wfull_val1_s0 .INIT=1'b1; +DFFP \fifo_inst/Full_s0 ( + .D(\fifo_inst/wfull_val1 ), + .CLK(WrClk), + .PRESET(\fifo_inst/wfull_val ), + .Q(Full) +); +defparam \fifo_inst/Full_s0 .INIT=1'b1; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[1:0]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO [31:2], Q[1:0]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_1_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[3:2]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_0 [31:2], Q[3:2]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_2_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[5:4]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_1 [31:2], Q[5:4]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_3_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[7:6]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_2 [31:2], Q[7:6]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_4_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[9:8]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_3 [31:2], Q[9:8]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_5_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[11:10]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_4 [31:2], Q[11:10]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_6_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[13:12]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_5 [31:2], Q[13:12]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_7_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[15:14]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_6 [31:2], Q[15:14]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .BLK_SEL_1=3'b000; +ALU \fifo_inst/rcnt_sub_0_s ( + .I0(\fifo_inst/Equal.wcount_r_d [0]), + .I1(\fifo_inst/rbin_num [0]), + .I3(GND), + .CIN(VCC), + .COUT(\fifo_inst/rcnt_sub_0_3 ), + .SUM(\fifo_inst/rcnt_sub [0]) +); +defparam \fifo_inst/rcnt_sub_0_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_1_s ( + .I0(\fifo_inst/Equal.wcount_r_d [1]), + .I1(\fifo_inst/rbin_num [1]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_0_3 ), + .COUT(\fifo_inst/rcnt_sub_1_3 ), + .SUM(\fifo_inst/rcnt_sub [1]) +); +defparam \fifo_inst/rcnt_sub_1_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_2_s ( + .I0(\fifo_inst/Equal.wcount_r_d [2]), + .I1(\fifo_inst/rbin_num [2]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_1_3 ), + .COUT(\fifo_inst/rcnt_sub_2_3 ), + .SUM(\fifo_inst/rcnt_sub [2]) +); +defparam \fifo_inst/rcnt_sub_2_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_3_s ( + .I0(\fifo_inst/Equal.wcount_r_d [3]), + .I1(\fifo_inst/rbin_num [3]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_2_3 ), + .COUT(\fifo_inst/rcnt_sub_3_3 ), + .SUM(\fifo_inst/rcnt_sub [3]) +); +defparam \fifo_inst/rcnt_sub_3_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_4_s ( + .I0(\fifo_inst/Equal.wcount_r_d [4]), + .I1(\fifo_inst/rbin_num [4]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_3_3 ), + .COUT(\fifo_inst/rcnt_sub_4_3 ), + .SUM(\fifo_inst/rcnt_sub [4]) +); +defparam \fifo_inst/rcnt_sub_4_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_5_s ( + .I0(\fifo_inst/Equal.wcount_r_d [5]), + .I1(\fifo_inst/rbin_num [5]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_4_3 ), + .COUT(\fifo_inst/rcnt_sub_5_3 ), + .SUM(\fifo_inst/rcnt_sub [5]) +); +defparam \fifo_inst/rcnt_sub_5_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_6_s ( + .I0(\fifo_inst/Equal.wcount_r_d [6]), + .I1(\fifo_inst/rbin_num [6]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_5_3 ), + .COUT(\fifo_inst/rcnt_sub_6_3 ), + .SUM(\fifo_inst/rcnt_sub [6]) +); +defparam \fifo_inst/rcnt_sub_6_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_7_s ( + .I0(\fifo_inst/Equal.wcount_r_d [7]), + .I1(\fifo_inst/rbin_num [7]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_6_3 ), + .COUT(\fifo_inst/rcnt_sub_7_3 ), + .SUM(\fifo_inst/rcnt_sub [7]) +); +defparam \fifo_inst/rcnt_sub_7_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_8_s ( + .I0(\fifo_inst/Equal.wcount_r_d [8]), + .I1(\fifo_inst/rbin_num [8]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_7_3 ), + .COUT(\fifo_inst/rcnt_sub_8_3 ), + .SUM(\fifo_inst/rcnt_sub [8]) +); +defparam \fifo_inst/rcnt_sub_8_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_9_s ( + .I0(\fifo_inst/Equal.wcount_r_d [9]), + .I1(\fifo_inst/rbin_num [9]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_8_3 ), + .COUT(\fifo_inst/rcnt_sub_9_3 ), + .SUM(\fifo_inst/rcnt_sub [9]) +); +defparam \fifo_inst/rcnt_sub_9_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_10_s ( + .I0(\fifo_inst/Equal.wcount_r_d [10]), + .I1(\fifo_inst/rbin_num [10]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_9_3 ), + .COUT(\fifo_inst/rcnt_sub_10_3 ), + .SUM(\fifo_inst/rcnt_sub [10]) +); +defparam \fifo_inst/rcnt_sub_10_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_11_s ( + .I0(\fifo_inst/Equal.wcount_r_d [11]), + .I1(\fifo_inst/rbin_num [11]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_10_3 ), + .COUT(\fifo_inst/rcnt_sub_11_3 ), + .SUM(\fifo_inst/rcnt_sub [11]) +); +defparam \fifo_inst/rcnt_sub_11_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_12_s ( + .I0(\fifo_inst/Equal.wcount_r_d [12]), + .I1(\fifo_inst/rbin_num [12]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_11_3 ), + .COUT(\fifo_inst/rcnt_sub_12_3 ), + .SUM(\fifo_inst/rcnt_sub [12]) +); +defparam \fifo_inst/rcnt_sub_12_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_13_s ( + .I0(\fifo_inst/n166_3 ), + .I1(GND), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_12_3 ), + .COUT(\fifo_inst/rcnt_sub_13_0_COUT ), + .SUM(\fifo_inst/rcnt_sub [13]) +); +defparam \fifo_inst/rcnt_sub_13_s .ALU_MODE=1; +ALU \fifo_inst/n106_s0 ( + .I0(\fifo_inst/wptr [0]), + .I1(\fifo_inst/rptr [0]), + .I3(GND), + .CIN(GND), + .COUT(\fifo_inst/n106_3 ), + .SUM(\fifo_inst/n106_1_SUM ) +); +defparam \fifo_inst/n106_s0 .ALU_MODE=3; +ALU \fifo_inst/n107_s0 ( + .I0(\fifo_inst/wptr [1]), + .I1(\fifo_inst/rptr [1]), + .I3(GND), + .CIN(\fifo_inst/n106_3 ), + .COUT(\fifo_inst/n107_3 ), + .SUM(\fifo_inst/n107_1_SUM ) +); +defparam \fifo_inst/n107_s0 .ALU_MODE=3; +ALU \fifo_inst/n108_s0 ( + .I0(\fifo_inst/wptr [2]), + .I1(\fifo_inst/rptr [2]), + .I3(GND), + .CIN(\fifo_inst/n107_3 ), + .COUT(\fifo_inst/n108_3 ), + .SUM(\fifo_inst/n108_1_SUM ) +); +defparam \fifo_inst/n108_s0 .ALU_MODE=3; +ALU \fifo_inst/n109_s0 ( + .I0(\fifo_inst/wptr [3]), + .I1(\fifo_inst/rptr [3]), + .I3(GND), + .CIN(\fifo_inst/n108_3 ), + .COUT(\fifo_inst/n109_3 ), + .SUM(\fifo_inst/n109_1_SUM ) +); +defparam \fifo_inst/n109_s0 .ALU_MODE=3; +ALU \fifo_inst/n110_s0 ( + .I0(\fifo_inst/wptr [4]), + .I1(\fifo_inst/rptr [4]), + .I3(GND), + .CIN(\fifo_inst/n109_3 ), + .COUT(\fifo_inst/n110_3 ), + .SUM(\fifo_inst/n110_1_SUM ) +); +defparam \fifo_inst/n110_s0 .ALU_MODE=3; +ALU \fifo_inst/n111_s0 ( + .I0(\fifo_inst/wptr [5]), + .I1(\fifo_inst/rptr [5]), + .I3(GND), + .CIN(\fifo_inst/n110_3 ), + .COUT(\fifo_inst/n111_3 ), + .SUM(\fifo_inst/n111_1_SUM ) +); +defparam \fifo_inst/n111_s0 .ALU_MODE=3; +ALU \fifo_inst/n112_s0 ( + .I0(\fifo_inst/wptr [6]), + .I1(\fifo_inst/rptr [6]), + .I3(GND), + .CIN(\fifo_inst/n111_3 ), + .COUT(\fifo_inst/n112_3 ), + .SUM(\fifo_inst/n112_1_SUM ) +); +defparam \fifo_inst/n112_s0 .ALU_MODE=3; +ALU \fifo_inst/n113_s0 ( + .I0(\fifo_inst/wptr [7]), + .I1(\fifo_inst/rptr [7]), + .I3(GND), + .CIN(\fifo_inst/n112_3 ), + .COUT(\fifo_inst/n113_3 ), + .SUM(\fifo_inst/n113_1_SUM ) +); +defparam \fifo_inst/n113_s0 .ALU_MODE=3; +ALU \fifo_inst/n114_s0 ( + .I0(\fifo_inst/wptr [8]), + .I1(\fifo_inst/rptr [8]), + .I3(GND), + .CIN(\fifo_inst/n113_3 ), + .COUT(\fifo_inst/n114_3 ), + .SUM(\fifo_inst/n114_1_SUM ) +); +defparam \fifo_inst/n114_s0 .ALU_MODE=3; +ALU \fifo_inst/n115_s0 ( + .I0(\fifo_inst/wptr [9]), + .I1(\fifo_inst/rptr [9]), + .I3(GND), + .CIN(\fifo_inst/n114_3 ), + .COUT(\fifo_inst/n115_3 ), + .SUM(\fifo_inst/n115_1_SUM ) +); +defparam \fifo_inst/n115_s0 .ALU_MODE=3; +ALU \fifo_inst/n116_s0 ( + .I0(\fifo_inst/wptr [10]), + .I1(\fifo_inst/rptr [10]), + .I3(GND), + .CIN(\fifo_inst/n115_3 ), + .COUT(\fifo_inst/n116_3 ), + .SUM(\fifo_inst/n116_1_SUM ) +); +defparam \fifo_inst/n116_s0 .ALU_MODE=3; +ALU \fifo_inst/n117_s0 ( + .I0(\fifo_inst/wptr [11]), + .I1(\fifo_inst/rptr [11]), + .I3(GND), + .CIN(\fifo_inst/n116_3 ), + .COUT(\fifo_inst/n117_3 ), + .SUM(\fifo_inst/n117_1_SUM ) +); +defparam \fifo_inst/n117_s0 .ALU_MODE=3; +ALU \fifo_inst/n118_s0 ( + .I0(\fifo_inst/wptr [12]), + .I1(\fifo_inst/rptr [12]), + .I3(GND), + .CIN(\fifo_inst/n117_3 ), + .COUT(\fifo_inst/n118_3 ), + .SUM(\fifo_inst/n118_1_SUM ) +); +defparam \fifo_inst/n118_s0 .ALU_MODE=3; +endmodule diff --git a/hsdaoh_nano4k_test/hsdaoh_nano4k_test.cst b/hsdaoh_nano4k_test/hsdaoh_nano4k_test.cst new file mode 100644 index 0000000..2ff0c44 --- /dev/null +++ b/hsdaoh_nano4k_test/hsdaoh_nano4k_test.cst @@ -0,0 +1,12 @@ +IO_LOC "sys_resetn" 14; +IO_PORT "sys_resetn" PULL_MODE=UP; +IO_LOC "sys_clk" 45; +IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP; +IO_LOC "tmds_d_p[0]" 30,29; +IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=4; +IO_LOC "tmds_d_p[1]" 32,31; +IO_PORT "tmds_d_p[1]" PULL_MODE=NONE DRIVE=4; +IO_LOC "tmds_d_p[2]" 35,34; +IO_PORT "tmds_d_p[2]" PULL_MODE=NONE DRIVE=4; +IO_LOC "tmds_clk_p" 28,27; +IO_PORT "tmds_clk_p" PULL_MODE=NONE DRIVE=4; \ No newline at end of file diff --git a/hsdaoh_nano4k_test/hsdaoh_nano4k_test.sdc b/hsdaoh_nano4k_test/hsdaoh_nano4k_test.sdc new file mode 100644 index 0000000..b4e6de1 --- /dev/null +++ b/hsdaoh_nano4k_test/hsdaoh_nano4k_test.sdc @@ -0,0 +1 @@ +create_clock -name sys_clk -period 37.04 [get_ports {sys_clk}] -add diff --git a/hsdaoh_nano4k_test/top.v b/hsdaoh_nano4k_test/top.v new file mode 100644 index 0000000..72d086c --- /dev/null +++ b/hsdaoh_nano4k_test/top.v @@ -0,0 +1,176 @@ +// hsdaoh - High Speed Data Acquisition over HDMI +// Test top design for Tang Nano 4K +// Copyright (C) 2024 by Steve Markgraf +// License: MIT + +module top ( + sys_clk, + sys_resetn, + tmds_clk_n, + tmds_clk_p, + tmds_d_n, + tmds_d_p +); + input sys_clk; + input sys_resetn; + output wire tmds_clk_n; + output wire tmds_clk_p; + output wire [2:0] tmds_d_n; + output wire [2:0] tmds_d_p; + + wire [2:0] tmds; + wire clk_pixel; + wire clk_pixel_x5; + wire hdmi_pll_lock; + + wire clk_data; + wire data_pll_lock; + + // https://juj.github.io/gowin_fpga_code_generators/pll_calculator.html + // 345.6 MHz, maximum that works with my nano 4K + // 345.6/5 = 69.12 MHz + localparam HDMI_PLL_IDIV = 4; + localparam HDMI_PLL_FBDIV = 63; + localparam HDMI_PLL_ODIV = 2; + + wire rst; + assign rst = ~sys_resetn; + + // PLL for HDMI clock + PLLVR #( + .FCLKIN (27), + .IDIV_SEL (HDMI_PLL_IDIV), + .FBDIV_SEL (HDMI_PLL_FBDIV), + .ODIV_SEL (HDMI_PLL_ODIV), + .DEVICE ("GW1NSR-4C") + ) hdmi_pll ( + .CLKIN(sys_clk), + .CLKFB(1'b0), + .RESET(rst), + .RESET_P(1'b0), + .FBDSEL(6'b0), + .IDSEL(6'b0), + .ODSEL(6'b0), + .DUTYDA(4'b0), + .PSDA(4'b0), + .FDLY(4'b0), + .CLKOUT(clk_pixel_x5), + .LOCK(hdmi_pll_lock), + .CLKOUTP(), + .CLKOUTD(), + .CLKOUTD3(), + .VREN(1'b1) + ); + + CLKDIV #( + .DIV_MODE(5), + .GSREN("false") + ) div_5 ( + .CLKOUT(clk_pixel), + .HCLKIN(clk_pixel_x5), + .RESETN(hdmi_pll_lock), + .CALIB(1'b0) + ); + + // 59.4 MHz (4/10/16) data clock (with proprietary, encrypted FIFO) + localparam DATA_PLL_IDIV = 4; + localparam DATA_PLL_FBDIV = 10; + localparam DATA_PLL_ODIV = 16; + + // PLL for data clock + PLLVR #( + .FCLKIN (27), + .IDIV_SEL (DATA_PLL_IDIV), + .FBDIV_SEL (DATA_PLL_FBDIV), + .ODIV_SEL (DATA_PLL_ODIV), + .DEVICE ("GW1NSR-4C") + ) data_pll ( + .CLKIN (sys_clk), + .CLKFB (1'b0), + .RESET (rst), + .RESET_P (1'b0), + .FBDSEL (6'b0), + .IDSEL (6'b0), + .ODSEL (6'b0), + .DUTYDA (4'b0), + .PSDA (4'b0), + .FDLY (4'b0), + .CLKOUT (clk_data), + .LOCK (data_pll_lock), + .CLKOUTP (), + .CLKOUTD (), + .CLKOUTD3 (), + .VREN (1'b1) + ); + + reg [15:0] counter = 16'h0000; + + reg [15:0] fifo_in; + + wire write_enable; + + wire [15:0] fifo_out; + wire fifo_empty; + wire fifo_aempty; + wire Full_o; + + wire FifoHalfFull; + wire FifoFull; + + wire fifo_rd_en_i; +/* + async_fifo #( + .DSIZE(16), + .ASIZE($clog2(8192*2)), // 3 + (1982 * 4) = 7931 => at least 8K entries to buffer 4 lines during VSYNC + .FALLTHROUGH("FALSE") + ) fifo ( + .wclk(clk_data), + .wrst_n(hdmi_pll_lock), + .winc(write_enable), + .wdata(fifo_in), + .wfull(FifoFull), + .awfull(FifoHalfFull), //fixme + .rclk(clk_pixel), + .rrst_n(hdmi_pll_lock), + .rinc(fifo_rd_en_i), + .rdata(fifo_out), + .rempty(fifo_empty), + .arempty(fifo_aempty) + ); +*/ + + FIFO_HS_Top fifo( + .Data(fifo_in), //input [0:0] Data + .WrClk(clk_data), //input WrClk + .RdClk(clk_pixel), //input RdClk + .WrEn(write_enable), //input WrEn + .RdEn(fifo_rd_en_i), //input RdEn + .Almost_Empty(fifo_aempty), //output Almost_Empty + .Q(fifo_out), //output [0:0] Q + .Empty(fifo_empty), //output Empty + .Full(FifoFull) //output Full + ); + + + hsdaoh_core hsdaoh ( + .rstn(hdmi_pll_lock), + .tmds_clk_n(tmds_clk_n), + .tmds_clk_p(tmds_clk_p), + .tmds_d_n(tmds_d_n), + .tmds_d_p(tmds_d_p), + .clk_pixel_x5(clk_pixel_x5), + .clk_pixel(clk_pixel), + .fifo_empty(fifo_empty), + .fifo_aempty(fifo_aempty), + .fifo_read_en(fifo_rd_en_i), + .data_in(fifo_out) + ); + + assign write_enable = 1'b1; + + always @(posedge clk_data) begin + fifo_in <= counter[15:0]; + counter <= counter + 1'b1; + end + +endmodule diff --git a/hsdaoh_nano9k_test.gprj b/hsdaoh_nano9k_test.gprj new file mode 100644 index 0000000..938867a --- /dev/null +++ b/hsdaoh_nano9k_test.gprj @@ -0,0 +1,26 @@ + + + + + 5 + gw1nr9c-004 + + + + + + + + + + + + + + + + + + + + diff --git a/hsdaoh_nano9k_test/fifo_hs/fifo_hs.ipc b/hsdaoh_nano9k_test/fifo_hs/fifo_hs.ipc new file mode 100644 index 0000000..a65eb0c --- /dev/null +++ b/hsdaoh_nano9k_test/fifo_hs/fifo_hs.ipc @@ -0,0 +1,35 @@ +[General] +ipc_version=4 +file=fifo_hs +module=FIFO_HS_Top +target_device=gw1nr9c-004 +type=fifo_hs +version=1.0 + +[Config] +AlmostEmptyFlag=true +AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter +AlmostFullFlag=false +AlmostFullFlagItem=Full_Single Threshold Constant Parameter +BSRAM=true +ControlledByRdEn=false +ECCSelected=false +EmptyClear=1 +EmptySet=1 +EnReset=false +FirstWordFallThrough=false +FullClear=1 +FullSet=1 +LANG=0 +OutputRegistersSelected=false +REG=false +ReadDataNum=false +ReadDataWidth=16 +ReadDepth=8192 +ResetSynchronization=false +SSRAM=false +StandardFIFO=true +Synthesis_tool=GowinSynthesis +WriteDataNum=false +WriteDataWidth=16 +WriteDepth=8192 diff --git a/hsdaoh_nano9k_test/fifo_hs/fifo_hs.v b/hsdaoh_nano9k_test/fifo_hs/fifo_hs.v new file mode 100644 index 0000000..5a16676 --- /dev/null +++ b/hsdaoh_nano9k_test/fifo_hs/fifo_hs.v @@ -0,0 +1,811 @@ +// +//Written by GowinSynthesis +//Product Version "V1.9.9 Beta-4 Education" +//Tue Apr 30 01:00:04 2024 + +//Source file index table: +//file0 "\/home/miracle/Downloads/Gowin_V1.9.9Beta-4_Education/IDE/ipcore/FIFO_HS/data/fifo_hs.v" +//file1 "\/home/miracle/Downloads/Gowin_V1.9.9Beta-4_Education/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" +`pragma protect begin_protected +`pragma protect version="2.3" +`pragma protect author="default" +`pragma protect author_info="default" +`pragma protect encrypt_agent="GOWIN" +`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3" + +`pragma protect encoding=(enctype="base64", line_length=76, bytes=256) +`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa" +`pragma protect key_block +cFD6mgVY1usg3+48x9owyCEr+bdaJ29++StKKKabGFKo4aHUuJA3v9bgkwKAsDNUzhGfEEBDqjav +0sIOyrvvg5a9bc1Au6EWitkoSHP477PR2uwW3+Nqofiw9de9t4V3CZUOjGpf7i0h6U+2idzYnr2p +wu2lcZ1yLsYPtI3SZf+/8B8QTApNO+GKJhhUaKzqoxQmvycd8zu2mNnlTrgQynv+VcjDr7NuIgPy +CXYlOjz7YYND/4VvllKEqzYC+cOZF1/QLn/IBZWo88COe2r1HnWc4TvBUNA8Pmctj7AY/55YPKbX +CIE40q7O2knfx5yGqXnQsl1AJdeAMJs41TBAhQ== + +`pragma protect encoding=(enctype="base64", line_length=76, bytes=44512) +`pragma protect data_keyowner="default-ip-vendor" +`pragma protect data_keyname="default-ip-key" +`pragma protect data_method="aes128-cfb" +`pragma protect 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+Q87CqoXbKG604xBIbFwWhII38CKV7/4du35aPADUWq9JFKihebUq235BuKSVkExNp9l6MQ== +`pragma protect end_protected diff --git a/hsdaoh_nano9k_test/fifo_hs/fifo_hs.vo b/hsdaoh_nano9k_test/fifo_hs/fifo_hs.vo new file mode 100644 index 0000000..e8c9018 --- /dev/null +++ b/hsdaoh_nano9k_test/fifo_hs/fifo_hs.vo @@ -0,0 +1,1967 @@ +//Copyright (C)2014-2023 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: Post-PnR Simulation Model file +//GOWIN Version: V1.9.9 Beta-4 Education +//Created Time: Tue Apr 30 01:00:04 2024 + +`timescale 100 ps/100 ps +module FIFO_HS_Top( + Data, + WrClk, + RdClk, + WrEn, + RdEn, + Almost_Empty, + Q, + Empty, + Full +); +input [15:0] Data; +input WrClk; +input RdClk; +input WrEn; +input RdEn; +output Almost_Empty; +output [15:0] Q; +output Empty; +output Full; +wire Almost_Empty; +wire [15:0] Data; +wire Empty; +wire Full; +wire GND; +wire [15:0] Q; +wire RdClk; +wire RdEn; +wire VCC; +wire WrClk; +wire WrEn; +wire \fifo_inst/n24_5 ; +wire \fifo_inst/n28_3 ; +wire \fifo_inst/n166_3 ; +wire \fifo_inst/wfull_val ; +wire \fifo_inst/n476_3 ; +wire \fifo_inst/Equal.rgraynext_3_4 ; +wire \fifo_inst/Equal.rgraynext_6_4 ; +wire \fifo_inst/Equal.rgraynext_8_4 ; +wire \fifo_inst/Equal.rgraynext_10_4 ; +wire \fifo_inst/Equal.rgraynext_11_4 ; +wire \fifo_inst/Equal.rgraynext_12_4 ; +wire \fifo_inst/Equal.wcount_r_6_4 ; +wire \fifo_inst/Equal.wcount_r_2_4 ; +wire \fifo_inst/Equal.wcount_r_1_4 ; +wire \fifo_inst/Equal.wgraynext_3_4 ; +wire \fifo_inst/Equal.wgraynext_6_4 ; +wire \fifo_inst/Equal.wgraynext_8_4 ; +wire \fifo_inst/Equal.wgraynext_9_4 ; +wire \fifo_inst/Equal.wgraynext_10_4 ; +wire \fifo_inst/Equal.wgraynext_11_4 ; +wire \fifo_inst/Equal.wgraynext_12_4 ; +wire \fifo_inst/wfull_val_4 ; +wire \fifo_inst/wfull_val_5 ; +wire \fifo_inst/wfull_val_6 ; +wire \fifo_inst/wfull_val_7 ; +wire \fifo_inst/n476_4 ; +wire \fifo_inst/rbin_num_next_2_8 ; +wire \fifo_inst/Equal.wbinnext_2_8 ; +wire \fifo_inst/Equal.rgraynext_6_5 ; +wire \fifo_inst/Equal.rgraynext_12_5 ; +wire \fifo_inst/Equal.wgraynext_6_5 ; +wire \fifo_inst/Equal.wgraynext_9_5 ; +wire \fifo_inst/Equal.wgraynext_10_5 ; +wire \fifo_inst/Equal.wgraynext_11_5 ; +wire \fifo_inst/Equal.wgraynext_12_5 ; +wire \fifo_inst/wfull_val_8 ; +wire \fifo_inst/wfull_val_9 ; +wire \fifo_inst/wfull_val_10 ; +wire \fifo_inst/wfull_val_11 ; +wire \fifo_inst/n476_5 ; +wire \fifo_inst/n476_6 ; +wire \fifo_inst/n476_7 ; +wire \fifo_inst/n473_61 ; +wire \fifo_inst/Equal.rgraynext_9_6 ; +wire \fifo_inst/Equal.wbinnext_0_9 ; +wire \fifo_inst/rbin_num_next_0_9 ; +wire \fifo_inst/rempty_val ; +wire \fifo_inst/rempty_val1 ; +wire \fifo_inst/wfull_val1 ; +wire \fifo_inst/Equal.rq1_wptr_0_5 ; +wire \fifo_inst/rcnt_sub_0_3 ; +wire \fifo_inst/rcnt_sub_1_3 ; +wire \fifo_inst/rcnt_sub_2_3 ; +wire \fifo_inst/rcnt_sub_3_3 ; +wire \fifo_inst/rcnt_sub_4_3 ; +wire \fifo_inst/rcnt_sub_5_3 ; +wire \fifo_inst/rcnt_sub_6_3 ; +wire \fifo_inst/rcnt_sub_7_3 ; +wire \fifo_inst/rcnt_sub_8_3 ; +wire \fifo_inst/rcnt_sub_9_3 ; +wire \fifo_inst/rcnt_sub_10_3 ; +wire \fifo_inst/rcnt_sub_11_3 ; +wire \fifo_inst/rcnt_sub_12_3 ; +wire \fifo_inst/rcnt_sub_13_0_COUT ; +wire \fifo_inst/n106_1_SUM ; +wire \fifo_inst/n106_3 ; +wire \fifo_inst/n107_1_SUM ; +wire \fifo_inst/n107_3 ; +wire \fifo_inst/n108_1_SUM ; +wire \fifo_inst/n108_3 ; +wire \fifo_inst/n109_1_SUM ; +wire \fifo_inst/n109_3 ; +wire \fifo_inst/n110_1_SUM ; +wire \fifo_inst/n110_3 ; +wire \fifo_inst/n111_1_SUM ; +wire \fifo_inst/n111_3 ; +wire \fifo_inst/n112_1_SUM ; +wire \fifo_inst/n112_3 ; +wire \fifo_inst/n113_1_SUM ; +wire \fifo_inst/n113_3 ; +wire \fifo_inst/n114_1_SUM ; +wire \fifo_inst/n114_3 ; +wire \fifo_inst/n115_1_SUM ; +wire \fifo_inst/n115_3 ; +wire \fifo_inst/n116_1_SUM ; +wire \fifo_inst/n116_3 ; +wire \fifo_inst/n117_1_SUM ; +wire \fifo_inst/n117_3 ; +wire \fifo_inst/n118_1_SUM ; +wire \fifo_inst/n118_3 ; +wire \fifo_inst/Equal.rq1_wptr_0_20 ; +wire [12:0] \fifo_inst/Equal.rgraynext ; +wire [12:0] \fifo_inst/Equal.wcount_r ; +wire [12:0] \fifo_inst/Equal.wgraynext ; +wire [13:1] \fifo_inst/rbin_num_next ; +wire [13:1] \fifo_inst/Equal.wbinnext ; +wire [12:0] \fifo_inst/rbin_num ; +wire [13:0] \fifo_inst/rptr ; +wire [13:0] \fifo_inst/wptr ; +wire [12:0] \fifo_inst/Equal.wbin ; +wire [13:0] \fifo_inst/Equal.wcount_r_d ; +wire [13:0] \fifo_inst/rcnt_sub_d ; +wire [13:0] \fifo_inst/Equal.rq2_wptr ; +wire [13:0] \fifo_inst/rcnt_sub ; +wire [31:2] \fifo_inst/DO ; +wire [31:2] \fifo_inst/DO_0 ; +wire [31:2] \fifo_inst/DO_1 ; +wire [31:2] \fifo_inst/DO_2 ; +wire [31:2] \fifo_inst/DO_3 ; +wire [31:2] \fifo_inst/DO_4 ; +wire [31:2] \fifo_inst/DO_5 ; +wire [31:2] \fifo_inst/DO_6 ; +wire [3:2] \fifo_inst/DO_7 ; +VCC VCC_cZ ( + .V(VCC) +); +GND GND_cZ ( + .G(GND) +); +GSR GSR ( + .GSRI(VCC) +); +LUT2 \fifo_inst/n24_s1 ( + .I0(Full), + .I1(WrEn), + .F(\fifo_inst/n24_5 ) +); +defparam \fifo_inst/n24_s1 .INIT=4'h4; +LUT2 \fifo_inst/n28_s0 ( + .I0(Empty), + .I1(RdEn), + .F(\fifo_inst/n28_3 ) +); +defparam \fifo_inst/n28_s0 .INIT=4'h4; +LUT3 \fifo_inst/Equal.rgraynext_3_s0 ( + .I0(\fifo_inst/rbin_num [4]), + .I1(\fifo_inst/rbin_num_next [3]), + .I2(\fifo_inst/Equal.rgraynext_3_4 ), + .F(\fifo_inst/Equal.rgraynext [3]) +); +defparam \fifo_inst/Equal.rgraynext_3_s0 .INIT=8'h96; +LUT3 \fifo_inst/Equal.rgraynext_4_s0 ( + .I0(\fifo_inst/rbin_num [4]), + .I1(\fifo_inst/Equal.rgraynext_3_4 ), + .I2(\fifo_inst/rbin_num [5]), + .F(\fifo_inst/Equal.rgraynext [4]) +); +defparam \fifo_inst/Equal.rgraynext_4_s0 .INIT=8'h1E; +LUT4 \fifo_inst/Equal.rgraynext_5_s0 ( + .I0(\fifo_inst/rbin_num [4]), + .I1(\fifo_inst/Equal.rgraynext_3_4 ), + .I2(\fifo_inst/rbin_num [5]), + .I3(\fifo_inst/rbin_num [6]), + .F(\fifo_inst/Equal.rgraynext [5]) +); +defparam \fifo_inst/Equal.rgraynext_5_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.rgraynext_7_s0 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/Equal.rgraynext_6_4 ), + .I2(\fifo_inst/rbin_num [7]), + .I3(\fifo_inst/rbin_num [8]), + .F(\fifo_inst/Equal.rgraynext [7]) +); +defparam \fifo_inst/Equal.rgraynext_7_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.rgraynext_8_s0 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/Equal.rgraynext_8_4 ), + .I2(\fifo_inst/rbin_num [8]), + .I3(\fifo_inst/rbin_num [9]), + .F(\fifo_inst/Equal.rgraynext [8]) +); +defparam \fifo_inst/Equal.rgraynext_8_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.rgraynext_9_s0 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/Equal.rgraynext_9_6 ), + .I2(\fifo_inst/rbin_num [9]), + .I3(\fifo_inst/rbin_num [10]), + .F(\fifo_inst/Equal.rgraynext [9]) +); +defparam \fifo_inst/Equal.rgraynext_9_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.rgraynext_10_s0 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/Equal.rgraynext_10_4 ), + .I2(\fifo_inst/rbin_num [10]), + .I3(\fifo_inst/rbin_num [11]), + .F(\fifo_inst/Equal.rgraynext [10]) +); +defparam \fifo_inst/Equal.rgraynext_10_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.rgraynext_11_s0 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/Equal.rgraynext_11_4 ), + .I2(\fifo_inst/rbin_num [11]), + .I3(\fifo_inst/rbin_num [12]), + .F(\fifo_inst/Equal.rgraynext [11]) +); +defparam \fifo_inst/Equal.rgraynext_11_s0 .INIT=16'h07F8; +LUT3 \fifo_inst/Equal.rgraynext_12_s0 ( + .I0(\fifo_inst/rbin_num [12]), + .I1(\fifo_inst/Equal.rgraynext_12_4 ), + .I2(\fifo_inst/rptr [13]), + .F(\fifo_inst/Equal.rgraynext [12]) +); +defparam \fifo_inst/Equal.rgraynext_12_s0 .INIT=8'h1E; +LUT2 \fifo_inst/Equal.wcount_r_12_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [13]), + .I1(\fifo_inst/Equal.rq2_wptr [12]), + .F(\fifo_inst/Equal.wcount_r [12]) +); +defparam \fifo_inst/Equal.wcount_r_12_s0 .INIT=4'h6; +LUT4 \fifo_inst/Equal.wcount_r_10_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [13]), + .I1(\fifo_inst/Equal.rq2_wptr [12]), + .I2(\fifo_inst/Equal.rq2_wptr [11]), + .I3(\fifo_inst/Equal.rq2_wptr [10]), + .F(\fifo_inst/Equal.wcount_r [10]) +); +defparam \fifo_inst/Equal.wcount_r_10_s0 .INIT=16'h6996; +LUT2 \fifo_inst/Equal.wcount_r_9_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [9]), + .I1(\fifo_inst/Equal.wcount_r [10]), + .F(\fifo_inst/Equal.wcount_r [9]) +); +defparam \fifo_inst/Equal.wcount_r_9_s0 .INIT=4'h6; +LUT2 \fifo_inst/Equal.wcount_r_6_s0 ( + .I0(\fifo_inst/Equal.wcount_r [10]), + .I1(\fifo_inst/Equal.wcount_r_6_4 ), + .F(\fifo_inst/Equal.wcount_r [6]) +); +defparam \fifo_inst/Equal.wcount_r_6_s0 .INIT=4'h6; +LUT3 \fifo_inst/Equal.wcount_r_5_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [5]), + .I1(\fifo_inst/Equal.wcount_r [10]), + .I2(\fifo_inst/Equal.wcount_r_6_4 ), + .F(\fifo_inst/Equal.wcount_r [5]) +); +defparam \fifo_inst/Equal.wcount_r_5_s0 .INIT=8'h96; +LUT3 \fifo_inst/Equal.wcount_r_3_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [4]), + .I1(\fifo_inst/Equal.rq2_wptr [3]), + .I2(\fifo_inst/Equal.wcount_r [5]), + .F(\fifo_inst/Equal.wcount_r [3]) +); +defparam \fifo_inst/Equal.wcount_r_3_s0 .INIT=8'h96; +LUT4 \fifo_inst/Equal.wcount_r_1_s0 ( + .I0(\fifo_inst/Equal.wcount_r [10]), + .I1(\fifo_inst/Equal.wcount_r_6_4 ), + .I2(\fifo_inst/Equal.wcount_r_2_4 ), + .I3(\fifo_inst/Equal.wcount_r_1_4 ), + .F(\fifo_inst/Equal.wcount_r [1]) +); +defparam \fifo_inst/Equal.wcount_r_1_s0 .INIT=16'h9669; +LUT2 \fifo_inst/Equal.wcount_r_0_s0 ( + .I0(\fifo_inst/Equal.rq2_wptr [0]), + .I1(\fifo_inst/Equal.wcount_r [1]), + .F(\fifo_inst/Equal.wcount_r [0]) +); +defparam \fifo_inst/Equal.wcount_r_0_s0 .INIT=4'h6; +LUT2 \fifo_inst/n166_s0 ( + .I0(\fifo_inst/rptr [13]), + .I1(\fifo_inst/Equal.wcount_r_d [13]), + .F(\fifo_inst/n166_3 ) +); +defparam \fifo_inst/n166_s0 .INIT=4'h6; +LUT3 \fifo_inst/Equal.wgraynext_3_s0 ( + .I0(\fifo_inst/Equal.wbin [4]), + .I1(\fifo_inst/Equal.wbinnext [3]), + .I2(\fifo_inst/Equal.wgraynext_3_4 ), + .F(\fifo_inst/Equal.wgraynext [3]) +); +defparam \fifo_inst/Equal.wgraynext_3_s0 .INIT=8'h96; +LUT3 \fifo_inst/Equal.wgraynext_4_s0 ( + .I0(\fifo_inst/Equal.wbin [4]), + .I1(\fifo_inst/Equal.wgraynext_3_4 ), + .I2(\fifo_inst/Equal.wbin [5]), + .F(\fifo_inst/Equal.wgraynext [4]) +); +defparam \fifo_inst/Equal.wgraynext_4_s0 .INIT=8'h1E; +LUT4 \fifo_inst/Equal.wgraynext_5_s0 ( + .I0(\fifo_inst/Equal.wbin [4]), + .I1(\fifo_inst/Equal.wgraynext_3_4 ), + .I2(\fifo_inst/Equal.wbin [5]), + .I3(\fifo_inst/Equal.wbin [6]), + .F(\fifo_inst/Equal.wgraynext [5]) +); +defparam \fifo_inst/Equal.wgraynext_5_s0 .INIT=16'h07F8; +LUT4 \fifo_inst/Equal.wgraynext_7_s0 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wgraynext_6_4 ), + .I2(\fifo_inst/Equal.wbin [7]), + .I3(\fifo_inst/Equal.wbin [8]), + .F(\fifo_inst/Equal.wgraynext [7]) +); +defparam \fifo_inst/Equal.wgraynext_7_s0 .INIT=16'h07F8; +LUT3 \fifo_inst/Equal.wgraynext_8_s0 ( + .I0(\fifo_inst/Equal.wbin [8]), + .I1(\fifo_inst/Equal.wgraynext_8_4 ), + .I2(\fifo_inst/Equal.wbin [9]), + .F(\fifo_inst/Equal.wgraynext [8]) +); +defparam \fifo_inst/Equal.wgraynext_8_s0 .INIT=8'h1E; +LUT3 \fifo_inst/Equal.wgraynext_9_s0 ( + .I0(\fifo_inst/Equal.wbin [9]), + .I1(\fifo_inst/Equal.wgraynext_9_4 ), + .I2(\fifo_inst/Equal.wbin [10]), + .F(\fifo_inst/Equal.wgraynext [9]) +); +defparam \fifo_inst/Equal.wgraynext_9_s0 .INIT=8'h1E; +LUT3 \fifo_inst/Equal.wgraynext_10_s0 ( + .I0(\fifo_inst/Equal.wbin [10]), + .I1(\fifo_inst/Equal.wgraynext_10_4 ), + .I2(\fifo_inst/Equal.wbin [11]), + .F(\fifo_inst/Equal.wgraynext [10]) +); +defparam \fifo_inst/Equal.wgraynext_10_s0 .INIT=8'h1E; +LUT3 \fifo_inst/Equal.wgraynext_11_s0 ( + .I0(\fifo_inst/Equal.wbin [11]), + .I1(\fifo_inst/Equal.wgraynext_11_4 ), + .I2(\fifo_inst/Equal.wbin [12]), + .F(\fifo_inst/Equal.wgraynext [11]) +); +defparam \fifo_inst/Equal.wgraynext_11_s0 .INIT=8'h1E; +LUT3 \fifo_inst/Equal.wgraynext_12_s0 ( + .I0(\fifo_inst/Equal.wbin [12]), + .I1(\fifo_inst/Equal.wgraynext_12_4 ), + .I2(\fifo_inst/wptr [13]), + .F(\fifo_inst/Equal.wgraynext [12]) +); +defparam \fifo_inst/Equal.wgraynext_12_s0 .INIT=8'h1E; +LUT4 \fifo_inst/wfull_val_s0 ( + .I0(\fifo_inst/wfull_val_4 ), + .I1(\fifo_inst/wfull_val_5 ), + .I2(\fifo_inst/wfull_val_6 ), + .I3(\fifo_inst/wfull_val_7 ), + .F(\fifo_inst/wfull_val ) +); +defparam \fifo_inst/wfull_val_s0 .INIT=16'h8000; +LUT4 \fifo_inst/n476_s0 ( + .I0(\fifo_inst/rcnt_sub_d [0]), + .I1(RdEn), + .I2(\fifo_inst/rcnt_sub_d [1]), + .I3(\fifo_inst/n476_4 ), + .F(\fifo_inst/n476_3 ) +); +defparam \fifo_inst/n476_s0 .INIT=16'h4000; +LUT2 \fifo_inst/rbin_num_next_2_s3 ( + .I0(\fifo_inst/rbin_num [2]), + .I1(\fifo_inst/rbin_num_next_2_8 ), + .F(\fifo_inst/rbin_num_next [2]) +); +defparam \fifo_inst/rbin_num_next_2_s3 .INIT=4'h6; +LUT3 \fifo_inst/rbin_num_next_3_s3 ( + .I0(\fifo_inst/rbin_num [2]), + .I1(\fifo_inst/rbin_num_next_2_8 ), + .I2(\fifo_inst/rbin_num [3]), + .F(\fifo_inst/rbin_num_next [3]) +); +defparam \fifo_inst/rbin_num_next_3_s3 .INIT=8'h78; +LUT3 \fifo_inst/rbin_num_next_5_s3 ( + .I0(\fifo_inst/rbin_num [4]), + .I1(\fifo_inst/Equal.rgraynext_3_4 ), + .I2(\fifo_inst/rbin_num [5]), + .F(\fifo_inst/rbin_num_next [5]) +); +defparam \fifo_inst/rbin_num_next_5_s3 .INIT=8'h78; +LUT2 \fifo_inst/rbin_num_next_12_s3 ( + .I0(\fifo_inst/rbin_num [12]), + .I1(\fifo_inst/Equal.rgraynext_12_4 ), + .F(\fifo_inst/rbin_num_next [12]) +); +defparam \fifo_inst/rbin_num_next_12_s3 .INIT=4'h6; +LUT3 \fifo_inst/rbin_num_next_13_s2 ( + .I0(\fifo_inst/rbin_num [12]), + .I1(\fifo_inst/Equal.rgraynext_12_4 ), + .I2(\fifo_inst/rptr [13]), + .F(\fifo_inst/rbin_num_next [13]) +); +defparam \fifo_inst/rbin_num_next_13_s2 .INIT=8'h78; +LUT2 \fifo_inst/Equal.wbinnext_2_s3 ( + .I0(\fifo_inst/Equal.wbin [2]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .F(\fifo_inst/Equal.wbinnext [2]) +); +defparam \fifo_inst/Equal.wbinnext_2_s3 .INIT=4'h6; +LUT3 \fifo_inst/Equal.wbinnext_3_s3 ( + .I0(\fifo_inst/Equal.wbin [2]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wbin [3]), + .F(\fifo_inst/Equal.wbinnext [3]) +); +defparam \fifo_inst/Equal.wbinnext_3_s3 .INIT=8'h78; +LUT3 \fifo_inst/Equal.wbinnext_5_s3 ( + .I0(\fifo_inst/Equal.wbin [4]), + .I1(\fifo_inst/Equal.wgraynext_3_4 ), + .I2(\fifo_inst/Equal.wbin [5]), + .F(\fifo_inst/Equal.wbinnext [5]) +); +defparam \fifo_inst/Equal.wbinnext_5_s3 .INIT=8'h78; +LUT2 \fifo_inst/Equal.wbinnext_8_s3 ( + .I0(\fifo_inst/Equal.wbin [8]), + .I1(\fifo_inst/Equal.wgraynext_8_4 ), + .F(\fifo_inst/Equal.wbinnext [8]) +); +defparam \fifo_inst/Equal.wbinnext_8_s3 .INIT=4'h6; +LUT2 \fifo_inst/Equal.wbinnext_9_s3 ( + .I0(\fifo_inst/Equal.wbin [9]), + .I1(\fifo_inst/Equal.wgraynext_9_4 ), + .F(\fifo_inst/Equal.wbinnext [9]) +); +defparam \fifo_inst/Equal.wbinnext_9_s3 .INIT=4'h6; +LUT2 \fifo_inst/Equal.wbinnext_11_s3 ( + .I0(\fifo_inst/Equal.wbin [11]), + .I1(\fifo_inst/Equal.wgraynext_11_4 ), + .F(\fifo_inst/Equal.wbinnext [11]) +); +defparam \fifo_inst/Equal.wbinnext_11_s3 .INIT=4'h6; +LUT2 \fifo_inst/Equal.wbinnext_12_s3 ( + .I0(\fifo_inst/Equal.wbin [12]), + .I1(\fifo_inst/Equal.wgraynext_12_4 ), + .F(\fifo_inst/Equal.wbinnext [12]) +); +defparam \fifo_inst/Equal.wbinnext_12_s3 .INIT=4'h6; +LUT3 \fifo_inst/Equal.wbinnext_13_s2 ( + .I0(\fifo_inst/Equal.wbin [12]), + .I1(\fifo_inst/Equal.wgraynext_12_4 ), + .I2(\fifo_inst/wptr [13]), + .F(\fifo_inst/Equal.wbinnext [13]) +); +defparam \fifo_inst/Equal.wbinnext_13_s2 .INIT=8'h78; +LUT3 \fifo_inst/Equal.rgraynext_3_s1 ( + .I0(\fifo_inst/rbin_num [2]), + .I1(\fifo_inst/rbin_num [3]), + .I2(\fifo_inst/rbin_num_next_2_8 ), + .F(\fifo_inst/Equal.rgraynext_3_4 ) +); +defparam \fifo_inst/Equal.rgraynext_3_s1 .INIT=8'h80; +LUT2 \fifo_inst/Equal.rgraynext_6_s1 ( + .I0(\fifo_inst/rbin_num_next_2_8 ), + .I1(\fifo_inst/Equal.rgraynext_6_5 ), + .F(\fifo_inst/Equal.rgraynext_6_4 ) +); +defparam \fifo_inst/Equal.rgraynext_6_s1 .INIT=4'h8; +LUT2 \fifo_inst/Equal.rgraynext_8_s1 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/rbin_num [7]), + .F(\fifo_inst/Equal.rgraynext_8_4 ) +); +defparam \fifo_inst/Equal.rgraynext_8_s1 .INIT=4'h8; +LUT4 \fifo_inst/Equal.rgraynext_10_s1 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/rbin_num [7]), + .I2(\fifo_inst/rbin_num [8]), + .I3(\fifo_inst/rbin_num [9]), + .F(\fifo_inst/Equal.rgraynext_10_4 ) +); +defparam \fifo_inst/Equal.rgraynext_10_s1 .INIT=16'h8000; +LUT2 \fifo_inst/Equal.rgraynext_11_s1 ( + .I0(\fifo_inst/rbin_num [10]), + .I1(\fifo_inst/Equal.rgraynext_10_4 ), + .F(\fifo_inst/Equal.rgraynext_11_4 ) +); +defparam \fifo_inst/Equal.rgraynext_11_s1 .INIT=4'h8; +LUT4 \fifo_inst/Equal.rgraynext_12_s1 ( + .I0(\fifo_inst/rbin_num_next_2_8 ), + .I1(\fifo_inst/Equal.rgraynext_6_5 ), + .I2(\fifo_inst/Equal.rgraynext_10_4 ), + .I3(\fifo_inst/Equal.rgraynext_12_5 ), + .F(\fifo_inst/Equal.rgraynext_12_4 ) +); +defparam \fifo_inst/Equal.rgraynext_12_s1 .INIT=16'h8000; +LUT4 \fifo_inst/Equal.wcount_r_6_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [9]), + .I1(\fifo_inst/Equal.rq2_wptr [8]), + .I2(\fifo_inst/Equal.rq2_wptr [7]), + .I3(\fifo_inst/Equal.rq2_wptr [6]), + .F(\fifo_inst/Equal.wcount_r_6_4 ) +); +defparam \fifo_inst/Equal.wcount_r_6_s1 .INIT=16'h6996; +LUT3 \fifo_inst/Equal.wcount_r_2_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [4]), + .I1(\fifo_inst/Equal.rq2_wptr [3]), + .I2(\fifo_inst/Equal.rq2_wptr [2]), + .F(\fifo_inst/Equal.wcount_r_2_4 ) +); +defparam \fifo_inst/Equal.wcount_r_2_s1 .INIT=8'h69; +LUT2 \fifo_inst/Equal.wcount_r_1_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [5]), + .I1(\fifo_inst/Equal.rq2_wptr [1]), + .F(\fifo_inst/Equal.wcount_r_1_4 ) +); +defparam \fifo_inst/Equal.wcount_r_1_s1 .INIT=4'h6; +LUT3 \fifo_inst/Equal.wgraynext_3_s1 ( + .I0(\fifo_inst/Equal.wbin [2]), + .I1(\fifo_inst/Equal.wbin [3]), + .I2(\fifo_inst/Equal.wbinnext_2_8 ), + .F(\fifo_inst/Equal.wgraynext_3_4 ) +); +defparam \fifo_inst/Equal.wgraynext_3_s1 .INIT=8'h80; +LUT2 \fifo_inst/Equal.wgraynext_6_s1 ( + .I0(\fifo_inst/Equal.wbinnext_2_8 ), + .I1(\fifo_inst/Equal.wgraynext_6_5 ), + .F(\fifo_inst/Equal.wgraynext_6_4 ) +); +defparam \fifo_inst/Equal.wgraynext_6_s1 .INIT=4'h8; +LUT4 \fifo_inst/Equal.wgraynext_8_s1 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbin [7]), + .I2(\fifo_inst/Equal.wbinnext_2_8 ), + .I3(\fifo_inst/Equal.wgraynext_6_5 ), + .F(\fifo_inst/Equal.wgraynext_8_4 ) +); +defparam \fifo_inst/Equal.wgraynext_8_s1 .INIT=16'h8000; +LUT4 \fifo_inst/Equal.wgraynext_9_s1 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wgraynext_6_5 ), + .I3(\fifo_inst/Equal.wgraynext_9_5 ), + .F(\fifo_inst/Equal.wgraynext_9_4 ) +); +defparam \fifo_inst/Equal.wgraynext_9_s1 .INIT=16'h8000; +LUT3 \fifo_inst/Equal.wgraynext_10_s1 ( + .I0(\fifo_inst/Equal.wbinnext_2_8 ), + .I1(\fifo_inst/Equal.wgraynext_6_5 ), + .I2(\fifo_inst/Equal.wgraynext_10_5 ), + .F(\fifo_inst/Equal.wgraynext_10_4 ) +); +defparam \fifo_inst/Equal.wgraynext_10_s1 .INIT=8'h80; +LUT4 \fifo_inst/Equal.wgraynext_11_s1 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wgraynext_6_5 ), + .I3(\fifo_inst/Equal.wgraynext_11_5 ), + .F(\fifo_inst/Equal.wgraynext_11_4 ) +); +defparam \fifo_inst/Equal.wgraynext_11_s1 .INIT=16'h8000; +LUT4 \fifo_inst/Equal.wgraynext_12_s1 ( + .I0(\fifo_inst/Equal.wbinnext_2_8 ), + .I1(\fifo_inst/Equal.wgraynext_6_5 ), + .I2(\fifo_inst/Equal.wgraynext_11_5 ), + .I3(\fifo_inst/Equal.wgraynext_12_5 ), + .F(\fifo_inst/Equal.wgraynext_12_4 ) +); +defparam \fifo_inst/Equal.wgraynext_12_s1 .INIT=16'h8000; +LUT4 \fifo_inst/wfull_val_s1 ( + .I0(\fifo_inst/wptr [1]), + .I1(\fifo_inst/rptr [1]), + .I2(\fifo_inst/wptr [7]), + .I3(\fifo_inst/rptr [7]), + .F(\fifo_inst/wfull_val_4 ) +); +defparam \fifo_inst/wfull_val_s1 .INIT=16'h9009; +LUT4 \fifo_inst/wfull_val_s2 ( + .I0(\fifo_inst/wptr [5]), + .I1(\fifo_inst/rptr [5]), + .I2(\fifo_inst/wptr [12]), + .I3(\fifo_inst/rptr [12]), + .F(\fifo_inst/wfull_val_5 ) +); +defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990; +LUT4 \fifo_inst/wfull_val_s3 ( + .I0(\fifo_inst/wptr [0]), + .I1(\fifo_inst/rptr [0]), + .I2(\fifo_inst/wptr [8]), + .I3(\fifo_inst/rptr [8]), + .F(\fifo_inst/wfull_val_6 ) +); +defparam \fifo_inst/wfull_val_s3 .INIT=16'h9009; +LUT4 \fifo_inst/wfull_val_s4 ( + .I0(\fifo_inst/wfull_val_8 ), + .I1(\fifo_inst/wfull_val_9 ), + .I2(\fifo_inst/wfull_val_10 ), + .I3(\fifo_inst/wfull_val_11 ), + .F(\fifo_inst/wfull_val_7 ) +); +defparam \fifo_inst/wfull_val_s4 .INIT=16'h8000; +LUT3 \fifo_inst/n476_s1 ( + .I0(\fifo_inst/n476_5 ), + .I1(\fifo_inst/n476_6 ), + .I2(\fifo_inst/n476_7 ), + .F(\fifo_inst/n476_4 ) +); +defparam \fifo_inst/n476_s1 .INIT=8'h80; +LUT4 \fifo_inst/rbin_num_next_2_s4 ( + .I0(Empty), + .I1(RdEn), + .I2(\fifo_inst/rbin_num [0]), + .I3(\fifo_inst/rbin_num [1]), + .F(\fifo_inst/rbin_num_next_2_8 ) +); +defparam \fifo_inst/rbin_num_next_2_s4 .INIT=16'h4000; +LUT4 \fifo_inst/Equal.wbinnext_2_s4 ( + .I0(Full), + .I1(WrEn), + .I2(\fifo_inst/Equal.wbin [0]), + .I3(\fifo_inst/Equal.wbin [1]), + .F(\fifo_inst/Equal.wbinnext_2_8 ) +); +defparam \fifo_inst/Equal.wbinnext_2_s4 .INIT=16'h4000; +LUT4 \fifo_inst/Equal.rgraynext_6_s2 ( + .I0(\fifo_inst/rbin_num [2]), + .I1(\fifo_inst/rbin_num [3]), + .I2(\fifo_inst/rbin_num [4]), + .I3(\fifo_inst/rbin_num [5]), + .F(\fifo_inst/Equal.rgraynext_6_5 ) +); +defparam \fifo_inst/Equal.rgraynext_6_s2 .INIT=16'h8000; +LUT2 \fifo_inst/Equal.rgraynext_12_s2 ( + .I0(\fifo_inst/rbin_num [10]), + .I1(\fifo_inst/rbin_num [11]), + .F(\fifo_inst/Equal.rgraynext_12_5 ) +); +defparam \fifo_inst/Equal.rgraynext_12_s2 .INIT=4'h8; +LUT4 \fifo_inst/Equal.wgraynext_6_s2 ( + .I0(\fifo_inst/Equal.wbin [2]), + .I1(\fifo_inst/Equal.wbin [3]), + .I2(\fifo_inst/Equal.wbin [4]), + .I3(\fifo_inst/Equal.wbin [5]), + .F(\fifo_inst/Equal.wgraynext_6_5 ) +); +defparam \fifo_inst/Equal.wgraynext_6_s2 .INIT=16'h8000; +LUT2 \fifo_inst/Equal.wgraynext_9_s2 ( + .I0(\fifo_inst/Equal.wbin [7]), + .I1(\fifo_inst/Equal.wbin [8]), + .F(\fifo_inst/Equal.wgraynext_9_5 ) +); +defparam \fifo_inst/Equal.wgraynext_9_s2 .INIT=4'h8; +LUT4 \fifo_inst/Equal.wgraynext_10_s2 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbin [7]), + .I2(\fifo_inst/Equal.wbin [8]), + .I3(\fifo_inst/Equal.wbin [9]), + .F(\fifo_inst/Equal.wgraynext_10_5 ) +); +defparam \fifo_inst/Equal.wgraynext_10_s2 .INIT=16'h8000; +LUT4 \fifo_inst/Equal.wgraynext_11_s2 ( + .I0(\fifo_inst/Equal.wbin [7]), + .I1(\fifo_inst/Equal.wbin [8]), + .I2(\fifo_inst/Equal.wbin [9]), + .I3(\fifo_inst/Equal.wbin [10]), + .F(\fifo_inst/Equal.wgraynext_11_5 ) +); +defparam \fifo_inst/Equal.wgraynext_11_s2 .INIT=16'h8000; +LUT2 \fifo_inst/Equal.wgraynext_12_s2 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbin [11]), + .F(\fifo_inst/Equal.wgraynext_12_5 ) +); +defparam \fifo_inst/Equal.wgraynext_12_s2 .INIT=4'h8; +LUT4 \fifo_inst/wfull_val_s5 ( + .I0(\fifo_inst/wptr [3]), + .I1(\fifo_inst/rptr [3]), + .I2(\fifo_inst/wptr [6]), + .I3(\fifo_inst/rptr [6]), + .F(\fifo_inst/wfull_val_8 ) +); +defparam \fifo_inst/wfull_val_s5 .INIT=16'h9009; +LUT4 \fifo_inst/wfull_val_s6 ( + .I0(\fifo_inst/wptr [2]), + .I1(\fifo_inst/rptr [2]), + .I2(\fifo_inst/wptr [13]), + .I3(\fifo_inst/rptr [13]), + .F(\fifo_inst/wfull_val_9 ) +); +defparam \fifo_inst/wfull_val_s6 .INIT=16'h0990; +LUT4 \fifo_inst/wfull_val_s7 ( + .I0(\fifo_inst/wptr [9]), + .I1(\fifo_inst/rptr [9]), + .I2(\fifo_inst/wptr [10]), + .I3(\fifo_inst/rptr [10]), + .F(\fifo_inst/wfull_val_10 ) +); +defparam \fifo_inst/wfull_val_s7 .INIT=16'h9009; +LUT4 \fifo_inst/wfull_val_s8 ( + .I0(\fifo_inst/wptr [4]), + .I1(\fifo_inst/rptr [4]), + .I2(\fifo_inst/wptr [11]), + .I3(\fifo_inst/rptr [11]), + .F(\fifo_inst/wfull_val_11 ) +); +defparam \fifo_inst/wfull_val_s8 .INIT=16'h9009; +LUT4 \fifo_inst/n476_s2 ( + .I0(\fifo_inst/rcnt_sub_d [10]), + .I1(\fifo_inst/rcnt_sub_d [11]), + .I2(\fifo_inst/rcnt_sub_d [12]), + .I3(\fifo_inst/rcnt_sub_d [13]), + .F(\fifo_inst/n476_5 ) +); +defparam \fifo_inst/n476_s2 .INIT=16'h0001; +LUT4 \fifo_inst/n476_s3 ( + .I0(\fifo_inst/rcnt_sub_d [6]), + .I1(\fifo_inst/rcnt_sub_d [7]), + .I2(\fifo_inst/rcnt_sub_d [8]), + .I3(\fifo_inst/rcnt_sub_d [9]), + .F(\fifo_inst/n476_6 ) +); +defparam \fifo_inst/n476_s3 .INIT=16'h0001; +LUT4 \fifo_inst/n476_s4 ( + .I0(\fifo_inst/rcnt_sub_d [2]), + .I1(\fifo_inst/rcnt_sub_d [3]), + .I2(\fifo_inst/rcnt_sub_d [4]), + .I3(\fifo_inst/rcnt_sub_d [5]), + .F(\fifo_inst/n476_7 ) +); +defparam \fifo_inst/n476_s4 .INIT=16'h0001; +LUT4 \fifo_inst/rbin_num_next_11_s4 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/rbin_num [10]), + .I2(\fifo_inst/Equal.rgraynext_10_4 ), + .I3(\fifo_inst/rbin_num [11]), + .F(\fifo_inst/rbin_num_next [11]) +); +defparam \fifo_inst/rbin_num_next_11_s4 .INIT=16'h7F80; +LUT3 \fifo_inst/Equal.wcount_r_11_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [11]), + .I1(\fifo_inst/Equal.rq2_wptr [13]), + .I2(\fifo_inst/Equal.rq2_wptr [12]), + .F(\fifo_inst/Equal.wcount_r [11]) +); +defparam \fifo_inst/Equal.wcount_r_11_s1 .INIT=8'h96; +LUT4 \fifo_inst/Equal.wcount_r_2_s2 ( + .I0(\fifo_inst/Equal.wcount_r [5]), + .I1(\fifo_inst/Equal.rq2_wptr [4]), + .I2(\fifo_inst/Equal.rq2_wptr [3]), + .I3(\fifo_inst/Equal.rq2_wptr [2]), + .F(\fifo_inst/Equal.wcount_r [2]) +); +defparam \fifo_inst/Equal.wcount_r_2_s2 .INIT=16'h6996; +LUT4 \fifo_inst/Equal.wbinnext_10_s4 ( + .I0(\fifo_inst/Equal.wbin [10]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wgraynext_6_5 ), + .I3(\fifo_inst/Equal.wgraynext_10_5 ), + .F(\fifo_inst/Equal.wbinnext [10]) +); +defparam \fifo_inst/Equal.wbinnext_10_s4 .INIT=16'h6AAA; +LUT4 \fifo_inst/n473_s43 ( + .I0(\fifo_inst/rcnt_sub_d [1]), + .I1(\fifo_inst/n476_5 ), + .I2(\fifo_inst/n476_6 ), + .I3(\fifo_inst/n476_7 ), + .F(\fifo_inst/n473_61 ) +); +defparam \fifo_inst/n473_s43 .INIT=16'h4000; +LUT3 \fifo_inst/Equal.rgraynext_9_s2 ( + .I0(\fifo_inst/rbin_num [8]), + .I1(\fifo_inst/rbin_num [6]), + .I2(\fifo_inst/rbin_num [7]), + .F(\fifo_inst/Equal.rgraynext_9_6 ) +); +defparam \fifo_inst/Equal.rgraynext_9_s2 .INIT=8'h80; +LUT4 \fifo_inst/rbin_num_next_8_s4 ( + .I0(\fifo_inst/Equal.rgraynext_6_4 ), + .I1(\fifo_inst/rbin_num [6]), + .I2(\fifo_inst/rbin_num [7]), + .I3(\fifo_inst/rbin_num [8]), + .F(\fifo_inst/rbin_num_next [8]) +); +defparam \fifo_inst/rbin_num_next_8_s4 .INIT=16'h7F80; +LUT3 \fifo_inst/Equal.wgraynext_2_s1 ( + .I0(\fifo_inst/Equal.wbin [2]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wbinnext [3]), + .F(\fifo_inst/Equal.wgraynext [2]) +); +defparam \fifo_inst/Equal.wgraynext_2_s1 .INIT=8'h96; +LUT3 \fifo_inst/Equal.wgraynext_1_s1 ( + .I0(\fifo_inst/Equal.wbinnext [1]), + .I1(\fifo_inst/Equal.wbin [2]), + .I2(\fifo_inst/Equal.wbinnext_2_8 ), + .F(\fifo_inst/Equal.wgraynext [1]) +); +defparam \fifo_inst/Equal.wgraynext_1_s1 .INIT=8'h96; +LUT4 \fifo_inst/Equal.wcount_r_7_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [8]), + .I1(\fifo_inst/Equal.rq2_wptr [7]), + .I2(\fifo_inst/Equal.rq2_wptr [9]), + .I3(\fifo_inst/Equal.wcount_r [10]), + .F(\fifo_inst/Equal.wcount_r [7]) +); +defparam \fifo_inst/Equal.wcount_r_7_s1 .INIT=16'h6996; +LUT3 \fifo_inst/Equal.wcount_r_8_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [8]), + .I1(\fifo_inst/Equal.rq2_wptr [9]), + .I2(\fifo_inst/Equal.wcount_r [10]), + .F(\fifo_inst/Equal.wcount_r [8]) +); +defparam \fifo_inst/Equal.wcount_r_8_s1 .INIT=8'h96; +LUT3 \fifo_inst/Equal.rgraynext_2_s1 ( + .I0(\fifo_inst/rbin_num [2]), + .I1(\fifo_inst/rbin_num_next_2_8 ), + .I2(\fifo_inst/rbin_num_next [3]), + .F(\fifo_inst/Equal.rgraynext [2]) +); +defparam \fifo_inst/Equal.rgraynext_2_s1 .INIT=8'h96; +LUT3 \fifo_inst/Equal.rgraynext_1_s1 ( + .I0(\fifo_inst/rbin_num_next [1]), + .I1(\fifo_inst/rbin_num [2]), + .I2(\fifo_inst/rbin_num_next_2_8 ), + .F(\fifo_inst/Equal.rgraynext [1]) +); +defparam \fifo_inst/Equal.rgraynext_1_s1 .INIT=8'h96; +LUT4 \fifo_inst/Equal.wcount_r_4_s1 ( + .I0(\fifo_inst/Equal.rq2_wptr [4]), + .I1(\fifo_inst/Equal.rq2_wptr [5]), + .I2(\fifo_inst/Equal.wcount_r [10]), + .I3(\fifo_inst/Equal.wcount_r_6_4 ), + .F(\fifo_inst/Equal.wcount_r [4]) +); +defparam \fifo_inst/Equal.wcount_r_4_s1 .INIT=16'h6996; +LUT4 \fifo_inst/Equal.wbinnext_7_s4 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wgraynext_6_5 ), + .I3(\fifo_inst/Equal.wbin [7]), + .F(\fifo_inst/Equal.wbinnext [7]) +); +defparam \fifo_inst/Equal.wbinnext_7_s4 .INIT=16'h7F80; +LUT3 \fifo_inst/Equal.wbinnext_6_s4 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wgraynext_6_5 ), + .F(\fifo_inst/Equal.wbinnext [6]) +); +defparam \fifo_inst/Equal.wbinnext_6_s4 .INIT=8'h6A; +LUT4 \fifo_inst/Equal.wgraynext_6_s3 ( + .I0(\fifo_inst/Equal.wbin [6]), + .I1(\fifo_inst/Equal.wbinnext_2_8 ), + .I2(\fifo_inst/Equal.wgraynext_6_5 ), + .I3(\fifo_inst/Equal.wbin [7]), + .F(\fifo_inst/Equal.wgraynext [6]) +); +defparam \fifo_inst/Equal.wgraynext_6_s3 .INIT=16'h15EA; +LUT4 \fifo_inst/rbin_num_next_4_s4 ( + .I0(\fifo_inst/rbin_num [4]), + .I1(\fifo_inst/rbin_num [2]), + .I2(\fifo_inst/rbin_num [3]), + .I3(\fifo_inst/rbin_num_next_2_8 ), + .F(\fifo_inst/rbin_num_next [4]) +); +defparam \fifo_inst/rbin_num_next_4_s4 .INIT=16'h6AAA; +LUT4 \fifo_inst/Equal.wbinnext_4_s4 ( + .I0(\fifo_inst/Equal.wbin [4]), + .I1(\fifo_inst/Equal.wbin [2]), + .I2(\fifo_inst/Equal.wbin [3]), + .I3(\fifo_inst/Equal.wbinnext_2_8 ), + .F(\fifo_inst/Equal.wbinnext [4]) +); +defparam \fifo_inst/Equal.wbinnext_4_s4 .INIT=16'h6AAA; +LUT4 \fifo_inst/Equal.wbinnext_1_s4 ( + .I0(\fifo_inst/Equal.wbin [0]), + .I1(Full), + .I2(WrEn), + .I3(\fifo_inst/Equal.wbin [1]), + .F(\fifo_inst/Equal.wbinnext [1]) +); +defparam \fifo_inst/Equal.wbinnext_1_s4 .INIT=16'hDF20; +LUT3 \fifo_inst/Equal.wbinnext_0_s4 ( + .I0(\fifo_inst/Equal.wbin [0]), + .I1(Full), + .I2(WrEn), + .F(\fifo_inst/Equal.wbinnext_0_9 ) +); +defparam \fifo_inst/Equal.wbinnext_0_s4 .INIT=8'h9A; +LUT4 \fifo_inst/rbin_num_next_1_s4 ( + .I0(\fifo_inst/rbin_num [0]), + .I1(Empty), + .I2(RdEn), + .I3(\fifo_inst/rbin_num [1]), + .F(\fifo_inst/rbin_num_next [1]) +); +defparam \fifo_inst/rbin_num_next_1_s4 .INIT=16'hDF20; +LUT3 \fifo_inst/rbin_num_next_0_s4 ( + .I0(\fifo_inst/rbin_num [0]), + .I1(Empty), + .I2(RdEn), + .F(\fifo_inst/rbin_num_next_0_9 ) +); +defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'h9A; +LUT4 \fifo_inst/rbin_num_next_10_s4 ( + .I0(\fifo_inst/rbin_num_next_2_8 ), + .I1(\fifo_inst/Equal.rgraynext_6_5 ), + .I2(\fifo_inst/Equal.rgraynext_10_4 ), + .I3(\fifo_inst/rbin_num [10]), + .F(\fifo_inst/rbin_num_next [10]) +); +defparam \fifo_inst/rbin_num_next_10_s4 .INIT=16'h7F80; +LUT4 \fifo_inst/rbin_num_next_9_s4 ( + .I0(\fifo_inst/rbin_num_next_2_8 ), + .I1(\fifo_inst/Equal.rgraynext_6_5 ), + .I2(\fifo_inst/Equal.rgraynext_9_6 ), + .I3(\fifo_inst/rbin_num [9]), + .F(\fifo_inst/rbin_num_next [9]) +); +defparam \fifo_inst/rbin_num_next_9_s4 .INIT=16'h7F80; +LUT4 \fifo_inst/rbin_num_next_7_s4 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/rbin_num_next_2_8 ), + .I2(\fifo_inst/Equal.rgraynext_6_5 ), + .I3(\fifo_inst/rbin_num [7]), + .F(\fifo_inst/rbin_num_next [7]) +); +defparam \fifo_inst/rbin_num_next_7_s4 .INIT=16'h7F80; +LUT3 \fifo_inst/rbin_num_next_6_s4 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/rbin_num_next_2_8 ), + .I2(\fifo_inst/Equal.rgraynext_6_5 ), + .F(\fifo_inst/rbin_num_next [6]) +); +defparam \fifo_inst/rbin_num_next_6_s4 .INIT=8'h6A; +LUT4 \fifo_inst/Equal.rgraynext_6_s3 ( + .I0(\fifo_inst/rbin_num [6]), + .I1(\fifo_inst/rbin_num_next_2_8 ), + .I2(\fifo_inst/Equal.rgraynext_6_5 ), + .I3(\fifo_inst/rbin_num [7]), + .F(\fifo_inst/Equal.rgraynext [6]) +); +defparam \fifo_inst/Equal.rgraynext_6_s3 .INIT=16'h15EA; +LUT3 \fifo_inst/rempty_val_s2 ( + .I0(\fifo_inst/wptr [13]), + .I1(\fifo_inst/rptr [13]), + .I2(\fifo_inst/n118_3 ), + .F(\fifo_inst/rempty_val ) +); +defparam \fifo_inst/rempty_val_s2 .INIT=8'h09; +LUT4 \fifo_inst/Equal.wgraynext_0_s1 ( + .I0(\fifo_inst/Equal.wbinnext [1]), + .I1(\fifo_inst/Equal.wbin [0]), + .I2(Full), + .I3(WrEn), + .F(\fifo_inst/Equal.wgraynext [0]) +); +defparam \fifo_inst/Equal.wgraynext_0_s1 .INIT=16'h6966; +LUT4 \fifo_inst/Equal.rgraynext_0_s1 ( + .I0(\fifo_inst/rbin_num_next [1]), + .I1(\fifo_inst/rbin_num [0]), + .I2(Empty), + .I3(RdEn), + .F(\fifo_inst/Equal.rgraynext [0]) +); +defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h6966; +DFF \fifo_inst/rbin_num_12_s0 ( + .D(\fifo_inst/rbin_num_next [12]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [12]) +); +defparam \fifo_inst/rbin_num_12_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_11_s0 ( + .D(\fifo_inst/rbin_num_next [11]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [11]) +); +defparam \fifo_inst/rbin_num_11_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_10_s0 ( + .D(\fifo_inst/rbin_num_next [10]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [10]) +); +defparam \fifo_inst/rbin_num_10_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_9_s0 ( + .D(\fifo_inst/rbin_num_next [9]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [9]) +); +defparam \fifo_inst/rbin_num_9_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_8_s0 ( + .D(\fifo_inst/rbin_num_next [8]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [8]) +); +defparam \fifo_inst/rbin_num_8_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_7_s0 ( + .D(\fifo_inst/rbin_num_next [7]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [7]) +); +defparam \fifo_inst/rbin_num_7_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_6_s0 ( + .D(\fifo_inst/rbin_num_next [6]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [6]) +); +defparam \fifo_inst/rbin_num_6_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_5_s0 ( + .D(\fifo_inst/rbin_num_next [5]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [5]) +); +defparam \fifo_inst/rbin_num_5_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_4_s0 ( + .D(\fifo_inst/rbin_num_next [4]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [4]) +); +defparam \fifo_inst/rbin_num_4_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_3_s0 ( + .D(\fifo_inst/rbin_num_next [3]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [3]) +); +defparam \fifo_inst/rbin_num_3_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_2_s0 ( + .D(\fifo_inst/rbin_num_next [2]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [2]) +); +defparam \fifo_inst/rbin_num_2_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_1_s0 ( + .D(\fifo_inst/rbin_num_next [1]), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [1]) +); +defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0; +DFF \fifo_inst/rbin_num_0_s0 ( + .D(\fifo_inst/rbin_num_next_0_9 ), + .CLK(RdClk), + .Q(\fifo_inst/rbin_num [0]) +); +defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_13_s0 ( + .D(\fifo_inst/rbin_num_next [13]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [13]) +); +defparam \fifo_inst/rptr_13_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_12_s0 ( + .D(\fifo_inst/Equal.rgraynext [12]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [12]) +); +defparam \fifo_inst/rptr_12_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_11_s0 ( + .D(\fifo_inst/Equal.rgraynext [11]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [11]) +); +defparam \fifo_inst/rptr_11_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_10_s0 ( + .D(\fifo_inst/Equal.rgraynext [10]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [10]) +); +defparam \fifo_inst/rptr_10_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_9_s0 ( + .D(\fifo_inst/Equal.rgraynext [9]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [9]) +); +defparam \fifo_inst/rptr_9_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_8_s0 ( + .D(\fifo_inst/Equal.rgraynext [8]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [8]) +); +defparam \fifo_inst/rptr_8_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_7_s0 ( + .D(\fifo_inst/Equal.rgraynext [7]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [7]) +); +defparam \fifo_inst/rptr_7_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_6_s0 ( + .D(\fifo_inst/Equal.rgraynext [6]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [6]) +); +defparam \fifo_inst/rptr_6_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_5_s0 ( + .D(\fifo_inst/Equal.rgraynext [5]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [5]) +); +defparam \fifo_inst/rptr_5_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_4_s0 ( + .D(\fifo_inst/Equal.rgraynext [4]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [4]) +); +defparam \fifo_inst/rptr_4_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_3_s0 ( + .D(\fifo_inst/Equal.rgraynext [3]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [3]) +); +defparam \fifo_inst/rptr_3_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_2_s0 ( + .D(\fifo_inst/Equal.rgraynext [2]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [2]) +); +defparam \fifo_inst/rptr_2_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_1_s0 ( + .D(\fifo_inst/Equal.rgraynext [1]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [1]) +); +defparam \fifo_inst/rptr_1_s0 .INIT=1'b0; +DFF \fifo_inst/rptr_0_s0 ( + .D(\fifo_inst/Equal.rgraynext [0]), + .CLK(RdClk), + .Q(\fifo_inst/rptr [0]) +); +defparam \fifo_inst/rptr_0_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_13_s0 ( + .D(\fifo_inst/Equal.wbinnext [13]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [13]) +); +defparam \fifo_inst/wptr_13_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_12_s0 ( + .D(\fifo_inst/Equal.wgraynext [12]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [12]) +); +defparam \fifo_inst/wptr_12_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_11_s0 ( + .D(\fifo_inst/Equal.wgraynext [11]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [11]) +); +defparam \fifo_inst/wptr_11_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_10_s0 ( + .D(\fifo_inst/Equal.wgraynext [10]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [10]) +); +defparam \fifo_inst/wptr_10_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_9_s0 ( + .D(\fifo_inst/Equal.wgraynext [9]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [9]) +); +defparam \fifo_inst/wptr_9_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_8_s0 ( + .D(\fifo_inst/Equal.wgraynext [8]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [8]) +); +defparam \fifo_inst/wptr_8_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_7_s0 ( + .D(\fifo_inst/Equal.wgraynext [7]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [7]) +); +defparam \fifo_inst/wptr_7_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_6_s0 ( + .D(\fifo_inst/Equal.wgraynext [6]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [6]) +); +defparam \fifo_inst/wptr_6_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_5_s0 ( + .D(\fifo_inst/Equal.wgraynext [5]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [5]) +); +defparam \fifo_inst/wptr_5_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_4_s0 ( + .D(\fifo_inst/Equal.wgraynext [4]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [4]) +); +defparam \fifo_inst/wptr_4_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_3_s0 ( + .D(\fifo_inst/Equal.wgraynext [3]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [3]) +); +defparam \fifo_inst/wptr_3_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_2_s0 ( + .D(\fifo_inst/Equal.wgraynext [2]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [2]) +); +defparam \fifo_inst/wptr_2_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_1_s0 ( + .D(\fifo_inst/Equal.wgraynext [1]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [1]) +); +defparam \fifo_inst/wptr_1_s0 .INIT=1'b0; +DFF \fifo_inst/wptr_0_s0 ( + .D(\fifo_inst/Equal.wgraynext [0]), + .CLK(WrClk), + .Q(\fifo_inst/wptr [0]) +); +defparam \fifo_inst/wptr_0_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_12_s0 ( + .D(\fifo_inst/Equal.wbinnext [12]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [12]) +); +defparam \fifo_inst/Equal.wbin_12_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_11_s0 ( + .D(\fifo_inst/Equal.wbinnext [11]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [11]) +); +defparam \fifo_inst/Equal.wbin_11_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_10_s0 ( + .D(\fifo_inst/Equal.wbinnext [10]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [10]) +); +defparam \fifo_inst/Equal.wbin_10_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_9_s0 ( + .D(\fifo_inst/Equal.wbinnext [9]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [9]) +); +defparam \fifo_inst/Equal.wbin_9_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_8_s0 ( + .D(\fifo_inst/Equal.wbinnext [8]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [8]) +); +defparam \fifo_inst/Equal.wbin_8_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_7_s0 ( + .D(\fifo_inst/Equal.wbinnext [7]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [7]) +); +defparam \fifo_inst/Equal.wbin_7_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_6_s0 ( + .D(\fifo_inst/Equal.wbinnext [6]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [6]) +); +defparam \fifo_inst/Equal.wbin_6_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_5_s0 ( + .D(\fifo_inst/Equal.wbinnext [5]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [5]) +); +defparam \fifo_inst/Equal.wbin_5_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_4_s0 ( + .D(\fifo_inst/Equal.wbinnext [4]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [4]) +); +defparam \fifo_inst/Equal.wbin_4_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_3_s0 ( + .D(\fifo_inst/Equal.wbinnext [3]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [3]) +); +defparam \fifo_inst/Equal.wbin_3_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_2_s0 ( + .D(\fifo_inst/Equal.wbinnext [2]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [2]) +); +defparam \fifo_inst/Equal.wbin_2_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_1_s0 ( + .D(\fifo_inst/Equal.wbinnext [1]), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [1]) +); +defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wbin_0_s0 ( + .D(\fifo_inst/Equal.wbinnext_0_9 ), + .CLK(WrClk), + .Q(\fifo_inst/Equal.wbin [0]) +); +defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_13_s0 ( + .D(\fifo_inst/Equal.rq2_wptr [13]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [13]) +); +defparam \fifo_inst/Equal.wcount_r_d_13_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_12_s0 ( + .D(\fifo_inst/Equal.wcount_r [12]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [12]) +); +defparam \fifo_inst/Equal.wcount_r_d_12_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_11_s0 ( + .D(\fifo_inst/Equal.wcount_r [11]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [11]) +); +defparam \fifo_inst/Equal.wcount_r_d_11_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_10_s0 ( + .D(\fifo_inst/Equal.wcount_r [10]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [10]) +); +defparam \fifo_inst/Equal.wcount_r_d_10_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_9_s0 ( + .D(\fifo_inst/Equal.wcount_r [9]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [9]) +); +defparam \fifo_inst/Equal.wcount_r_d_9_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_8_s0 ( + .D(\fifo_inst/Equal.wcount_r [8]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [8]) +); +defparam \fifo_inst/Equal.wcount_r_d_8_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_7_s0 ( + .D(\fifo_inst/Equal.wcount_r [7]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [7]) +); +defparam \fifo_inst/Equal.wcount_r_d_7_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_6_s0 ( + .D(\fifo_inst/Equal.wcount_r [6]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [6]) +); +defparam \fifo_inst/Equal.wcount_r_d_6_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_5_s0 ( + .D(\fifo_inst/Equal.wcount_r [5]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [5]) +); +defparam \fifo_inst/Equal.wcount_r_d_5_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_4_s0 ( + .D(\fifo_inst/Equal.wcount_r [4]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [4]) +); +defparam \fifo_inst/Equal.wcount_r_d_4_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_3_s0 ( + .D(\fifo_inst/Equal.wcount_r [3]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [3]) +); +defparam \fifo_inst/Equal.wcount_r_d_3_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_2_s0 ( + .D(\fifo_inst/Equal.wcount_r [2]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [2]) +); +defparam \fifo_inst/Equal.wcount_r_d_2_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_1_s0 ( + .D(\fifo_inst/Equal.wcount_r [1]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [1]) +); +defparam \fifo_inst/Equal.wcount_r_d_1_s0 .INIT=1'b0; +DFF \fifo_inst/Equal.wcount_r_d_0_s0 ( + .D(\fifo_inst/Equal.wcount_r [0]), + .CLK(RdClk), + .Q(\fifo_inst/Equal.wcount_r_d [0]) +); +defparam \fifo_inst/Equal.wcount_r_d_0_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_13_s0 ( + .D(\fifo_inst/rcnt_sub [13]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [13]) +); +defparam \fifo_inst/rcnt_sub_d_13_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_12_s0 ( + .D(\fifo_inst/rcnt_sub [12]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [12]) +); +defparam \fifo_inst/rcnt_sub_d_12_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_11_s0 ( + .D(\fifo_inst/rcnt_sub [11]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [11]) +); +defparam \fifo_inst/rcnt_sub_d_11_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_10_s0 ( + .D(\fifo_inst/rcnt_sub [10]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [10]) +); +defparam \fifo_inst/rcnt_sub_d_10_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_9_s0 ( + .D(\fifo_inst/rcnt_sub [9]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [9]) +); +defparam \fifo_inst/rcnt_sub_d_9_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_8_s0 ( + .D(\fifo_inst/rcnt_sub [8]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [8]) +); +defparam \fifo_inst/rcnt_sub_d_8_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_7_s0 ( + .D(\fifo_inst/rcnt_sub [7]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [7]) +); +defparam \fifo_inst/rcnt_sub_d_7_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_6_s0 ( + .D(\fifo_inst/rcnt_sub [6]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [6]) +); +defparam \fifo_inst/rcnt_sub_d_6_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_5_s0 ( + .D(\fifo_inst/rcnt_sub [5]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [5]) +); +defparam \fifo_inst/rcnt_sub_d_5_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_4_s0 ( + .D(\fifo_inst/rcnt_sub [4]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [4]) +); +defparam \fifo_inst/rcnt_sub_d_4_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_3_s0 ( + .D(\fifo_inst/rcnt_sub [3]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [3]) +); +defparam \fifo_inst/rcnt_sub_d_3_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_2_s0 ( + .D(\fifo_inst/rcnt_sub [2]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [2]) +); +defparam \fifo_inst/rcnt_sub_d_2_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_1_s0 ( + .D(\fifo_inst/rcnt_sub [1]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [1]) +); +defparam \fifo_inst/rcnt_sub_d_1_s0 .INIT=1'b0; +DFF \fifo_inst/rcnt_sub_d_0_s0 ( + .D(\fifo_inst/rcnt_sub [0]), + .CLK(RdClk), + .Q(\fifo_inst/rcnt_sub_d [0]) +); +defparam \fifo_inst/rcnt_sub_d_0_s0 .INIT=1'b0; +DFFP \fifo_inst/rempty_val1_s0 ( + .D(\fifo_inst/rempty_val ), + .CLK(RdClk), + .PRESET(\fifo_inst/rempty_val ), + .Q(\fifo_inst/rempty_val1 ) +); +defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1; +DFFP \fifo_inst/Empty_s0 ( + .D(\fifo_inst/rempty_val1 ), + .CLK(RdClk), + .PRESET(\fifo_inst/rempty_val ), + .Q(Empty) +); +defparam \fifo_inst/Empty_s0 .INIT=1'b1; +DFFS \fifo_inst/Almost_Empty_s0 ( + .D(\fifo_inst/n476_3 ), + .CLK(RdClk), + .SET(\fifo_inst/n473_61 ), + .Q(Almost_Empty) +); +defparam \fifo_inst/Almost_Empty_s0 .INIT=1'b1; +DFFP \fifo_inst/wfull_val1_s0 ( + .D(\fifo_inst/wfull_val ), + .CLK(WrClk), + .PRESET(\fifo_inst/wfull_val ), + .Q(\fifo_inst/wfull_val1 ) +); +defparam \fifo_inst/wfull_val1_s0 .INIT=1'b1; +DFFP \fifo_inst/Full_s0 ( + .D(\fifo_inst/wfull_val1 ), + .CLK(WrClk), + .PRESET(\fifo_inst/wfull_val ), + .Q(Full) +); +defparam \fifo_inst/Full_s0 .INIT=1'b1; +DFF \fifo_inst/Equal.rq1_wptr_0_s2 ( + .D(\fifo_inst/Equal.rq1_wptr_0_20 ), + .CLK(RdClk), + .Q(\fifo_inst/Equal.rq1_wptr_0_5 ) +); +defparam \fifo_inst/Equal.rq1_wptr_0_s2 .INIT=1'b0; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[1:0]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO [31:2], Q[1:0]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_1_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[3:2]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_0 [31:2], Q[3:2]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_2_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[5:4]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_1 [31:2], Q[5:4]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_3_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[7:6]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_2 [31:2], Q[7:6]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_3_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_4_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[9:8]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_3 [31:2], Q[9:8]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_4_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_5_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[11:10]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_4 [31:2], Q[11:10]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_5_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_6_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[13:12]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_5 [31:2], Q[13:12]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_6_s .BLK_SEL_1=3'b000; +SDPB \fifo_inst/Equal.mem_Equal.mem_0_7_s ( + .CLKA(WrClk), + .CEA(\fifo_inst/n24_5 ), + .RESETA(GND), + .CLKB(RdClk), + .CEB(\fifo_inst/n28_3 ), + .RESETB(GND), + .OCE(GND), + .BLKSELA({GND, GND, GND}), + .BLKSELB({GND, GND, GND}), + .DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[15:14]}), + .ADA({\fifo_inst/Equal.wbin [12:0], GND}), + .ADB({\fifo_inst/rbin_num [12:0], GND}), + .DO({\fifo_inst/DO_6 [31:2], Q[15:14]}) +); +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .READ_MODE=1'b0; +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .BIT_WIDTH_0=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .BIT_WIDTH_1=2; +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .RESET_MODE="SYNC"; +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .BLK_SEL_0=3'b000; +defparam \fifo_inst/Equal.mem_Equal.mem_0_7_s .BLK_SEL_1=3'b000; +RAM16S4 \fifo_inst/Equal.rq1_wptr_0_s4 ( + .CLK(RdClk), + .WRE(VCC), + .AD({GND, GND, GND, \fifo_inst/Equal.rq1_wptr_0_5 }), + .DI({\fifo_inst/wptr [3:0]}), + .DO({\fifo_inst/Equal.rq2_wptr [3:0]})); +defparam \fifo_inst/Equal.rq1_wptr_0_s4 .INIT_0=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s4 .INIT_1=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s4 .INIT_2=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s4 .INIT_3=16'h0000; +RAM16S4 \fifo_inst/Equal.rq1_wptr_0_s6 ( + .CLK(RdClk), + .WRE(VCC), + .AD({GND, GND, GND, \fifo_inst/Equal.rq1_wptr_0_5 }), + .DI({\fifo_inst/wptr [7:4]}), + .DO({\fifo_inst/Equal.rq2_wptr [7:4]})); +defparam \fifo_inst/Equal.rq1_wptr_0_s6 .INIT_0=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s6 .INIT_1=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s6 .INIT_2=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s6 .INIT_3=16'h0000; +RAM16S4 \fifo_inst/Equal.rq1_wptr_0_s8 ( + .CLK(RdClk), + .WRE(VCC), + .AD({GND, GND, GND, \fifo_inst/Equal.rq1_wptr_0_5 }), + .DI({\fifo_inst/wptr [11:8]}), + .DO({\fifo_inst/Equal.rq2_wptr [11:8]})); +defparam \fifo_inst/Equal.rq1_wptr_0_s8 .INIT_0=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s8 .INIT_1=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s8 .INIT_2=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s8 .INIT_3=16'h0000; +RAM16S4 \fifo_inst/Equal.rq1_wptr_0_s10 ( + .CLK(RdClk), + .WRE(VCC), + .AD({GND, GND, GND, \fifo_inst/Equal.rq1_wptr_0_5 }), + .DI({GND, GND, \fifo_inst/wptr [13:12]}), + .DO({\fifo_inst/DO_7 [3:2], \fifo_inst/Equal.rq2_wptr [13:12]})); +defparam \fifo_inst/Equal.rq1_wptr_0_s10 .INIT_0=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s10 .INIT_1=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s10 .INIT_2=16'h0000; +defparam \fifo_inst/Equal.rq1_wptr_0_s10 .INIT_3=16'h0000; +ALU \fifo_inst/rcnt_sub_0_s ( + .I0(\fifo_inst/Equal.wcount_r_d [0]), + .I1(\fifo_inst/rbin_num [0]), + .I3(GND), + .CIN(VCC), + .COUT(\fifo_inst/rcnt_sub_0_3 ), + .SUM(\fifo_inst/rcnt_sub [0]) +); +defparam \fifo_inst/rcnt_sub_0_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_1_s ( + .I0(\fifo_inst/Equal.wcount_r_d [1]), + .I1(\fifo_inst/rbin_num [1]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_0_3 ), + .COUT(\fifo_inst/rcnt_sub_1_3 ), + .SUM(\fifo_inst/rcnt_sub [1]) +); +defparam \fifo_inst/rcnt_sub_1_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_2_s ( + .I0(\fifo_inst/Equal.wcount_r_d [2]), + .I1(\fifo_inst/rbin_num [2]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_1_3 ), + .COUT(\fifo_inst/rcnt_sub_2_3 ), + .SUM(\fifo_inst/rcnt_sub [2]) +); +defparam \fifo_inst/rcnt_sub_2_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_3_s ( + .I0(\fifo_inst/Equal.wcount_r_d [3]), + .I1(\fifo_inst/rbin_num [3]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_2_3 ), + .COUT(\fifo_inst/rcnt_sub_3_3 ), + .SUM(\fifo_inst/rcnt_sub [3]) +); +defparam \fifo_inst/rcnt_sub_3_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_4_s ( + .I0(\fifo_inst/Equal.wcount_r_d [4]), + .I1(\fifo_inst/rbin_num [4]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_3_3 ), + .COUT(\fifo_inst/rcnt_sub_4_3 ), + .SUM(\fifo_inst/rcnt_sub [4]) +); +defparam \fifo_inst/rcnt_sub_4_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_5_s ( + .I0(\fifo_inst/Equal.wcount_r_d [5]), + .I1(\fifo_inst/rbin_num [5]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_4_3 ), + .COUT(\fifo_inst/rcnt_sub_5_3 ), + .SUM(\fifo_inst/rcnt_sub [5]) +); +defparam \fifo_inst/rcnt_sub_5_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_6_s ( + .I0(\fifo_inst/Equal.wcount_r_d [6]), + .I1(\fifo_inst/rbin_num [6]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_5_3 ), + .COUT(\fifo_inst/rcnt_sub_6_3 ), + .SUM(\fifo_inst/rcnt_sub [6]) +); +defparam \fifo_inst/rcnt_sub_6_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_7_s ( + .I0(\fifo_inst/Equal.wcount_r_d [7]), + .I1(\fifo_inst/rbin_num [7]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_6_3 ), + .COUT(\fifo_inst/rcnt_sub_7_3 ), + .SUM(\fifo_inst/rcnt_sub [7]) +); +defparam \fifo_inst/rcnt_sub_7_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_8_s ( + .I0(\fifo_inst/Equal.wcount_r_d [8]), + .I1(\fifo_inst/rbin_num [8]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_7_3 ), + .COUT(\fifo_inst/rcnt_sub_8_3 ), + .SUM(\fifo_inst/rcnt_sub [8]) +); +defparam \fifo_inst/rcnt_sub_8_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_9_s ( + .I0(\fifo_inst/Equal.wcount_r_d [9]), + .I1(\fifo_inst/rbin_num [9]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_8_3 ), + .COUT(\fifo_inst/rcnt_sub_9_3 ), + .SUM(\fifo_inst/rcnt_sub [9]) +); +defparam \fifo_inst/rcnt_sub_9_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_10_s ( + .I0(\fifo_inst/Equal.wcount_r_d [10]), + .I1(\fifo_inst/rbin_num [10]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_9_3 ), + .COUT(\fifo_inst/rcnt_sub_10_3 ), + .SUM(\fifo_inst/rcnt_sub [10]) +); +defparam \fifo_inst/rcnt_sub_10_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_11_s ( + .I0(\fifo_inst/Equal.wcount_r_d [11]), + .I1(\fifo_inst/rbin_num [11]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_10_3 ), + .COUT(\fifo_inst/rcnt_sub_11_3 ), + .SUM(\fifo_inst/rcnt_sub [11]) +); +defparam \fifo_inst/rcnt_sub_11_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_12_s ( + .I0(\fifo_inst/Equal.wcount_r_d [12]), + .I1(\fifo_inst/rbin_num [12]), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_11_3 ), + .COUT(\fifo_inst/rcnt_sub_12_3 ), + .SUM(\fifo_inst/rcnt_sub [12]) +); +defparam \fifo_inst/rcnt_sub_12_s .ALU_MODE=1; +ALU \fifo_inst/rcnt_sub_13_s ( + .I0(\fifo_inst/n166_3 ), + .I1(GND), + .I3(GND), + .CIN(\fifo_inst/rcnt_sub_12_3 ), + .COUT(\fifo_inst/rcnt_sub_13_0_COUT ), + .SUM(\fifo_inst/rcnt_sub [13]) +); +defparam \fifo_inst/rcnt_sub_13_s .ALU_MODE=1; +ALU \fifo_inst/n106_s0 ( + .I0(\fifo_inst/wptr [0]), + .I1(\fifo_inst/rptr [0]), + .I3(GND), + .CIN(GND), + .COUT(\fifo_inst/n106_3 ), + .SUM(\fifo_inst/n106_1_SUM ) +); +defparam \fifo_inst/n106_s0 .ALU_MODE=3; +ALU \fifo_inst/n107_s0 ( + .I0(\fifo_inst/wptr [1]), + .I1(\fifo_inst/rptr [1]), + .I3(GND), + .CIN(\fifo_inst/n106_3 ), + .COUT(\fifo_inst/n107_3 ), + .SUM(\fifo_inst/n107_1_SUM ) +); +defparam \fifo_inst/n107_s0 .ALU_MODE=3; +ALU \fifo_inst/n108_s0 ( + .I0(\fifo_inst/wptr [2]), + .I1(\fifo_inst/rptr [2]), + .I3(GND), + .CIN(\fifo_inst/n107_3 ), + .COUT(\fifo_inst/n108_3 ), + .SUM(\fifo_inst/n108_1_SUM ) +); +defparam \fifo_inst/n108_s0 .ALU_MODE=3; +ALU \fifo_inst/n109_s0 ( + .I0(\fifo_inst/wptr [3]), + .I1(\fifo_inst/rptr [3]), + .I3(GND), + .CIN(\fifo_inst/n108_3 ), + .COUT(\fifo_inst/n109_3 ), + .SUM(\fifo_inst/n109_1_SUM ) +); +defparam \fifo_inst/n109_s0 .ALU_MODE=3; +ALU \fifo_inst/n110_s0 ( + .I0(\fifo_inst/wptr [4]), + .I1(\fifo_inst/rptr [4]), + .I3(GND), + .CIN(\fifo_inst/n109_3 ), + .COUT(\fifo_inst/n110_3 ), + .SUM(\fifo_inst/n110_1_SUM ) +); +defparam \fifo_inst/n110_s0 .ALU_MODE=3; +ALU \fifo_inst/n111_s0 ( + .I0(\fifo_inst/wptr [5]), + .I1(\fifo_inst/rptr [5]), + .I3(GND), + .CIN(\fifo_inst/n110_3 ), + .COUT(\fifo_inst/n111_3 ), + .SUM(\fifo_inst/n111_1_SUM ) +); +defparam \fifo_inst/n111_s0 .ALU_MODE=3; +ALU \fifo_inst/n112_s0 ( + .I0(\fifo_inst/wptr [6]), + .I1(\fifo_inst/rptr [6]), + .I3(GND), + .CIN(\fifo_inst/n111_3 ), + .COUT(\fifo_inst/n112_3 ), + .SUM(\fifo_inst/n112_1_SUM ) +); +defparam \fifo_inst/n112_s0 .ALU_MODE=3; +ALU \fifo_inst/n113_s0 ( + .I0(\fifo_inst/wptr [7]), + .I1(\fifo_inst/rptr [7]), + .I3(GND), + .CIN(\fifo_inst/n112_3 ), + .COUT(\fifo_inst/n113_3 ), + .SUM(\fifo_inst/n113_1_SUM ) +); +defparam \fifo_inst/n113_s0 .ALU_MODE=3; +ALU \fifo_inst/n114_s0 ( + .I0(\fifo_inst/wptr [8]), + .I1(\fifo_inst/rptr [8]), + .I3(GND), + .CIN(\fifo_inst/n113_3 ), + .COUT(\fifo_inst/n114_3 ), + .SUM(\fifo_inst/n114_1_SUM ) +); +defparam \fifo_inst/n114_s0 .ALU_MODE=3; +ALU \fifo_inst/n115_s0 ( + .I0(\fifo_inst/wptr [9]), + .I1(\fifo_inst/rptr [9]), + .I3(GND), + .CIN(\fifo_inst/n114_3 ), + .COUT(\fifo_inst/n115_3 ), + .SUM(\fifo_inst/n115_1_SUM ) +); +defparam \fifo_inst/n115_s0 .ALU_MODE=3; +ALU \fifo_inst/n116_s0 ( + .I0(\fifo_inst/wptr [10]), + .I1(\fifo_inst/rptr [10]), + .I3(GND), + .CIN(\fifo_inst/n115_3 ), + .COUT(\fifo_inst/n116_3 ), + .SUM(\fifo_inst/n116_1_SUM ) +); +defparam \fifo_inst/n116_s0 .ALU_MODE=3; +ALU \fifo_inst/n117_s0 ( + .I0(\fifo_inst/wptr [11]), + .I1(\fifo_inst/rptr [11]), + .I3(GND), + .CIN(\fifo_inst/n116_3 ), + .COUT(\fifo_inst/n117_3 ), + .SUM(\fifo_inst/n117_1_SUM ) +); +defparam \fifo_inst/n117_s0 .ALU_MODE=3; +ALU \fifo_inst/n118_s0 ( + .I0(\fifo_inst/wptr [12]), + .I1(\fifo_inst/rptr [12]), + .I3(GND), + .CIN(\fifo_inst/n117_3 ), + .COUT(\fifo_inst/n118_3 ), + .SUM(\fifo_inst/n118_1_SUM ) +); +defparam \fifo_inst/n118_s0 .ALU_MODE=3; +LUT1 \fifo_inst/Equal.rq1_wptr_0_s16 ( + .I0(\fifo_inst/Equal.rq1_wptr_0_5 ), + .F(\fifo_inst/Equal.rq1_wptr_0_20 ) +); +defparam \fifo_inst/Equal.rq1_wptr_0_s16 .INIT=2'h1; +endmodule diff --git a/hsdaoh_nano9k_test/hsdaoh_nano9k_test.cst b/hsdaoh_nano9k_test/hsdaoh_nano9k_test.cst new file mode 100644 index 0000000..1ed1317 --- /dev/null +++ b/hsdaoh_nano9k_test/hsdaoh_nano9k_test.cst @@ -0,0 +1,12 @@ +IO_LOC "sys_resetn" 4; +IO_PORT "sys_resetn" PULL_MODE=UP; +IO_LOC "sys_clk" 52; +IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP; +IO_LOC "tmds_d_p[0]" 71,70; +IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=8; +IO_LOC "tmds_d_p[1]" 73,72; +IO_PORT "tmds_d_p[1]" PULL_MODE=NONE DRIVE=8; +IO_LOC "tmds_d_p[2]" 75,74; +IO_PORT "tmds_d_p[2]" PULL_MODE=NONE DRIVE=8; +IO_LOC "tmds_clk_p" 69,68; +IO_PORT "tmds_clk_p" PULL_MODE=NONE DRIVE=8; diff --git a/hsdaoh_nano9k_test/hsdaoh_nano9k_test.sdc b/hsdaoh_nano9k_test/hsdaoh_nano9k_test.sdc new file mode 100644 index 0000000..b4e6de1 --- /dev/null +++ b/hsdaoh_nano9k_test/hsdaoh_nano9k_test.sdc @@ -0,0 +1 @@ +create_clock -name sys_clk -period 37.04 [get_ports {sys_clk}] -add diff --git a/hsdaoh_nano9k_test/top.v b/hsdaoh_nano9k_test/top.v new file mode 100644 index 0000000..8bd2d5e --- /dev/null +++ b/hsdaoh_nano9k_test/top.v @@ -0,0 +1,172 @@ +// hsdaoh - High Speed Data Acquisition over HDMI +// Test top design for Tang Nano 9K +// Copyright (C) 2024 by Steve Markgraf +// License: MIT + +module top ( + sys_clk, + sys_resetn, + tmds_clk_n, + tmds_clk_p, + tmds_d_n, + tmds_d_p +); + input sys_clk; + input sys_resetn; + output wire tmds_clk_n; + output wire tmds_clk_p; + output wire [2:0] tmds_d_n; + output wire [2:0] tmds_d_p; + + wire [2:0] tmds; + wire clk_pixel; + wire clk_pixel_x5; + wire hdmi_pll_lock; + + wire clk_data; + wire data_pll_lock; + + // https://juj.github.io/gowin_fpga_code_generators/pll_calculator.html + // 337.5 MHz, maximum that works with my nano 9K + // 337.5/5 = 67.5 MHz + localparam HDMI_PLL_IDIV = 1; + localparam HDMI_PLL_FBDIV = 24; + localparam HDMI_PLL_ODIV = 2; + + // PLL for HDMI clock + rPLL #( + .FCLKIN (27), + .IDIV_SEL (HDMI_PLL_IDIV), + .FBDIV_SEL (HDMI_PLL_FBDIV), + .ODIV_SEL (HDMI_PLL_ODIV), + .DEVICE ("GW1NR-9C") + ) hdmi_pll ( + .CLKIN(sys_clk), + .CLKFB(1'b0), + .RESET(1'b0), + .RESET_P(1'b0), + .FBDSEL(6'b0), + .IDSEL(6'b0), + .ODSEL(6'b0), + .DUTYDA(4'b0), + .PSDA(4'b0), + .FDLY(4'b0), + .CLKOUT(clk_pixel_x5), + .LOCK(hdmi_pll_lock), + .CLKOUTP(), + .CLKOUTD(), + .CLKOUTD3() + ); + + CLKDIV #( + .DIV_MODE(5), + .GSREN("false") + ) div_5 ( + .CLKOUT(clk_pixel), + .HCLKIN(clk_pixel_x5), + .RESETN(hdmi_pll_lock), + .CALIB(1'b0) + ); + + // 40.5 MHz (1/2/16) is maximum that works with 'open source' fifo + // 51 MHz (8/16/8) data clock (with proprietary, encrypted FIFO) + localparam DATA_PLL_IDIV = 8; + localparam DATA_PLL_FBDIV = 16; + localparam DATA_PLL_ODIV = 8; + + // PLL for data clock + rPLL #( + .FCLKIN (27), + .IDIV_SEL (DATA_PLL_IDIV), + .FBDIV_SEL (DATA_PLL_FBDIV), + .ODIV_SEL (DATA_PLL_ODIV), + .DEVICE ("GW1NR-9C") + ) data_pll ( + .CLKIN (sys_clk), + .CLKFB (1'b0), + .RESET (rst), + .RESET_P (1'b0), + .FBDSEL (6'b0), + .IDSEL (6'b0), + .ODSEL (6'b0), + .DUTYDA (4'b0), + .PSDA (4'b0), + .FDLY (4'b0), + .CLKOUT (clk_data), + .LOCK (data_pll_lock), + .CLKOUTP (), + .CLKOUTD (), + .CLKOUTD3 () + ); + + reg [15:0] counter = 16'h0000; + + reg [15:0] fifo_in; + + wire write_enable; + + wire [15:0] fifo_out; + wire fifo_empty; + wire fifo_aempty; + wire Full_o; + + wire FifoHalfFull; + wire FifoFull; + + wire fifo_rd_en_i; +/* + async_fifo #( + .DSIZE(16), + .ASIZE($clog2(8192*2)), // 3 + (1982 * 4) = 7931 => at least 8K entries to buffer 4 lines during VSYNC + .FALLTHROUGH("FALSE") + ) fifo ( + .wclk(clk_data), + .wrst_n(hdmi_pll_lock), + .winc(write_enable), + .wdata(fifo_in), + .wfull(FifoFull), + .awfull(FifoHalfFull), //fixme + .rclk(clk_pixel), + .rrst_n(hdmi_pll_lock), + .rinc(fifo_rd_en_i), + .rdata(fifo_out), + .rempty(fifo_empty), + .arempty(fifo_aempty) + ); +*/ + + FIFO_HS_Top fifo( + .Data(fifo_in), //input [0:0] Data + .WrClk(clk_data), //input WrClk + .RdClk(clk_pixel), //input RdClk + .WrEn(write_enable), //input WrEn + .RdEn(fifo_rd_en_i), //input RdEn + .Almost_Empty(fifo_aempty), //output Almost_Empty + .Q(fifo_out), //output [0:0] Q + .Empty(fifo_empty), //output Empty + .Full(FifoFull) //output Full + ); + + + hsdaoh_core hsdaoh ( + .rstn(hdmi_pll_lock), + .tmds_clk_n(tmds_clk_n), + .tmds_clk_p(tmds_clk_p), + .tmds_d_n(tmds_d_n), + .tmds_d_p(tmds_d_p), + .clk_pixel_x5(clk_pixel_x5), + .clk_pixel(clk_pixel), + .fifo_empty(fifo_empty), + .fifo_aempty(fifo_aempty), + .fifo_read_en(fifo_rd_en_i), + .data_in(fifo_out) + ); + + assign write_enable = 1'b1; + + always @(posedge clk_data) begin + fifo_in <= counter[15:0]; + counter <= counter + 1'b1; + end + +endmodule diff --git a/hsdaoh_primer20k_test.gprj b/hsdaoh_primer20k_test.gprj new file mode 100644 index 0000000..e7caa7f --- /dev/null +++ b/hsdaoh_primer20k_test.gprj @@ -0,0 +1,25 @@ + + + + + 5 + gw2a18c-011 + + + + + + + + + + + + + + + + + + + diff --git a/hsdaoh_primer20k_test/hsdaoh_primer20k_test.cst b/hsdaoh_primer20k_test/hsdaoh_primer20k_test.cst new file mode 100644 index 0000000..2369876 --- /dev/null +++ b/hsdaoh_primer20k_test/hsdaoh_primer20k_test.cst @@ -0,0 +1,13 @@ +IO_LOC "sys_resetn" T10; +IO_PORT "sys_resetn" IO_TYPE=LVCMOS33 PULL_MODE=UP; +IO_LOC "sys_clk" H11; +//IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP; +IO_PORT "sys_clk" PULL_MODE=UP; +IO_LOC "tmds_d_p[0]" H14,H16; +IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=8; +IO_LOC "tmds_d_p[1]" J15,K16; +IO_PORT "tmds_d_p[1]" PULL_MODE=NONE DRIVE=8; +IO_LOC "tmds_d_p[2]" K14,K15; +IO_PORT "tmds_d_p[2]" PULL_MODE=NONE DRIVE=8; +IO_LOC "tmds_clk_p" G16,H15; +IO_PORT "tmds_clk_p" PULL_MODE=NONE DRIVE=8; diff --git a/hsdaoh_primer20k_test/hsdaoh_primer20k_test.sdc b/hsdaoh_primer20k_test/hsdaoh_primer20k_test.sdc new file mode 100644 index 0000000..55afe1c --- /dev/null +++ b/hsdaoh_primer20k_test/hsdaoh_primer20k_test.sdc @@ -0,0 +1,2 @@ +create_clock -name sys_clk -period 37.04 [get_ports {sys_clk}] -add +//create_clock -name adc_clkout -period 12.3 [get_ports {adc_clkout}] -add \ No newline at end of file diff --git a/hsdaoh_primer20k_test/top.v b/hsdaoh_primer20k_test/top.v new file mode 100644 index 0000000..65c23c7 --- /dev/null +++ b/hsdaoh_primer20k_test/top.v @@ -0,0 +1,157 @@ +// hsdaoh - High Speed Data Acquisition over HDMI +// Test top design for Tang Primer 20K +// Copyright (C) 2024 by Steve Markgraf +// License: MIT + +module top ( + sys_clk, + sys_resetn, + enable, + tmds_clk_n, + tmds_clk_p, + tmds_d_n, + tmds_d_p +); + input sys_clk; + input sys_resetn; + input wire enable; + output wire tmds_clk_n; + output wire tmds_clk_p; + output wire [2:0] tmds_d_n; + output wire [2:0] tmds_d_p; + + wire [2:0] tmds; + wire clk_pixel; + wire clk_pixel_x5; + wire hdmi_pll_lock; + + wire clk_data; + wire data_pll_lock; + + // 477 MHz, maximum that works with the primer 20K + // 477/5 = 95.4 MHz + localparam HDMI_PLL_IDIV = 2; + localparam HDMI_PLL_FBDIV = 52; + localparam HDMI_PLL_ODIV = 2; + + // PLL for HDMI clock + rPLL #( + .FCLKIN (27), + .IDIV_SEL (HDMI_PLL_IDIV), + .FBDIV_SEL (HDMI_PLL_FBDIV), + .ODIV_SEL (HDMI_PLL_ODIV), + .DEVICE ("GW2A-18C") + ) hdmi_pll ( + .CLKIN(sys_clk), + .CLKFB(1'b0), + .RESET(1'b0), + .RESET_P(1'b0), + .FBDSEL(6'b0), + .IDSEL(6'b0), + .ODSEL(6'b0), + .DUTYDA(4'b0), + .PSDA(4'b0), + .FDLY(4'b0), + .CLKOUT(clk_pixel_x5), + .LOCK(hdmi_pll_lock), + .CLKOUTP(), + .CLKOUTD(), + .CLKOUTD3() + ); + + CLKDIV #( + .DIV_MODE(5), + .GSREN("false") + ) div_5 ( + .CLKOUT(clk_pixel), + .HCLKIN(clk_pixel_x5), + .RESETN(hdmi_pll_lock), + .CALIB(1'b0) + ); + + // 91.8 MHz clock for data + localparam DATA_PLL_IDIV = 4; + localparam DATA_PLL_FBDIV = 16; + localparam DATA_PLL_ODIV = 8; + + // PLL for data clock + rPLL #( + .FCLKIN (27), + .IDIV_SEL (DATA_PLL_IDIV), + .FBDIV_SEL (DATA_PLL_FBDIV), + .ODIV_SEL (DATA_PLL_ODIV), + .DEVICE ("GW2A-18C") + ) data_pll ( + .CLKIN (sys_clk), + .CLKFB (1'b0), + .RESET (rst), + .RESET_P (1'b0), + .FBDSEL (6'b0), + .IDSEL (6'b0), + .ODSEL (6'b0), + .DUTYDA (4'b0), + .PSDA (4'b0), + .FDLY (4'b0), + .CLKOUT (clk_data), + .LOCK (data_pll_lock), + .CLKOUTP (), + .CLKOUTD (), + .CLKOUTD3 () + ); + + reg [15:0] counter = 16'h0000; + + reg [15:0] fifo_in; + + wire write_enable; + + wire [15:0] fifo_out; + wire fifo_empty; + wire fifo_aempty; + wire Full_o; + + wire FifoHalfFull; + wire FifoFull; + + wire fifo_rd_en_i; + async_fifo #( + .DSIZE(16), + .ASIZE($clog2(16384)), // 3 + (1982 * 4) = 7931 => at least 8K entries to buffer 4 lines during VSYNC + .FALLTHROUGH("FALSE") + ) fifo ( + .wclk(clk_data), + .wrst_n(hdmi_pll_lock), + .winc(write_enable), + .wdata(fifo_in), + .wfull(FifoFull), + .awfull(FifoHalfFull), //fixme + .rclk(clk_pixel), + .rrst_n(hdmi_pll_lock), + .rinc(fifo_rd_en_i), + .rdata(fifo_out), + .rempty(fifo_empty), + .arempty(fifo_aempty) + ); + + hsdaoh_core hsdaoh ( + .rstn(hdmi_pll_lock), + .tmds_clk_n(tmds_clk_n), + .tmds_clk_p(tmds_clk_p), + .tmds_d_n(tmds_d_n), + .tmds_d_p(tmds_d_p), + .clk_pixel_x5(clk_pixel_x5), + .clk_pixel(clk_pixel), + .fifo_empty(fifo_empty), + .fifo_aempty(fifo_aempty), + .fifo_read_en(fifo_rd_en_i), + .data_in(fifo_out) + ); + + assign write_enable = 1'b1; + + always @(posedge clk_data) begin + fifo_in <= counter[15:0]; + counter <= counter + 1'b1; + end + +endmodule diff --git a/hsdaoh_primer25k_test.gprj b/hsdaoh_primer25k_test.gprj new file mode 100644 index 0000000..f37ca6a --- /dev/null +++ b/hsdaoh_primer25k_test.gprj @@ -0,0 +1,25 @@ + + + + + 5 + gw5a25a-002 + + + + + + + + + + + + + + + + + + + diff --git a/hsdaoh_primer25k_test/hsdaoh_primer25k_test.cst b/hsdaoh_primer25k_test/hsdaoh_primer25k_test.cst new file mode 100644 index 0000000..219b1d9 --- /dev/null +++ b/hsdaoh_primer25k_test/hsdaoh_primer25k_test.cst @@ -0,0 +1,15 @@ +IO_LOC "sys_resetn" H11; +IO_PORT "sys_resetn" IO_TYPE=LVCMOS33 PULL_MODE=DOWN DRIVE=OFF BANK_VCCIO=3.3; + +// middle PMOD connector for HDMI +IO_LOC "tmds_clk_p" L5,K5; +IO_PORT "tmds_clk_p" IO_TYPE=LVCMOS33D PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "tmds_d_p[0]" K11,L11; +IO_PORT "tmds_d_p[0]" IO_TYPE=LVCMOS33D PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "tmds_d_p[1]" E11,E10; +IO_PORT "tmds_d_p[1]" IO_TYPE=LVCMOS33D PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "tmds_d_p[2]" A11,A10; +IO_PORT "tmds_d_p[2]" IO_TYPE=LVCMOS33D PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3; + +IO_LOC "sys_clk" E2; +IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=OFF BANK_VCCIO=3.3; diff --git a/hsdaoh_primer25k_test/hsdaoh_primer25k_test.sdc b/hsdaoh_primer25k_test/hsdaoh_primer25k_test.sdc new file mode 100644 index 0000000..adee078 --- /dev/null +++ b/hsdaoh_primer25k_test/hsdaoh_primer25k_test.sdc @@ -0,0 +1 @@ +create_clock -name sys_clk -period 20 [get_ports {sys_clk}] -add \ No newline at end of file diff --git a/hsdaoh_primer25k_test/top.v b/hsdaoh_primer25k_test/top.v new file mode 100644 index 0000000..993ca9a --- /dev/null +++ b/hsdaoh_primer25k_test/top.v @@ -0,0 +1,195 @@ +// hsdaoh - High Speed Data Acquisition over HDMI +// Test top design for Tang Primer 25K +// Copyright (C) 2024 by Steve Markgraf +// License: MIT + +module top ( + sys_clk, + sys_resetn, + tmds_clk_n, + tmds_clk_p, + tmds_d_n, + tmds_d_p +); + input sys_clk; + input sys_resetn; + output wire tmds_clk_n; + output wire tmds_clk_p; + output wire [2:0] tmds_d_n; + output wire [2:0] tmds_d_p; + + wire [2:0] tmds; + wire clk_pixel; + wire clk_pixel_x5; + wire pll_lock; + + wire clk_data; + + // 475 MHz, maximum that works with the primer 25K + // 475/5 = 95 MHz + // Data PLL output is 89.0625 MHz + + PLLA #( + .FCLKIN ("50"), + .IDIV_SEL (2), + .FBDIV_SEL (1), + .CLKFB_SEL ("INTERNAL"), + .ODIV0_SEL (3), + .ODIV0_FRAC_SEL (0), + .ODIV1_SEL (16), + .ODIV2_SEL (8), + .ODIV3_SEL (8), + .ODIV4_SEL (8), + .ODIV5_SEL (8), + .ODIV6_SEL (8), + .MDIV_SEL (57), + .MDIV_FRAC_SEL (0), + .CLKOUT0_EN ("TRUE"), + .CLKOUT1_EN ("TRUE"), + .CLKOUT2_EN ("FALSE"), + .CLKOUT3_EN ("FALSE"), + .CLKOUT4_EN ("FALSE"), + .CLKOUT5_EN ("FALSE"), + .CLKOUT6_EN ("FALSE"), + .CLKOUT0_DT_DIR (1'b1), + .CLKOUT0_DT_DIR (1'b1), + .CLKOUT1_DT_DIR (1'b1), + .CLKOUT2_DT_DIR (1'b1), + .CLKOUT3_DT_DIR (1'b1), + .CLK0_IN_SEL (1'b0), + .CLK0_OUT_SEL (1'b0), + .CLK1_IN_SEL (1'b0), + .CLK1_OUT_SEL (1'b0), + .CLK2_IN_SEL (1'b0), + .CLK2_OUT_SEL (1'b0), + .CLK3_IN_SEL (1'b0), + .CLK3_OUT_SEL (1'b0), + .CLK4_IN_SEL (2'b00), + .CLK4_OUT_SEL (1'b0), + .CLK5_IN_SEL (1'b0), + .CLK5_OUT_SEL (1'b0), + .CLK6_IN_SEL (1'b0), + .CLK6_OUT_SEL (1'b0), + .CLKOUT0_PE_COARSE (0), + .CLKOUT0_PE_FINE (0), + .CLKOUT1_PE_COARSE (0), + .CLKOUT1_PE_FINE (0), + .CLKOUT2_PE_COARSE (0), + .CLKOUT2_PE_FINE (0), + .CLKOUT3_PE_COARSE (0), + .CLKOUT3_PE_FINE (0), + .CLKOUT4_PE_COARSE (0), + .CLKOUT4_PE_FINE (0), + .CLKOUT5_PE_COARSE (0), + .CLKOUT5_PE_FINE (0), + .CLKOUT6_PE_COARSE (0), + .CLKOUT6_PE_FINE (0), + .DE0_EN ("FALSE"), + .DE1_EN ("FALSE"), + .DE2_EN ("FALSE"), + .DE3_EN ("FALSE"), + .DE4_EN ("FALSE"), + .DE5_EN ("FALSE"), + .DE6_EN ("FALSE"), + .DYN_DPA_EN ("FALSE"), + .DYN_PE0_SEL ("FALSE"), + .DYN_PE1_SEL ("FALSE"), + .DYN_PE2_SEL ("FALSE"), + .DYN_PE3_SEL ("FALSE"), + .DYN_PE4_SEL ("FALSE"), + .DYN_PE5_SEL ("FALSE"), + .DYN_PE6_SEL ("FALSE"), + .RESET_I_EN ("FALSE"), + .RESET_O_EN ("FALSE"), + .ICP_SEL (6'bXXXXXX), + .LPF_RES (3'bXXX), + .LPF_CAP (2'b00), + .SSC_EN ("FALSE"), + .CLKOUT0_DT_STEP (0), + .CLKOUT1_DT_STEP (0), + .CLKOUT2_DT_STEP (0), + .CLKOUT3_DT_STEP (0) + ) pll ( + .LOCK(pll_lock), + .CLKOUT0(clk_pixel_x5), + .CLKOUT1(clk_data), + .CLKIN(sys_clk), + .CLKFB(1'b0), + .RESET(1'b0), + .PLLPWD(1'b0), + .RESET_I(1'b0), + .RESET_O(1'b0), + .PSSEL(3'b0), + .PSDIR(1'b0), + .PSPULSE(1'b0), + .SSCPOL(1'b0), + .SSCON(1'b0), + .SSCMDSEL(7'b0), + .SSCMDSEL_FRAC(3'b0), + .MDCLK(1'b0), + .MDOPC(2'b0), + .MDAINC(1'b0), + .MDWDI(8'b0) + ); + + CLKDIV #( + .DIV_MODE(5) + ) div_5 ( + .CLKOUT(clk_pixel), + .HCLKIN(clk_pixel_x5), + .RESETN(1'b1), + .CALIB(1'b0) + ); + + reg [15:0] counter = 16'h0000; + reg [15:0] fifo_in; + wire write_enable; + wire [15:0] fifo_out; + wire fifo_empty; + wire fifo_aempty; + wire Full_o; + + wire FifoHalfFull; + wire FifoFull; + + wire fifo_rd_en_i; + async_fifo #( + .DSIZE(16), + .ASIZE($clog2(16384)), // 3 + (1982 * 4) = 7931 => at least 8K entries to buffer 4 lines during VSYNC + .FALLTHROUGH("FALSE") + ) fifo ( + .wclk(clk_data), + .wrst_n(pll_lock), + .winc(write_enable), + .wdata(fifo_in), + .wfull(FifoFull), + .awfull(FifoHalfFull), + .rclk(clk_pixel), + .rrst_n(pll_lock), + .rinc(fifo_rd_en_i), + .rdata(fifo_out), + .rempty(fifo_empty), + .arempty(fifo_aempty) + ); + + hsdaoh_core hsdaoh ( + .rstn(pll_lock), + .tmds_clk_n(tmds_clk_n), + .tmds_clk_p(tmds_clk_p), + .tmds_d_n(tmds_d_n), + .tmds_d_p(tmds_d_p), + .clk_pixel_x5(clk_pixel_x5), + .clk_pixel(clk_pixel), + .fifo_empty(fifo_empty), + .fifo_aempty(fifo_aempty), + .fifo_read_en(fifo_rd_en_i), + .data_in(fifo_out) + ); + + assign write_enable = 1'b1; + + always @(posedge clk_data) begin + fifo_in <= counter[15:0]; + counter <= counter + 1'b1; + end +endmodule