16140fd383
This FW for the New Packet Radio project was taken from the Hackaday project https://hackaday.io/project/164092-npr-new-packet-radio The source code is original without any modifications, ver. 2020_06_29.
246 lines
No EOL
8.8 KiB
C++
246 lines
No EOL
8.8 KiB
C++
// This file is part of "NPR70 modem firmware" software
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// (A GMSK data modem for ham radio 430-440MHz, at several hundreds of kbps)
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// Copyright (c) 2017-2020 Guillaume F. F4HDK (amateur radio callsign)
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//
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// "NPR70 modem firmware" is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// "NPR70 modem firmware" is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with "NPR70 modem firmware". If not, see <http://www.gnu.org/licenses/>
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#ifdef EXT_SRAM_USAGE
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#include "mbed.h"
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#include "global_variables.h"
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#include "ext_SRAM2.h"
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static unsigned char trash[350];
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static unsigned short int extSRAM_FIFOs[8][94];// 8 FIFO of pointers to extSRAM
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static unsigned char extSRAM_filling[374];// 0 : empty frame slot; 1: occupied frame slot
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static int extSRAM_total_filling = 0;
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static unsigned char extSRAM_pkt_timer[374];// timer of each frame
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static unsigned short int extSRAM_pkt_size[374];// size of each frame
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static unsigned char extSRAM_FIFO_index_read[8];//Read pointers of FIFO
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static unsigned char extSRAM_FIFO_index_write[8];//write pointers of FIFO
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static unsigned char extSRAM_FIFO_filling[8];
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void ext_SRAM_init(void) {
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int i;
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int j;
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for (i=0; i<8; i++) {
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extSRAM_FIFO_index_read[i] = 0;
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extSRAM_FIFO_index_write[i] = 0;
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extSRAM_FIFO_filling[i] = 0;
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}
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extSRAM_total_filling = 0;
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}
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void ext_SRAM_set_mode(ext_SRAM_chip* loc_SPI) {
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static unsigned char command[6] = {0x01, 0x40, 0x00, 0x00};
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loc_SPI->cs->write(0);
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loc_SPI->spi_port->transfer_2 (command, 2, trash, 2);
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loc_SPI->cs->write(1);
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}
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/*
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void ext_SRAM_read2(ext_SRAM_chip* loc_SPI, unsigned char* loc_data, unsigned int address, int size) {
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static unsigned char command[6] = {0x03, 0x00, 0x00, 0x00};
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loc_SPI->cs->write(0);
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command[3] = address & 0xFF;
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command[2] = (address & 0xFF00) >> 8;
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command[1] = (address & 0xFF0000) >> 16;
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loc_SPI->spi_port->transfer_2 (command, 4, trash, 4);
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loc_SPI->spi_port->transfer_2 (trash, size, loc_data, size);
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loc_SPI->cs->write(1);
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}
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*/
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void ext_SRAM_write(ext_SRAM_chip* loc_SPI, unsigned char* loc_data, unsigned int address, int size) {
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//static unsigned char trash[350];
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static unsigned char command[6] = {0x02, 0x00, 0x00, 0x00};
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loc_SPI->cs->write(0);
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command[3] = address & 0xFF;
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command[2] = (address & 0xFF00) >> 8;
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command[1] = (address & 0xFF0000) >> 16;
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loc_SPI->spi_port->transfer_2 (command, 4, trash, 4);
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loc_SPI->spi_port->transfer_2 (loc_data, size, trash, size);
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loc_SPI->cs->write(1);
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}
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int extSRAM_testfreespace(int pkt_nb, unsigned char FIFO_index) {
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int freespace_available = 1;
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if ( (extSRAM_FIFO_filling[FIFO_index] + pkt_nb) > 94 ) {
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freespace_available = 0;
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}
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if ( (extSRAM_total_filling + pkt_nb) > 374 ) {
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freespace_available = 0;
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}
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return freespace_available;
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}
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void extSRAM_push(unsigned char* raw_data, int size, unsigned char FIFO_nb) {
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unsigned short int i;
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unsigned short int free_slot = 0xFFFF;
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for (i=0; i<350; i++) {
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if (extSRAM_filling[i] == 0) {
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free_slot = i;
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}
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}
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if (free_slot != 0xFFFF) {
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extSRAM_filling[free_slot] = 1;
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extSRAM_FIFOs[FIFO_nb][extSRAM_FIFO_index_write[FIFO_nb]] = free_slot;
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extSRAM_FIFO_index_write[FIFO_nb] ++;
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if (extSRAM_FIFO_index_write[FIFO_nb] > 93) {
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extSRAM_FIFO_index_write[FIFO_nb] = 0;
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}
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extSRAM_total_filling ++;
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extSRAM_FIFO_filling[FIFO_nb]++;
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extSRAM_pkt_timer[free_slot] = raw_data[0];
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extSRAM_pkt_size[free_slot] = size;
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ext_SRAM_write (SPI_SRAM_p, raw_data, free_slot*350, size);
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} else {
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printf("ERROR extSRAM push\r\n");
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}
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}
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void TXPS_FIFO_fill(unsigned char* loc_data, int size) {
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int size_to_write;
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if ( ( (TXPS_FIFO->WR_point & TXPS_FIFO->mask) + size) > TXPS_FIFO->mask) { // to big for 1 step
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size_to_write = (TXPS_FIFO->mask + 1 - (TXPS_FIFO->WR_point & TXPS_FIFO->mask) );
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//G_SI4463->spi->transfer_2 (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), size_to_write, SI_trash, size_to_write);
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memcpy (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), loc_data, size_to_write);
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TXPS_FIFO->WR_point = TXPS_FIFO->WR_point + size_to_write; // should become ZERO
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//second step
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size_to_write = size - size_to_write;
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//G_SI4463->spi->transfer_2 (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), size_to_write, SI_trash, size_to_write);
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memcpy (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), loc_data, size_to_write);
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TXPS_FIFO->WR_point = TXPS_FIFO->WR_point + size_to_write;
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TXPS_FIFO->last_ready = TXPS_FIFO->WR_point;
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} else { //1 step is enough
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//G_SI4463->spi->transfer_2 (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), size, SI_trash, size);
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memcpy (TXPS_FIFO->data + (TXPS_FIFO->WR_point & TXPS_FIFO->mask), loc_data, size);
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TXPS_FIFO->WR_point = TXPS_FIFO->WR_point + size;
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TXPS_FIFO->last_ready = TXPS_FIFO->WR_point;
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}
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}
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/*
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void ext_SRAM_periodic_call(void) {
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int intern_FIFO_filling;
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int ext_FIFO_filling;
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intern_FIFO_filling = TX_buff_intern_WR_pointer - TX_buff_intern_RD_pointer;
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ext_FIFO_filling = TX_buff_ext_WR_pointer - TX_buff_ext_RD_pointer;
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while ( (ext_FIFO_filling > 0) && (intern_FIFO_filling <= 9) ) {
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ext_SRAM_read(SPI_SRAM_p, TX_buff_intern_FIFOdata[TX_buff_intern_WR_pointer % 128], TX_buff_ext_RD_pointer*128, 128);
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TX_buff_ext_RD_pointer++;
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TX_buff_intern_WR_pointer++;
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TX_buff_intern_last_ready = TX_buff_intern_WR_pointer;
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}
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}
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*/
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/*
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void ext_SRAM_periodic_call() {
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static unsigned char current_buff;
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unsigned char radio_pckt[360];
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unsigned char nb_buffer_treated = 0;
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unsigned char frame_datation;
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unsigned char loc_time_char;
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unsigned int loc_time_int;
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unsigned short int extSRAM_pointer;
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int one_packet_ok = 0;
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int switch_to_next_buff = 0;
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int fifo_full;
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int frame_size;
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nb_buffer_treated = 0;
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loc_time_int = GLOBAL_timer.read_us();
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loc_time_char = (loc_time_int >> 16) & 0xFF;
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//condition a rajouter sur buffer interne TXPS
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if ((TXPS_FIFO->last_ready - TXPS_FIFO->RD_point) < 3740 ) { //16380 - 350 ; 3740
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fifo_full = 0;
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} else {
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fifo_full = 1;
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}
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//printf("FIFO full : %i\r\n", fifo_full);
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while ( (nb_buffer_treated<8) && (one_packet_ok==0) && (fifo_full == 0) ) {//loop over all buffers
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switch_to_next_buff = 0;
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if (extSRAM_FIFO_filling[current_buff] > 0) {//data available in current buffer
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extSRAM_pointer = extSRAM_FIFOs[current_buff][extSRAM_FIFO_index_read[current_buff]];
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frame_datation = extSRAM_pkt_timer[extSRAM_pointer];
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//frame_size = extSRAM_pkt_size[extSRAM_pointer] + 2 + SI4463_offset_size;
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frame_size = extSRAM_pkt_size[extSRAM_pointer];
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if ( (loc_time_char - frame_datation) < CONF_Tx_rframe_timeout) {//frame ok
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//printf("frame OK ext SRAM\r\n");
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ext_SRAM_read (SPI_SRAM_p, radio_pckt, extSRAM_pointer*350, frame_size);
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radio_pckt[1] = frame_size - 2 - SI4463_offset_size;//-2
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TXPS_FIFO_fill (radio_pckt, frame_size);
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switch_to_next_buff = 1;
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one_packet_ok = 1;
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} else {//old frame
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switch_to_next_buff = 0;
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}
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extSRAM_filling[extSRAM_pointer] = 0;
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extSRAM_FIFO_index_read[current_buff]++;
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if (extSRAM_FIFO_index_read[current_buff] > 93) {
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extSRAM_FIFO_index_read[current_buff] = 0;
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}
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extSRAM_FIFO_filling[current_buff]--;
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extSRAM_total_filling--;
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}
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else {//no data in the current buffer
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switch_to_next_buff = 1;
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}
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if (switch_to_next_buff == 1) {
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current_buff++;
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if (current_buff>7) {current_buff = 0;}
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nb_buffer_treated++;
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}
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}
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}
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*/
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void ext_SRAM_test(ext_SRAM_chip* loc_SPI) {
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unsigned char test_table[400] = "bonjour!!";
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unsigned char test_table2[400];
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unsigned long int timer1;
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unsigned long int timer2;
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unsigned int loc_address;
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int i, j;
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printf("\r\nsram test begin\r\n");
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//loc_SPI->cs->write(1);
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for (i=0; i<5000; i++) {
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loc_address = 16 * i;
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//wait_ms(1);
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sprintf ((char*)test_table, "jourbon %i", i);
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ext_SRAM_write(loc_SPI, test_table, loc_address, 20);
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printf("write %i\r\n", i);
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}
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for (i=0; i<5000; i++) {
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loc_address = 16 * i;
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for (j=0; j<30; j++) {
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test_table2[j] = 0;
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}
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//wait_ms(1);
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ext_SRAM_read2(loc_SPI, test_table2, loc_address, 20);
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test_table2[12] = 0;
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printf ("read addr %i content '%s' \r\n", loc_address, test_table2);
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}
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timer1 = GLOBAL_timer.read_us();
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for (i=0; i<10; i++) {
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memcpy(test_table2+i, test_table+i, 350);
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}
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timer2 = GLOBAL_timer.read_us();
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printf("temps memcpy 350 %i\r\n", timer2-timer1);
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}
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#endif |