Changed PCB stackup from 2 to 4 layers

This commit is contained in:
Vlastimil Slinták 2025-07-13 22:05:01 +02:00 committed by Wojciech Kaczmarski
parent 18195bee4c
commit 92ac59d905
2 changed files with 69 additions and 2 deletions

View file

@ -9,6 +9,8 @@
(paper "A4")
(layers
(0 "F.Cu" signal)
(4 "In1.Cu" signal)
(6 "In2.Cu" signal)
(2 "B.Cu" signal)
(9 "F.Adhes" user "F.Adhesive")
(11 "B.Adhes" user "B.Adhesive")
@ -34,6 +36,67 @@
(45 "User.4" user)
)
(setup
(stackup
(layer "F.SilkS"
(type "Top Silk Screen")
)
(layer "F.Paste"
(type "Top Solder Paste")
)
(layer "F.Mask"
(type "Top Solder Mask")
(thickness 0.01)
)
(layer "F.Cu"
(type "copper")
(thickness 0.035)
)
(layer "dielectric 1"
(type "prepreg")
(thickness 0.1)
(material "FR4")
(epsilon_r 4.5)
(loss_tangent 0.02)
)
(layer "In1.Cu"
(type "copper")
(thickness 0.035)
)
(layer "dielectric 2"
(type "core")
(thickness 1.24)
(material "FR4")
(epsilon_r 4.5)
(loss_tangent 0.02)
)
(layer "In2.Cu"
(type "copper")
(thickness 0.035)
)
(layer "dielectric 3"
(type "prepreg")
(thickness 0.1)
(material "FR4")
(epsilon_r 4.5)
(loss_tangent 0.02)
)
(layer "B.Cu"
(type "copper")
(thickness 0.035)
)
(layer "B.Mask"
(type "Bottom Solder Mask")
(thickness 0.01)
)
(layer "B.Paste"
(type "Bottom Solder Paste")
)
(layer "B.SilkS"
(type "Bottom Silk Screen")
)
(copper_finish "None")
(dielectric_constraints no)
)
(pad_to_mask_clearance 0)
(allow_soldermask_bridges_in_footprints no)
(tenting front back)
@ -200145,7 +200208,7 @@
(extension_offset 0.5)
(keep_text_aligned yes)
)
(gr_text "45,5"
(gr_text "45.5"
(at 122.75 153.85 0)
(layer "User.1")
(uuid "304f2af6-c48a-4d09-9874-a225aa208bd4")

View file

@ -72,6 +72,8 @@
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],
"col_order": [
@ -84,7 +86,9 @@
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],
"col_widths": [
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