forked from mirror/openwrt
775d903216
The RTL9300 has a broken R4K MIPS timer interrupt, however, the R4K clocksource works. We replace the RTL9300 timer with a Clock Event Timer (CEVT), which is VSMP aware and can be instantiated as part of brining a VSMTP cpu up instead of the R4K CEVT source. For this we place the RTL9300 CEVT timer in arch/mips/kernel together with other MIPS CEVT timers, initialize the SoC IRQs from a modified smp-mt.c and instantiate each timer as part of the MIPS time setup in arch/mips/include/asm/time.h instead of the R4K CEVT, similarly as is done by other MIPS CEVT timers. Signed-off-by: Birger Koblitz <git@birger-koblitz.de> |
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| .. | ||
| base-files | ||
| dts-5.10 | ||
| files/firmware/rtl838x_phy | ||
| files-5.10 | ||
| image | ||
| patches-5.10 | ||
| profiles | ||
| rtl838x | ||
| rtl839x | ||
| Makefile | ||