forked from mirror/openwrt
76f7dd3312
The native bus address for UART was entered for rt305x UART_BASE, but the bootloaders have memory space remapped with the same virtual memory map the kernel uses for program addressing at boot time. In UBoot, the remapped address is often defined as TEXT_BASE. In the kernel, for rt305x this remapped address is RT305X_SYSC_BASE. (arch/mips/include/asm/mach-ralink/rt305x.h) Because the ralink I/O busses begin at a low address of 0x10000000, they are remapped using KSEG0 or KSEG1, which for all 32-bit MIPS SOCs (arch/mips/include/asm/addrspace.h) are offsets of 0x80000000 and 0xa0000000 respectively. This is consistent with the other UART_BASE macros here and with MIPS memory map documentation. Before the recent rework of the lzma-loader for ramips, the original board-$(PLATFORM).c files also did not use KSEG1ADDR for UART_BASE despite being defined, which made this mistake easier to occur. Fix this by defining KSEG1ADDR again and actually use it. Copy and paste from the kernel's macros for consistency. Link: https://training.mips.com/basic_mips/PDF/Memory_Map.pdf Fixes: |
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| .. | ||
| base-files/etc | ||
| dts | ||
| files/drivers | ||
| image | ||
| mt76x8 | ||
| mt7620 | ||
| mt7621 | ||
| patches-5.15 | ||
| rt288x | ||
| rt305x | ||
| rt3883 | ||
| Makefile | ||
| modules.mk | ||