forked from mirror/openwrt
673b48a674
Add a patch fixing a bunch of missing prototype errors, scattered all over the tree. Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
116 lines
3.4 KiB
Diff
116 lines
3.4 KiB
Diff
--- a/arch/mips/cavium-octeon/octeon-platform.c
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+++ b/arch/mips/cavium-octeon/octeon-platform.c
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@@ -15,6 +15,7 @@
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#include <linux/libfdt.h>
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#include <asm/octeon/octeon.h>
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+#include <asm/octeon/octeon-platform.h>
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#include <asm/octeon/cvmx-helper-board.h>
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#ifdef CONFIG_USB
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--- a/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
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+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
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@@ -34,6 +34,7 @@
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#include <asm/octeon/octeon.h>
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+#include <asm/octeon/cvmx-interrupt-decodes.h>
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#include <asm/octeon/cvmx-gmxx-defs.h>
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#include <asm/octeon/cvmx-pcsx-defs.h>
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#include <asm/octeon/cvmx-pcsxx-defs.h>
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--- a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
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+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
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@@ -39,6 +39,8 @@
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#include <asm/octeon/cvmx-helper-jtag.h>
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+#include <asm/octeon/cvmx-helper-errata.h>
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+
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/**
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* Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
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* 1 doesn't work properly. The following code disables 2nd order
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--- a/arch/mips/cavium-octeon/smp.c
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+++ b/arch/mips/cavium-octeon/smp.c
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@@ -92,6 +92,8 @@ static irqreturn_t mailbox_interrupt(int
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return IRQ_HANDLED;
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}
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+void octeon_send_ipi_single(int cpu, unsigned int action);
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+
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/*
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* Cause the function described by call_data to be executed on the passed
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* cpu. When the function has finished, increment the finished field of
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--- a/arch/mips/mm/c-octeon.c
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+++ b/arch/mips/mm/c-octeon.c
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@@ -16,6 +16,7 @@
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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+#include <asm/c-octeon.h>
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#include <asm/cacheops.h>
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#include <asm/cpu-features.h>
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#include <asm/cpu-type.h>
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--- /dev/null
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+++ b/arch/mips/include/asm/c-octeon.h
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@@ -0,0 +1,9 @@
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+#ifndef __C_OCTEON_H__
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+#define __C_OCTEON_H__
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+
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+extern int register_co_cache_error_notifier(struct notifier_block *nb);
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+extern int unregister_co_cache_error_notifier(struct notifier_block *nb);
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+extern void cache_parity_error_octeon_recoverable(void);
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+extern void cache_parity_error_octeon_non_recoverable(void);
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+
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+#endif
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--- /dev/null
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+++ b/drivers/watchdog/octeon-wdt-main.h
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@@ -0,0 +1,5 @@
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+#ifdef CONFIG_OCTEON_WDT
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+
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+extern void octeon_wdt_nmi_stage3(u64 reg[32]);
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+
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+#endif
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--- a/drivers/watchdog/octeon-wdt-main.c
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+++ b/drivers/watchdog/octeon-wdt-main.c
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@@ -64,6 +64,8 @@
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#include <asm/octeon/cvmx-ciu2-defs.h>
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#include <asm/octeon/cvmx-rst-defs.h>
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+#include "octeon-wdt-main.h"
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+
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/* Watchdog interrupt major block number (8 MSBs of intsn) */
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#define WD_BLOCK_NUMBER 0x01
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--- a/arch/mips/include/asm/octeon/pci-octeon.h
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+++ b/arch/mips/include/asm/octeon/pci-octeon.h
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@@ -24,6 +24,12 @@
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*/
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#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
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+extern int octeon_pci_pcibios_map_irq(const struct pci_dev *dev, u8 slot,
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+ u8 pin);
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+
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+extern int octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, u8 slot,
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+ u8 pin);
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+
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/*
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* pcibios_map_irq() is defined inside pci-octeon.c. All it does is
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* call the Octeon specific version pointed to by this variable. This
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--- /dev/null
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+++ b/arch/mips/include/asm/octeon/cvmx-interrupt-decodes.h
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@@ -0,0 +1,6 @@
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+#ifndef __CVMX_INTERRUPT_DECODES_H__
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+#define __CVMX_INTERRUPT_DECODES_H__
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+
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+extern void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block);
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+
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+#endif
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--- /dev/null
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+++ b/arch/mips/include/asm/octeon/octeon-platform.h
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@@ -0,0 +1,6 @@
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+#ifndef __OCTEON_PLATFORM_H__
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+#define __OCTEON_PLATFORM_H__
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+
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+extern void octeon_fill_mac_addresses(void);
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+
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+#endif
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