forked from mirror/openwrt
a626b7e74d
There are two spi drivers for en7523/an7581/an7583: * en7581-snand (spi-airoha-snfi.c) * en7523-spi (spi-en7523.c) The first one supports DMA, but until recently it has several nasty issues. The second do things properly but does not support DMA. Recently the first driver was greatly improved, so there is no sence keep both drivers anymore. This patch removes en7523-spi driver and use DMA capable driver instead. Unfortunately there is a nasty en7523 specific issue. We found that some serial console may pull TX line to GROUND during board boot time. Airoha uses TX line as one of it's BOOT pins. This will lead to booting in RESERVED boot mode. It was found that some flashes operates incorrectly in RESERVED mode if DMA used. This patch also adds a hack that turns off DMA and prints big fat warning if booting in reserved mode was detected. This slow down flash operations but does not kill your data. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Link: https://github.com/openwrt/openwrt/pull/20365 Signed-off-by: Robert Marko <robimarko@gmail.com>
226 lines
4.8 KiB
Text
226 lines
4.8 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/en7523-clk.h>
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#include <dt-bindings/reset/airoha,en7523-reset.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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npu_binary@84000000 {
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no-map;
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reg = <0x84000000 0xA00000>;
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};
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npu_flag@84B0000 {
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no-map;
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reg = <0x84B00000 0x100000>;
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};
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npu_pkt@85000000 {
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no-map;
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reg = <0x85000000 0x1A00000>;
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};
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npu_phyaddr@86B00000 {
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no-map;
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reg = <0x86B00000 0x100000>;
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};
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npu_rxdesc@86D00000 {
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no-map;
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reg = <0x86D00000 0x100000>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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clock-frequency = <80000000>;
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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clock-frequency = <80000000>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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scu: system-controller@1fa20000 {
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compatible = "airoha,en7523-scu";
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reg = <0x1fa20000 0x400>,
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<0x1fb00000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gic: interrupt-controller@9000000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x09000000 0x20000>,
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<0x09080000 0x80000>,
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<0x09400000 0x2000>,
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<0x09500000 0x2000>,
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<0x09600000 0x20000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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uart1: serial@1fbf0000 {
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compatible = "ns16550";
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reg = <0x1fbf0000 0x30>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <1843200>;
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status = "okay";
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};
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gpio0: gpio@1fbf0200 {
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compatible = "airoha,en7523-gpio";
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reg = <0x1fbf0204 0x4>,
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<0x1fbf0200 0x4>,
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<0x1fbf0220 0x4>,
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<0x1fbf0214 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@1fbf0270 {
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compatible = "airoha,en7523-gpio";
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reg = <0x1fbf0270 0x4>,
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<0x1fbf0260 0x4>,
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<0x1fbf0264 0x4>,
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<0x1fbf0278 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pcie0: pcie@1fa91000 {
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compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
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device_type = "pci";
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reg = <0x1fa91000 0x1000>;
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reg-names = "port0";
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie_irq";
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clocks = <&scu EN7523_CLK_PCIE>;
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clock-names = "sys_ck0";
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x20000000 0 0x2000000>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pcie1: pcie@1fa92000 {
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compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
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device_type = "pci";
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reg = <0x1fa92000 0x1000>;
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reg-names = "port1";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie_irq";
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clocks = <&scu EN7523_CLK_PCIE>;
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clock-names = "sys_ck1";
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x22000000 0x22000000 0 0x2000000>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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spi_ctrl: spi_controller@1fa10000 {
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compatible = "airoha,en7523-snand";
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reg = <0x1fa10000 0x140>,
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<0x1fa11000 0x160>;
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clocks = <&scu EN7523_CLK_SPI>;
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clock-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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nand: nand@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <2>;
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};
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};
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};
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