forked from mirror/openwrt
fe27cce1ec
Until now the the SerDes configuration is realized with helper functions
scattered around the DSA and PHY driver. Give them a new home as a PCS
driver.
The target design is as follows:
- dsa driver manages switch
- pcs driver manages SerDes on high level (this commit)
- mdio driver manages SerDes on low level
This driver adds the high level SerDes access via PCS. It makes use of
the low level mdio SerDes driver to access the registers.
Remark: This initial version provides exactly all phylink_pcs_ops that
are currently part of the DSA driver. So this can be swapped in one of
the next commits as a drop in replacement. To make use of it something
like this is needed:
...
ports = of_get_child_by_name(node, "ethernet-ports");
if (!ports)
return -EINVAL;
for_each_available_child_of_node(ports, port) {
pcs_node = of_parse_phandle(port, "pcs-handle", 0);
of_property_read_u32(port, "reg", &port_nr)) {
priv->pcs[port_nr] = rtpcs_create(dev, pcs_node, port_nr);
}
...
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20075
Signed-off-by: Robert Marko <robimarko@gmail.com>
380 lines
7.3 KiB
Text
380 lines
7.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "macros.dtsi"
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#include <dt-bindings/clock/rtl83xx-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "realtek,rtl838x-soc";
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osc: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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ccu: clock-controller {
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compatible = "realtek,rtl8380-clock";
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#clock-cells = <1>;
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clocks = <&osc>;
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clock-names = "ref_clk";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips4KEc";
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reg = <0>;
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clocks = <&ccu CLK_CPU>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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};
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cpu_opp_table: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <325000000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <350000000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <375000000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <400000000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <425000000>;
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};
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opp05 {
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opp-hz = /bits/ 64 <450000000>;
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};
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opp06 {
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opp-hz = /bits/ 64 <475000000>;
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};
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opp07 {
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opp-hz = /bits/ 64 <500000000>;
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};
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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mdio-gpio1 = &mdio_gpio;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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cpuintc: cpuintc {
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compatible = "mti,cpu-interrupt-controller";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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/*
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* Provided for devices with RTL838xM SoC with revision A silicon.
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* Newer SoCs can use the &mdio_aux bus instead.
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*/
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mdio_gpio: mdio {
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compatible = "virtual,mdio-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>,
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<&gpio0 3 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_aux_gpio>;
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status = "disabled";
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x18000000 0x10000>;
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intc: interrupt-controller@3000 {
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compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
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reg = <0x3000 0x18>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>, <3>, <4>, <5>, <6>;
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};
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spi0: spi@1200 {
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compatible = "realtek,rtl8380-spi";
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reg = <0x1200 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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timer0: timer@3100 {
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compatible = "realtek,rtl8380-timer", "realtek,otto-timer";
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reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
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<0x3130 0x10>, <0x3140 0x10>;
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interrupt-parent = <&intc>;
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interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
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clocks = <&ccu CLK_LXB>;
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};
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uart0: uart@2000 {
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compatible = "ns16550a";
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reg = <0x2000 0x100>;
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clocks = <&ccu CLK_LXB>;
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interrupt-parent = <&intc>;
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interrupts = <31 1>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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};
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uart1: uart@2100 {
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pinctrl-names = "default";
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pinctrl-0 = <&enable_uart1>;
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compatible = "ns16550a";
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reg = <0x2100 0x100>;
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clocks = <&ccu CLK_LXB>;
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interrupt-parent = <&intc>;
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interrupts = <30 0>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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status = "disabled";
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};
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watchdog0: watchdog@3150 {
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compatible = "realtek,rtl8380-wdt";
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reg = <0x3150 0xc>;
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realtek,reset-mode = "soc";
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clocks = <&ccu CLK_LXB>;
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timeout-sec = <30>;
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interrupt-parent = <&intc>;
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interrupt-names = "phase1", "phase2";
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interrupts = <19 3>, <18 4>;
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};
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gpio0: gpio-controller@3500 {
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compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
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reg = <0x3500 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <24>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <23 3>;
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};
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};
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switchcore@1b000000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x1b000000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mdio_ctrl: mdio-controller {
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compatible = "realtek,rtl8380-mdio", "realtek,otto-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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mdio_bus0: mdio-bus@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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mdio_aux: mdio-aux {
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compatible = "realtek,rtl8380-aux-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_aux_mdx>, <&aux_mode_mdio>;
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};
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mdio_serdes: mdio-serdes {
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compatible = "realtek,rtl8380-serdes-mdio", "realtek,otto-serdes-mdio";
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};
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pcs {
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compatible = "realtek,rtl8380-pcs", "realtek,otto-pcs";
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#address-cells = <1>;
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#size-cells = <0>;
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serdes0: serdes@0 {
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reg = <0>;
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};
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serdes1: serdes@1 {
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reg = <1>;
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};
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serdes2: serdes@2 {
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reg = <2>;
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};
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serdes3: serdes@3 {
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reg = <3>;
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};
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serdes4: serdes@4 {
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reg = <4>;
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};
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serdes5: serdes@5 {
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reg = <5>;
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};
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};
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soc_thermal: thermal {
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compatible = "realtek,rtl8380-thermal";
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#thermal-sensor-cells = <0>;
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};
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};
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pinmux@1b000144 {
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compatible = "pinctrl-single";
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reg = <0x1b000144 0x4>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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/* I2C mode */
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aux_mode_i2c: i2c-pins {
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pinctrl-single,bits = <0x0 0x0 0x1>;
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};
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/* MDIO mode */
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aux_mode_mdio: mdx-pins {
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pinctrl-single,bits = <0x0 0x1 0x1>;
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};
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};
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pinmux: pinmux@1b001000 {
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compatible = "pinctrl-single";
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reg = <0x1b001000 0x4>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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enable_uart1: pinmux_enable_uart1 {
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pinctrl-single,bits = <0x0 0x10 0x10>;
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};
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};
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/* LED_GLB_CTRL */
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pinmux_led: pinmux@1b00a000 {
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compatible = "pinctrl-single";
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reg = <0x1b00a000 0x4>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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/* enable GPIO 0 */
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pinmux_disable_sys_led: disable_sys_led {
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pinctrl-single,bits = <0x0 0x0 0x8000>;
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};
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};
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pinmux@1b00a0e0 {
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compatible = "pinctrl-single";
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reg = <0x1b00a0e0 0x4>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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/* Use SoC GPIO 2/3 as GPIO */
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mdio_aux_gpio: gpio-pins {
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pinctrl-single,bits = <0x0 0x0 0x1>;
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};
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/* Use SoC GPIO 2/3 as MDC/MDIO */
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mdio_aux_mdx: mdx-pins {
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pinctrl-single,bits = <0x0 0x1 0x1>;
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};
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};
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ethernet0: ethernet@1b00a300 {
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compatible = "realtek,rtl838x-eth";
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reg = <0x1b00a300 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <24 3>;
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#interrupt-cells = <1>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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sram0: sram@9f000000 {
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compatible = "mmio-sram";
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reg = <0x9f000000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x9f000000 0x10000>;
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};
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switch0: switch@1b000000 {
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compatible = "realtek,rtl83xx-switch";
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interrupt-parent = <&intc>;
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interrupts = <20 2>;
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};
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thermal_zones: thermal-zones {
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cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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coefficients = <1000 0>;
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thermal-sensors = <&soc_thermal>;
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trips {
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cpu-crit {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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};
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