forked from mirror/openwrt
1a1b2d3d36
For each port (or port group) the mdio bus needs to define the
PHY type that is attached to it. There are the following bit
values that need to be set in SMI_MAC_TYPE_CTRL.
- 0x0: 10G/1G Fiber (SerDes)
- 0x1: 10G/2G5 GPHY
- 0x2: FEPHY
- 0x3: GPHY
SerDes ports are out of scope of the mdio driver and are handled
by the PCS driver. So the corresponding bits are untouched. That
is not good as the register default is 0x3 for ports 0-23. To
make it simple: Without proper setup devices that have SerDes
driven fiber ports at address 0-23 do not poll in the right way.
Link detection is broken.
Fix this by initializing the register to zero. This way all ports
that are not setup by the mdio driver default to "SerDes". That
should be a reasonable assumption.
Fixes:
|
||
|---|---|---|
| .. | ||
| airoha | ||
| apm821xx | ||
| armsr | ||
| at91 | ||
| ath79 | ||
| bcm27xx | ||
| bcm47xx | ||
| bcm53xx | ||
| bcm4908 | ||
| bmips | ||
| d1 | ||
| econet | ||
| gemini | ||
| generic | ||
| imx | ||
| ipq40xx | ||
| ipq806x | ||
| ixp4xx | ||
| kirkwood | ||
| lantiq | ||
| layerscape | ||
| loongarch64 | ||
| malta | ||
| mediatek | ||
| microchipsw | ||
| mpc85xx | ||
| mvebu | ||
| mxs | ||
| octeon | ||
| omap | ||
| pistachio | ||
| qoriq | ||
| qualcommax | ||
| qualcommbe | ||
| ramips | ||
| realtek | ||
| rockchip | ||
| sifiveu | ||
| siflower | ||
| starfive | ||
| stm32 | ||
| sunxi | ||
| tegra | ||
| uml | ||
| x86 | ||
| zynq | ||
| Makefile | ||