arm-trusted-firmware-mediatek: update to new release 20250711

Update mediatek arm-trusted-firmware to the latest version. Remove upstream patch: 0004-mediatek-snfi-fix-return-code-when-reading.patch Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
uboot-mediatek: sync with mtk-openwrt/u-boot 20250711
2025-07-19 02:59:16 +01:00 · 2025-07-19 02:59:16 +01:00 · 2025-07-19 02:59:16 +01:00 · 2025-07-19 02:59:16 +01:00 · 2025-07-19 02:59:16 +01:00 · 2025-07-19 02:59:15 +01:00
65 changed files with 56073 additions and 3188 deletions
--- a/package/boot/arm-trusted-firmware-mediatek/Makefile
+++ b/package/boot/arm-trusted-firmware-mediatek/Makefile
@ -13,9 +13,9 @@ PKG_RELEASE:=1

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=https://github.com/mtk-openwrt/arm-trusted-firmware.git
-PKG_SOURCE_DATE:=2025-02-12
-PKG_SOURCE_VERSION:=e090770684e775711a624e68e0b28112227a4c38
-PKG_MIRROR_HASH:=1ff9d60f3677aadd9a6716e860985987ba7157bd28ce831112e05c0b3170939a
+PKG_SOURCE_DATE:=2025-07-11
+PKG_SOURCE_VERSION:=78a0dfd927bb00ce973a1f8eb4079df0f755887a
+PKG_MIRROR_HASH:=72a5f3f00f9e368226bb779dc098aac6195a312b48cc22172987d494ccd135d1

 PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>

--- a/package/boot/arm-trusted-firmware-mediatek/patches/0004-mediatek-snfi-fix-return-code-when-reading.patch
+++ b/package/boot/arm-trusted-firmware-mediatek/patches/0004-mediatek-snfi-fix-return-code-when-reading.patch
@ -1,31 +0,0 @@
-From 94802b344195d3574701ca6ab5122f6b7615a6eb Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 11 Aug 2024 23:12:33 +0100
-Subject: [PATCH] mediatek: snfi: fix return code when reading
-
-Return 0 on succesful read, which may contain correctable bitflips.
-
-Fixes: #10
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
- plat/mediatek/apsoc_common/bl2/bl2_dev_snfi_init.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
--- a/plat/mediatek/apsoc_common/bl2/bl2_dev_snfi_init.c
-+++ b/plat/mediatek/apsoc_common/bl2/bl2_dev_snfi_init.c
-@@ -30,9 +30,14 @@ static int snfi_mtd_read_page(struct nan
- 	int ret;
- 
- 	ret = mtk_snand_read_page(snf, addr, (void *)buffer, NULL, false);
-	if (ret == -EBADMSG || ret > 0)
-+	if (ret == -EBADMSG)
- 		ret = 0;
- 
-+	if (ret > 0) {
-+		NOTICE("corrected %d bitflips while reading page %u\n", ret, page);
-+		ret = 0;
-+	}
-+
- 	return ret;
- }
- 
--- a/package/boot/uboot-mediatek/Makefile
+++ b/package/boot/uboot-mediatek/Makefile
@ -1,8 +1,8 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk

-PKG_VERSION:=2025.04
-PKG_HASH:=439d3bef296effd54130be6a731c5b118be7fddd7fcc663ccbc5fb18294d8718
+PKG_VERSION:=2025.07
+PKG_HASH:=0f933f6c5a426895bf306e93e6ac53c60870e4b54cda56d95211bec99e63bec7
 PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host

 UBOOT_USE_INTREE_DTC:=1
--- a/package/boot/uboot-mediatek/patches/001-mtd-spinand-winbond-add-Winbond-W25N04KV-flash-suppo.patch
+++ b/package/boot/uboot-mediatek/patches/001-mtd-spinand-winbond-add-Winbond-W25N04KV-flash-suppo.patch
@ -0,0 +1,56 @@
+From fe37fb8214e40ea64cf03453d112527b629fb08a Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sat, 7 Jun 2025 23:11:21 +0200
+Subject: [PATCH] mtd: spinand: winbond: add Winbond W25N04KV flash support
+
+Add Winbond W25N04KV flash support that use a different value to detect
+ECC bitflip.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/mtd/nand/spi/winbond.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
+@@ -11,6 +11,7 @@
+ #include <linux/device.h>
+ #include <linux/kernel.h>
+ #endif
+#include <linux/bitfield.h>
+ #include <linux/bug.h>
+ #include <linux/mtd/spinand.h>
+ 
+@@ -18,6 +19,8 @@
+ 
+ #define WINBOND_CFG_BUF_READ		BIT(3)
+ 
+#define W25N04KV_STATUS_ECC_5_8_BITFLIPS GENMASK(5, 4)
+
+ static SPINAND_OP_VARIANTS(read_cache_variants,
+ 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+@@ -121,6 +124,7 @@ static int w25n02kv_ecc_get_status(struc
+ 		return -EBADMSG;
+ 
+ 	case STATUS_ECC_HAS_BITFLIPS:
+	case W25N04KV_STATUS_ECC_5_8_BITFLIPS:
+ 		/*
+ 		 * Let's try to retrieve the real maximum number of bitflips
+ 		 * in order to avoid forcing the wear-leveling layer to move
+@@ -169,6 +173,15 @@ static const struct spinand_info winbond
+ 		     NAND_ECCREQ(8, 512),
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ 					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
+	SPINAND_INFO("W25N04KV",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 2, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     0,
+ 		     SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
--- a/package/boot/uboot-mediatek/patches/002-mtd-spinand-gigadevice-sync-supported-chips-with-lin.patch
+++ b/package/boot/uboot-mediatek/patches/002-mtd-spinand-gigadevice-sync-supported-chips-with-lin.patch
@ -0,0 +1,245 @@
+From 506ceddffdc40acf709822b678b986e2e22c5056 Mon Sep 17 00:00:00 2001
+From: Chuanhong Guo <gch981213@gmail.com>
+Date: Wed, 1 May 2024 15:45:23 +0800
+Subject: [PATCH] mtd/spinand: gigadevice: sync supported chips with linux 6.9
+
+Adding support for:
+GD5F1GQ4RExxG
+GD5F2GQ4UExxG
+GD5F2GQ4RExxG
+GD5F1GQ5RExxG
+GD5F2GQ5UExxG
+GD5F2GQ5RExxG
+GD5F4GQ6UExxG
+GD5F4GQ6RExxG
+GD5F1GM7UExxG
+GD5F1GM7RExxG
+GD5F2GM7UExxG
+GD5F2GM7RExxG
+GD5F4GM8UExxG
+GD5F4GM8RExxG
+GD5F2GQ5xExxH
+GD5F1GQ5RExxH
+GD5F1GQ4RExxH
+
+Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
+---
+ drivers/mtd/nand/spi/gigadevice.c | 188 +++++++++++++++++++++++++++++-
+ 1 file changed, 187 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
+@@ -43,6 +43,22 @@ static SPINAND_OP_VARIANTS(read_cache_va
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
+ 
+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+ static SPINAND_OP_VARIANTS(write_cache_variants,
+ 		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+@@ -329,6 +345,36 @@ static const struct spinand_info gigadev
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ 				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GQ4RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GQ4UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GQ4RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+ 	SPINAND_INFO("GD5F1GQ4UFxxG",
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+@@ -343,12 +389,152 @@ static const struct spinand_info gigadev
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ 		     NAND_ECCREQ(4, 512),
+-		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ 				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GQ5RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GQ5UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GQ5RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F4GQ6UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F4GQ6RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GM7UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GM7RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GM7UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GM7RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F4GM8UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F4GM8RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GQ5xExxH",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GQ5RExxH",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x21),
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GQ4RExxH",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xc9),
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+ };
+ 
+ static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
--- a/package/boot/uboot-mediatek/patches/003-net-mediatek-correct-the-AN8855-TPID-value-in-port-i.patch
+++ b/package/boot/uboot-mediatek/patches/003-net-mediatek-correct-the-AN8855-TPID-value-in-port-i.patch
@ -0,0 +1,26 @@
+From dc495442ba610b190775122a31f958ad74229262 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Tue, 8 Jul 2025 17:53:48 +0800
+Subject: [PATCH] net: mediatek: correct the AN8855 TPID value in port
+ isolation settings
+
+The TPID value should be 0x9100 instead of 0x8100 according to the
+datasheet.
+
+Fixes: cedafee9ff3 (net: mediatek: add support for Airoha AN8855 ethernet switch)
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/net/mtk_eth/an8855.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/mtk_eth/an8855.c
+++ b/drivers/net/mtk_eth/an8855.c
+@@ -909,7 +909,7 @@ static void an8855_port_isolation(struct
+ 
+ 		/* Set port mode to user port */
+ 		an8855_reg_write(priv, AN8855_PVC(i),
+-				 (0x8100 << AN8855_STAG_VPID_S) |
+				 (0x9100 << AN8855_STAG_VPID_S) |
+ 				 (VLAN_ATTR_USER << AN8855_VLAN_ATTR_S));
+ 	}
+ }
--- a/package/boot/uboot-mediatek/patches/004-01-serial-mediatek-fix-register-names-and-offsets.patch
+++ b/package/boot/uboot-mediatek/patches/004-01-serial-mediatek-fix-register-names-and-offsets.patch
@ -0,0 +1,44 @@
+From 6e15d3f91aa698798578d39a6d9e292fcc5c577f Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Fri, 23 May 2025 17:25:55 +0800
+Subject: [PATCH] serial: mediatek: fix register names and offsets
+
+Fix UART register names and offsets according to the programming
+guide to allow implementing some enhanced features.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/serial/serial_mtk.c | 17 ++++++++++++-----
+ 1 file changed, 12 insertions(+), 5 deletions(-)
+
+--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
+@@ -30,16 +30,23 @@ struct mtk_serial_regs {
+ 	u32 mcr;
+ 	u32 lsr;
+ 	u32 msr;
+-	u32 spr;
+-	u32 mdr1;
+	u32 scr;
+	u32 autobaud_en;
+ 	u32 highspeed;
+ 	u32 sample_count;
+ 	u32 sample_point;
+	u32 autobaud_reg;
+	u32 ratefix_ad;
+	u32 autobaud_sample;
+	u32 guard;
+	u32 escape_dat;
+	u32 escape_en;
+	u32 sleep_en;
+	u32 dma_en;
+	u32 rxtri_ad;
+ 	u32 fracdiv_l;
+ 	u32 fracdiv_m;
+-	u32 escape_en;
+-	u32 guard;
+-	u32 rx_sel;
+	u32 fcr_rd;
+ };
+ 
+ #define thr rbr
--- a/package/boot/uboot-mediatek/patches/004-02-serial-mediatek-enable-baudrate-accuracy-compensatio.patch
+++ b/package/boot/uboot-mediatek/patches/004-02-serial-mediatek-enable-baudrate-accuracy-compensatio.patch
@ -0,0 +1,81 @@
+From 6952209ef220138189dd261d06441e1b2d50e994 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Fri, 23 May 2025 17:26:02 +0800
+Subject: [PATCH] serial: mediatek: enable baudrate accuracy compensation
+
+The high-speed UART from MediaTek supports baudrate accuracy
+compensation when using high-speed mode 3.
+
+This is done by calculating the first digit of the fraction part of
+sample count value. The fraction value will be then used as the
+reference to insert 0 to 10 sample cycle(s) to one frame (assume
+that frame format is 8n1, i.e. 10 bits per frame).
+
+The fracdiv_[l/m] registers are used to determine whether a bit in one frame
+should be inserted with one sample cycle.
+
+With typical 40MHz source clock, the actual baudrates with/without
+accuracy compensation are:
+
+Ideal    w/o compensation w/ compensation
+======== ================ ===============
+9600     9603             9600
+115200   114942           115207
+921600   930232           921659
+3000000  3076923          3007519
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/serial/serial_mtk.c | 24 +++++++++++++++++++++---
+ 1 file changed, 21 insertions(+), 3 deletions(-)
+
+--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
+@@ -99,10 +99,18 @@ struct mtk_serial_priv {
+ 	bool upstream_highspeed_logic;
+ };
+ 
+static const unsigned short fraction_l_mapping[] = {
+	0, 1, 0x5, 0x15, 0x55, 0x57, 0x57, 0x77, 0x7F, 0xFF, 0xFF
+};
+
+static const unsigned short fraction_m_mapping[] = {
+	0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3
+};
+
+ static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud,
+ 			       uint clk_rate)
+ {
+-	u32 quot, realbaud, samplecount = 1;
+	u32 quot, realbaud, samplecount = 1, fraction, frac_l = 0, frac_m = 0;
+ 
+ 	/* Special case for low baud clock */
+ 	if (baud <= 115200 && clk_rate == 12000000) {
+@@ -147,7 +155,13 @@ use_hs3:
+ 		writel(3, &priv->regs->highspeed);
+ 
+ 		quot = DIV_ROUND_UP(clk_rate, 256 * baud);
+-		samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud);
+		samplecount = clk_rate / (quot * baud);
+
+		fraction = ((clk_rate * 100) / quot / baud) % 100;
+		fraction = DIV_ROUND_CLOSEST(fraction, 10);
+
+		frac_l = fraction_l_mapping[fraction];
+		frac_m = fraction_m_mapping[fraction];
+ 	}
+ 
+ set_baud:
+@@ -159,7 +173,11 @@ set_baud:
+ 
+ 	/* set highspeed mode sample count & point */
+ 	writel(samplecount - 1, &priv->regs->sample_count);
+-	writel((samplecount - 2) >> 1, &priv->regs->sample_point);
+	writel((samplecount >> 1) - 1, &priv->regs->sample_point);
+
+	/* set baudrate fraction compensation */
+	writel(frac_l, &priv->regs->fracdiv_l);
+	writel(frac_m, &priv->regs->fracdiv_m);
+ }
+ 
+ static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
--- a/package/boot/uboot-mediatek/patches/100-01-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch
+++ b/package/boot/uboot-mediatek/patches/100-01-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch
@ -1,7 +1,7 @@
-From f7704275957852cd4c4632d6da126979ef24b83a Mon Sep 17 00:00:00 2001
+From 86d7d787e6d9802176cc563a95ac5c1919fbad66 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Tue, 2 Mar 2021 16:58:01 +0800
-Subject: [PATCH 36/71] drivers: mtd: add support for MediaTek SPI-NAND flash
+Subject: [PATCH 01/30] drivers: mtd: add support for MediaTek SPI-NAND flash
 controller

 Add mtd driver for MediaTek SPI-NAND flash controller
@ -19,12 +19,12 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 drivers/mtd/mtk-snand/mtk-snand-def.h |  271 ++++
 drivers/mtd/mtk-snand/mtk-snand-ecc.c |  411 ++++++
 drivers/mtd/mtk-snand/mtk-snand-ids.c |  515 +++++++
- drivers/mtd/mtk-snand/mtk-snand-mtd.c |  535 +++++++
+ drivers/mtd/mtk-snand/mtk-snand-mtd.c |  534 +++++++
 drivers/mtd/mtk-snand/mtk-snand-os.c  |   39 +
- drivers/mtd/mtk-snand/mtk-snand-os.h  |  120 ++
+ drivers/mtd/mtk-snand/mtk-snand-os.h  |  119 ++
 drivers/mtd/mtk-snand/mtk-snand.c     | 1933 +++++++++++++++++++++++++
 drivers/mtd/mtk-snand/mtk-snand.h     |   77 +
- 12 files changed, 3937 insertions(+)
+ 12 files changed, 3935 insertions(+)
 create mode 100644 drivers/mtd/mtk-snand/Kconfig
 create mode 100644 drivers/mtd/mtk-snand/Makefile
 create mode 100644 drivers/mtd/mtk-snand/mtk-snand-def.h
@ -514,8 +514,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes,
 +		  uint32_t msg_size)
 +{
-+	uint32_t i, val, ecc_msg_bits, ecc_strength;
-+	int ret;
+	uint32_t val, ecc_msg_bits, ecc_strength;
+	int i, ret;
 +
 +	snf->ecc_soc = &mtk_ecc_socs[snf->soc];
 +
@ -783,7 +783,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +}
 --- /dev/null
 +++ b/drivers/mtd/mtk-snand/mtk-snand-ids.c
-@@ -0,0 +1,519 @@
+@@ -0,0 +1,515 @@
 +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 +/*
 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
@ -901,10 +901,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		   SNAND_MEMORG_1G_2K_64,
 +		   &snand_cap_read_from_cache_quad_q2d,
 +		   &snand_cap_program_load_x4),
-+	SNAND_INFO("GD5F1GQ5UExxG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x51),
-+		   SNAND_MEMORG_1G_2K_128,
-+		   &snand_cap_read_from_cache_quad,
-+		   &snand_cap_program_load_x4),
 +	SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2),
 +		   SNAND_MEMORG_2G_2K_128,
 +		   &snand_cap_read_from_cache_quad_q2d,
@ -1217,7 +1213,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +
 +	SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
 +		   SNAND_MEMORG_1G_2K_64,
-+		   &snand_cap_read_from_cache_x4_only,
+		   &snand_cap_read_from_cache_x4,
 +		   &snand_cap_program_load_x4),
 +
 +	SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),
@ -1305,7 +1301,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +}
 --- /dev/null
 +++ b/drivers/mtd/mtk-snand/mtk-snand-mtd.c
-@@ -0,0 +1,535 @@
+@@ -0,0 +1,534 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
@ -1313,7 +1309,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 + * Author: Weijie Gao <weijie.gao@mediatek.com>
 + */
 +
-+#include <config.h>
 +#include <dm.h>
 +#include <malloc.h>
 +#include <mapmem.h>
@ -1885,7 +1880,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +}
 --- /dev/null
 +++ b/drivers/mtd/mtk-snand/mtk-snand-os.h
-@@ -0,0 +1,120 @@
+@@ -0,0 +1,119 @@
 +/* SPDX-License-Identifier: GPL-2.0 */
 +/*
 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
@ -1896,7 +1891,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +#ifndef _MTK_SNAND_OS_H_
 +#define _MTK_SNAND_OS_H_
 +
-+#include <config.h>
 +#include <cpu_func.h>
 +#include <errno.h>
 +#include <div64.h>
--- a/package/boot/uboot-mediatek/patches/100-02-mtd-mtk-snand-add-support-for-SPL.patch
+++ b/package/boot/uboot-mediatek/patches/100-02-mtd-mtk-snand-add-support-for-SPL.patch
@ -1,7 +1,7 @@
-From a347e374cb338213632c6dde88dd226d64bd8b27 Mon Sep 17 00:00:00 2001
+From 219aa55e830fe7f5b56dc097f544990a032a0bfe Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Wed, 3 Mar 2021 08:57:29 +0800
-Subject: [PATCH 37/71] mtd: mtk-snand: add support for SPL
+Subject: [PATCH 02/30] mtd: mtk-snand: add support for SPL

 Add support to initialize SPI-NAND in SPL.
 Add implementation for SPL NAND loader.
@ -47,7 +47,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 + * Author: Weijie Gao <weijie.gao@mediatek.com>
 + */
 +
-+#include <config.h>
+#include <common.h>
 +#include <dm.h>
 +#include <dm/uclass.h>
 +#include <malloc.h>
--- a/package/boot/uboot-mediatek/patches/100-03-mtd-add-a-new-mtd-device-type-for-NMBM.patch
+++ b/package/boot/uboot-mediatek/patches/100-03-mtd-add-a-new-mtd-device-type-for-NMBM.patch
@ -1,7 +1,7 @@
-From d26a789c451068caf4bbb4d1ac7bc1f592b5493e Mon Sep 17 00:00:00 2001
+From 6571329dbac9f2278b6a5d36999982220b17daf4 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 10:58:06 +0800
-Subject: [PATCH 39/71] mtd: add a new mtd device type for NMBM
+Subject: [PATCH 03/30] mtd: add a new mtd device type for NMBM

 This patch adds a new mtd device type for NMBM so that mtdparts can be
 correctly probed. And this also gives us an opportunity to add NMBM support
--- a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch
+++ b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch
@ -1,390 +0,0 @@
-From efc3e6f5d29f87a433b42f15a0b87e04b7cd498d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 3 Mar 2021 10:11:32 +0800
-Subject: [PATCH 38/71] env: add support for generic MTD device
-
-Add an env driver for generic MTD device.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
- cmd/nvedit.c           |   3 +-
- env/Kconfig            |  37 +++++-
- env/Makefile           |   1 +
- env/env.c              |   3 +
- env/mtd.c              | 256 +++++++++++++++++++++++++++++++++++++++++
- include/env_internal.h |   1 +
- tools/Makefile         |   1 +
- 7 files changed, 299 insertions(+), 3 deletions(-)
- create mode 100644 env/mtd.c
-
--- a/env/Kconfig
-+++ b/env/Kconfig
-@@ -74,7 +74,7 @@ config ENV_IS_DEFAULT
- 		     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
- 		     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
- 		     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
-		     !ENV_IS_IN_UBI
-+		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
- 	select ENV_IS_NOWHERE
- 
- config ENV_IS_NOWHERE
-@@ -267,6 +267,27 @@ config ENV_IS_IN_MMC
- 	  offset: "u-boot,mmc-env-offset", "u-boot,mmc-env-offset-redundant".
- 	  CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND are not used.
- 
-+config ENV_IS_IN_MTD
-+	bool "Environment in a MTD device"
-+	depends on !CHAIN_OF_TRUST
-+	depends on MTD
-+	help
-+	  Define this if you have a MTD device which you want to use for
-+	  the environment.
-+
-+	  - CONFIG_ENV_MTD_NAME:
-+	  - CONFIG_ENV_OFFSET:
-+	  - CONFIG_ENV_SIZE:
-+
-+	  These three #defines specify the MTD device where the environment
-+	  is stored, offset and size of the environment area within the MTD
-+	  device. CONFIG_ENV_OFFSET must be aligned to an erase block boundary.
-+
-+	  - CONFIG_ENV_SIZE_REDUND:
-+
-+	  This #define specify the maximum size allowed for read/write/erase
-+	  with skipped bad blocks starting from ENV_OFFSET.
-+
- config ENV_IS_IN_NAND
- 	bool "Environment in a NAND device"
- 	depends on !CHAIN_OF_TRUST
-@@ -574,10 +595,16 @@ config ENV_ADDR_REDUND
- 	  Offset from the start of the device (or partition) of the redundant
- 	  environment location.
- 
-+config ENV_MTD_NAME
-+	string "Name of the MTD device storing the environment"
-+	depends on ENV_IS_IN_MTD
-+	help
-+	  Name of the MTD device that stores the environment
-+
- config ENV_OFFSET
- 	hex "Environment offset"
- 	depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
-		    ENV_IS_IN_SPI_FLASH
-+		    ENV_IS_IN_SPI_FLASH || ENV_IS_IN_MTD
- 	default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
- 	default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
- 	default 0xF0000 if ARCH_SUNXI
-@@ -635,6 +662,12 @@ config ENV_SECT_SIZE
- 	help
- 	  Size of the sector containing the environment.
- 
-+config ENV_SIZE_REDUND
-+	hex "Redundant environment size"
-+	depends on ENV_IS_IN_MTD
-+	help
-+	  The maximum size allowed for read/write/erase with skipped bad blocks.
-+
- config ENV_UBI_PART
- 	string "UBI partition name"
- 	depends on ENV_IS_IN_UBI
--- a/env/Makefile
-+++ b/env/Makefile
-@@ -24,6 +24,7 @@ obj-$(CONFIG_$(PHASE_)ENV_IS_NOWHERE) +=
- obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MMC) += mmc.o
- obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FAT) += fat.o
- obj-$(CONFIG_$(PHASE_)ENV_IS_IN_EXT4) += ext4.o
-+obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MTD) += mtd.o
- obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NAND) += nand.o
- obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SPI_FLASH) += sf.o
- obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o
--- a/env/env.c
-+++ b/env/env.c
-@@ -46,6 +46,9 @@ static enum env_location env_locations[]
- #ifdef CONFIG_ENV_IS_IN_MMC
- 	ENVL_MMC,
- #endif
-+#ifdef CONFIG_ENV_IS_IN_MTD
-+	ENVL_MTD,
-+#endif
- #ifdef CONFIG_ENV_IS_IN_NAND
- 	ENVL_NAND,
- #endif
--- /dev/null
-+++ b/env/mtd.c
-@@ -0,0 +1,256 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2021 MediaTek Inc. All Rights Reserved.
-+ *
-+ * Author: Weijie Gao <weijie.gao@mediatek.com>
-+ */
-+
-+#include <command.h>
-+#include <env.h>
-+#include <env_internal.h>
-+#include <errno.h>
-+#include <linux/kernel.h>
-+#include <linux/stddef.h>
-+#include <linux/types.h>
-+#include <linux/mtd/mtd.h>
-+#include <malloc.h>
-+#include <memalign.h>
-+#include <mtd.h>
-+#include <search.h>
-+
-+#if CONFIG_ENV_SIZE_REDUND < CONFIG_ENV_SIZE
-+#undef CONFIG_ENV_SIZE_REDUND
-+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-+#endif
-+
-+#if defined(ENV_IS_EMBEDDED)
-+env_t *env_ptr = &environment;
-+#else /* ! ENV_IS_EMBEDDED */
-+env_t *env_ptr;
-+#endif /* ENV_IS_EMBEDDED */
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+static int env_mtd_init(void)
-+{
-+#if defined(ENV_IS_EMBEDDED)
-+	int crc1_ok = 0, crc2_ok = 0;
-+	env_t *tmp_env1;
-+
-+	tmp_env1 = env_ptr;
-+	crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc;
-+
-+	if (!crc1_ok && !crc2_ok) {
-+		gd->env_addr	= 0;
-+		gd->env_valid	= ENV_INVALID;
-+
-+		return 0;
-+	} else if (crc1_ok && !crc2_ok) {
-+		gd->env_valid = ENV_VALID;
-+	}
-+
-+	if (gd->env_valid == ENV_VALID)
-+		env_ptr = tmp_env1;
-+
-+	gd->env_addr = (ulong)env_ptr->data;
-+
-+#else /* ENV_IS_EMBEDDED */
-+	gd->env_addr	= (ulong)&default_environment[0];
-+	gd->env_valid	= ENV_VALID;
-+#endif /* ENV_IS_EMBEDDED */
-+
-+	return 0;
-+}
-+
-+static struct mtd_info *env_mtd_get_dev(void)
-+{
-+	struct mtd_info *mtd;
-+
-+	mtd_probe_devices();
-+
-+	mtd = get_mtd_device_nm(CONFIG_ENV_MTD_NAME);
-+	if (IS_ERR(mtd) || !mtd) {
-+		printf("MTD device '%s' not found\n", CONFIG_ENV_MTD_NAME);
-+		return NULL;
-+	}
-+
-+	return mtd;
-+}
-+
-+static inline bool mtd_addr_is_block_aligned(struct mtd_info *mtd, u64 addr)
-+{
-+	return (addr & mtd->erasesize_mask) == 0;
-+}
-+
-+static int mtd_io_skip_bad(struct mtd_info *mtd, bool read, loff_t offset,
-+			   size_t length, size_t redund, u8 *buffer)
-+{
-+	struct mtd_oob_ops io_op = {};
-+	size_t remaining = length;
-+	loff_t off, end;
-+	int ret;
-+
-+	io_op.mode = MTD_OPS_PLACE_OOB;
-+	io_op.len = mtd->writesize;
-+	io_op.datbuf = (void *)buffer;
-+
-+	/* Search for the first good block after the given offset */
-+	off = offset;
-+	end = (off + redund) | (mtd->erasesize - 1);
-+	while (mtd_block_isbad(mtd, off) && off < end)
-+		off += mtd->erasesize;
-+
-+	/* Reached end position */
-+	if (off >= end)
-+		return -EIO;
-+
-+	/* Loop over the pages to do the actual read/write */
-+	while (remaining) {
-+		/* Skip the block if it is bad */
-+		if (mtd_addr_is_block_aligned(mtd, off) &&
-+		    mtd_block_isbad(mtd, off)) {
-+			off += mtd->erasesize;
-+			continue;
-+		}
-+
-+		if (read)
-+			ret = mtd_read_oob(mtd, off, &io_op);
-+		else
-+			ret = mtd_write_oob(mtd, off, &io_op);
-+
-+		if (ret) {
-+			printf("Failure while %s at offset 0x%llx\n",
-+			       read ? "reading" : "writing", off);
-+			break;
-+		}
-+
-+		off += io_op.retlen;
-+		remaining -= io_op.retlen;
-+		io_op.datbuf += io_op.retlen;
-+		io_op.oobbuf += io_op.oobretlen;
-+
-+		/* Reached end position */
-+		if (off >= end)
-+			return -EIO;
-+	}
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_CMD_SAVEENV
-+static int mtd_erase_skip_bad(struct mtd_info *mtd, loff_t offset,
-+			      size_t length, size_t redund)
-+{
-+	struct erase_info erase_op = {};
-+	loff_t end = (offset + redund) | (mtd->erasesize - 1);
-+	int ret;
-+
-+	erase_op.mtd = mtd;
-+	erase_op.addr = offset;
-+	erase_op.len = length;
-+
-+	while (erase_op.len) {
-+		ret = mtd_erase(mtd, &erase_op);
-+
-+		/* Abort if its not a bad block error */
-+		if (ret != -EIO)
-+			return ret;
-+
-+		printf("Skipping bad block at 0x%08llx\n", erase_op.fail_addr);
-+
-+		/* Skip bad block and continue behind it */
-+		erase_op.len -= erase_op.fail_addr - erase_op.addr;
-+		erase_op.len -= mtd->erasesize;
-+		erase_op.addr = erase_op.fail_addr + mtd->erasesize;
-+
-+		/* Reached end position */
-+		if (erase_op.addr >= end)
-+			return -EIO;
-+	}
-+
-+	return 0;
-+}
-+
-+static int env_mtd_save(void)
-+{
-+	ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
-+	struct mtd_info *mtd;
-+	int ret = 0;
-+
-+	ret = env_export(env_new);
-+	if (ret)
-+		return ret;
-+
-+	mtd = env_mtd_get_dev();
-+	if (!mtd)
-+		return 1;
-+
-+	printf("Erasing on MTD device '%s'... ", mtd->name);
-+
-+	ret = mtd_erase_skip_bad(mtd, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-+				 CONFIG_ENV_SIZE_REDUND);
-+
-+	puts(ret ? "FAILED\n" : "OK\n");
-+
-+	if (ret) {
-+		put_mtd_device(mtd);
-+		return 1;
-+	}
-+
-+	printf("Writing to MTD device '%s'... ", mtd->name);
-+
-+	ret = mtd_io_skip_bad(mtd, false, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-+			      CONFIG_ENV_SIZE_REDUND, (u8 *)env_new);
-+
-+	puts(ret ? "FAILED\n" : "OK\n");
-+
-+	put_mtd_device(mtd);
-+
-+	return !!ret;
-+}
-+#endif /* CONFIG_CMD_SAVEENV */
-+
-+static int readenv(size_t offset, u_char *buf)
-+{
-+	struct mtd_info *mtd;
-+	int ret;
-+
-+	mtd = env_mtd_get_dev();
-+	if (!mtd)
-+		return 1;
-+
-+	ret = mtd_io_skip_bad(mtd, true, offset, CONFIG_ENV_SIZE,
-+			      CONFIG_ENV_SIZE_REDUND, buf);
-+
-+	put_mtd_device(mtd);
-+
-+	return !!ret;
-+}
-+
-+static int env_mtd_load(void)
-+{
-+#if !defined(ENV_IS_EMBEDDED)
-+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
-+	int ret;
-+
-+	ret = readenv(CONFIG_ENV_OFFSET, (u_char *)buf);
-+	if (ret) {
-+		env_set_default("readenv() failed", 0);
-+		return -EIO;
-+	}
-+
-+	return env_import(buf, 1, H_EXTERNAL);
-+#endif /* ! ENV_IS_EMBEDDED */
-+
-+	return 0;
-+}
-+
-+U_BOOT_ENV_LOCATION(mtd) = {
-+	.location	= ENVL_MTD,
-+	ENV_NAME("MTD")
-+	.load		= env_mtd_load,
-+#if defined(CONFIG_CMD_SAVEENV)
-+	.save		= env_save_ptr(env_mtd_save),
-+#endif
-+	.init		= env_mtd_init,
-+};
--- a/include/env_internal.h
-+++ b/include/env_internal.h
-@@ -108,6 +108,7 @@ enum env_location {
- 	ENVL_FAT,
- 	ENVL_FLASH,
- 	ENVL_MMC,
-+	ENVL_MTD,
- 	ENVL_NAND,
- 	ENVL_NVRAM,
- 	ENVL_ONENAND,
--- a/tools/Makefile
-+++ b/tools/Makefile
-@@ -37,6 +37,7 @@ subdir-$(HOST_TOOLS_ALL) += gdb
- ENVCRC-$(CONFIG_ENV_IS_IN_EEPROM) = y
- ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y
- ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y
-+ENVCRC-$(CONFIG_ENV_IS_IN_MTD) = y
- ENVCRC-$(CONFIG_ENV_IS_IN_NAND) = y
- ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y
- ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y
--- a/package/boot/uboot-mediatek/patches/100-04-mtd-add-core-facility-code-of-NMBM.patch
+++ b/package/boot/uboot-mediatek/patches/100-04-mtd-add-core-facility-code-of-NMBM.patch
@ -1,7 +1,7 @@
-From 690479081fb6a0c0f77f10fb457ad69e71390f15 Mon Sep 17 00:00:00 2001
+From 9b29603e11e68148f640d602361dcc5e61f431b3 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 10:26:35 +0800
-Subject: [PATCH 40/71] mtd: add core facility code of NMBM
+Subject: [PATCH 04/30] mtd: add core facility code of NMBM

 This patch adds a NAND bad block management named NMBM (NAND mapping block
 management) which supports using a mapping table to deal with bad blocks
--- a/package/boot/uboot-mediatek/patches/100-05-mtd-nmbm-add-support-for-mtd.patch
+++ b/package/boot/uboot-mediatek/patches/100-05-mtd-nmbm-add-support-for-mtd.patch
@ -1,7 +1,7 @@
-From 0524995f07fcd216a1a7e267fdb5cf2b0ede8489 Mon Sep 17 00:00:00 2001
+From 0056bd4ec8ac2cbde6c2a5e07cba9b4eb3b7cfa3 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 10:42:12 +0800
-Subject: [PATCH 41/71] mtd: nmbm: add support for mtd
+Subject: [PATCH 05/30] mtd: nmbm: add support for mtd

 Add support to create NMBM based on MTD devices

--- a/package/boot/uboot-mediatek/patches/100-06-common-board_r-add-support-to-initialize-NMBM-after-.patch
+++ b/package/boot/uboot-mediatek/patches/100-06-common-board_r-add-support-to-initialize-NMBM-after-.patch
@ -1,7 +1,7 @@
-From dcf24c8deeb43a4406ae18136c8700dc2f867415 Mon Sep 17 00:00:00 2001
+From 7499c0e030ef5051b2920576a75dfd7c60d5232a Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 11:18:03 +0800
-Subject: [PATCH 42/71] common: board_r: add support to initialize NMBM after
+Subject: [PATCH 06/30] common: board_r: add support to initialize NMBM after
 nand initialization

 This patch add support to initialize NMBM after nand initialized.
@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/common/board_r.c
 +++ b/common/board_r.c
-@@ -378,6 +378,20 @@ static int initr_nand(void)
+@@ -399,6 +399,20 @@ static int initr_nand(void)
 }
 #endif
 
@ -34,13 +34,13 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 #if defined(CONFIG_CMD_ONENAND)
 /* go init the NAND */
 static int initr_onenand(void)
-@@ -693,6 +707,9 @@ static init_fnc_t init_sequence_r[] = {
- #ifdef CONFIG_CMD_ONENAND
- 	initr_onenand,
+@@ -718,6 +732,9 @@ static void initcall_run_r(void)
+ #if CONFIG_IS_ENABLED(CMD_ONENAND)
+ 	INITCALL(initr_onenand);
 #endif
-+#ifdef CONFIG_NMBM_MTD
-+	initr_nmbm,
+#if CONFIG_IS_ENABLED(NMBM_MTD)
+	INITCALL(initr_nmbm);
 +#endif
- #ifdef CONFIG_MMC
- 	initr_mmc,
+ #if CONFIG_IS_ENABLED(MMC)
+ 	INITCALL(initr_mmc);
 #endif
--- a/package/boot/uboot-mediatek/patches/100-07-cmd-add-nmbm-command.patch
+++ b/package/boot/uboot-mediatek/patches/100-07-cmd-add-nmbm-command.patch
@ -1,7 +1,7 @@
-From 0af8d0aac77f4df4bc7dadbcdea5d9a16f5f3e45 Mon Sep 17 00:00:00 2001
+From db0424519d3cc24ae94c15de26af12c075a95e6a Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 10:44:57 +0800
-Subject: [PATCH 43/71] cmd: add nmbm command
+Subject: [PATCH 07/30] cmd: add nmbm command

 Add nmbm command for debugging, data operations and image-booting support

@ -9,13 +9,13 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 ---
 cmd/Kconfig  |   6 +
 cmd/Makefile |   1 +
- cmd/nmbm.c   | 327 +++++++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 334 insertions(+)
+ cmd/nmbm.c   | 328 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 335 insertions(+)
 create mode 100644 cmd/nmbm.c

 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1525,6 +1525,12 @@ config CMD_NAND_WATCH
+@@ -1535,6 +1535,12 @@ config CMD_NAND_WATCH
 
 endif # CMD_NAND
 
@ -40,7 +40,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 else ifdef CONFIG_NET_LWIP
 --- /dev/null
 +++ b/cmd/nmbm.c
-@@ -0,0 +1,327 @@
+@@ -0,0 +1,328 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
@ -49,6 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 + */
 +
 +#include <command.h>
+#include <env.h>
 +#include <image.h>
 +#include <stdbool.h>
 +#include <linux/types.h>
--- a/package/boot/uboot-mediatek/patches/100-08-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
+++ b/package/boot/uboot-mediatek/patches/100-08-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
@ -1,7 +1,7 @@
-From 6dbbc8affb6ab22f940d13d0e928d5e881127ca4 Mon Sep 17 00:00:00 2001
+From f180eb4beec9b0cf19e8c2418d2b01404797cb26 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 11:22:57 +0800
-Subject: [PATCH 44/71] cmd: mtd: add markbad subcommand for NMBM testing
+Subject: [PATCH 08/30] cmd: mtd: add markbad subcommand for NMBM testing

 This patch adds:
 * Mark bad block on lower mtd device and erase on upper mtd
--- a/package/boot/uboot-mediatek/patches/100-09-mtd-mtk-snand-add-NMBM-support-for-SPL.patch
+++ b/package/boot/uboot-mediatek/patches/100-09-mtd-mtk-snand-add-NMBM-support-for-SPL.patch
@ -1,18 +1,38 @@
-From 9e8ac4fc7125795ac5e8834aaf454fd45b99c580 Mon Sep 17 00:00:00 2001
+From 1c5d96f544cfe2140834cc79dc1335b0e6fc5ce5 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 10:53:03 +0800
-Subject: [PATCH 46/71] mtd: mtk-snand: add NMBM support for SPL
+Subject: [PATCH 09/30] mtd: mtk-snand: add NMBM support for SPL

 Add NMBM support for mtk-snand SPL loader

 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 ---
- drivers/mtd/mtk-snand/mtk-snand-spl.c | 127 ++++++++++++++++++++++++++
- 1 file changed, 127 insertions(+)
+ drivers/mtd/mtk-snand/Makefile        |   2 +-
+ drivers/mtd/mtk-snand/mtk-snand-spl.c | 133 +++++++++++++++++++++++++-
+ 2 files changed, 133 insertions(+), 2 deletions(-)

+--- a/drivers/mtd/mtk-snand/Makefile
+++ b/drivers/mtd/mtk-snand/Makefile
+@@ -8,7 +8,7 @@
+ obj-y += mtk-snand.o mtk-snand-ecc.o mtk-snand-ids.o mtk-snand-os.o
+ obj-$(CONFIG_MTK_SPI_NAND_MTD) += mtk-snand-mtd.o
+ 
+-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
+ obj-$(CONFIG_SPL_MTK_SPI_NAND) += mtk-snand-spl.o
+ endif
+ 
 --- a/drivers/mtd/mtk-snand/mtk-snand-spl.c
 +++ b/drivers/mtd/mtk-snand/mtk-snand-spl.c
-@@ -13,12 +13,134 @@
+@@ -5,7 +5,6 @@
+  * Author: Weijie Gao <weijie.gao@mediatek.com>
+  */
+ 
+-#include <common.h>
+ #include <dm.h>
+ #include <dm/uclass.h>
+ #include <malloc.h>
+@@ -13,12 +12,134 @@
 #include <mtd.h>
 #include <watchdog.h>
 
@ -147,7 +167,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 static u8 *page_cache;
 
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
-@@ -60,6 +182,7 @@ int nand_spl_load_image(uint32_t offs, u
+@@ -60,6 +181,7 @@ int nand_spl_load_image(uint32_t offs, u
 
 	return ret;
 }
@ -155,7 +175,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 void nand_init(void)
 {
-@@ -105,11 +228,15 @@ void nand_init(void)
+@@ -105,11 +227,20 @@ void nand_init(void)
 	printf("SPI-NAND: %s (%uMB)\n", cinfo.model,
 	       (u32)(cinfo.chipsize >> 20));
 
@ -168,6 +188,11 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 		printf("mtk-snand-spl: failed to allocate page cache\n");
 	}
 +#endif
+}
+
+unsigned int nand_page_size(void)
+{
+	return cinfo.pagesize;
 }
 
 void nand_deselect(void)
--- a/package/boot/uboot-mediatek/patches/100-10-cmd-add-a-new-command-for-NAND-flash-debugging.patch
+++ b/package/boot/uboot-mediatek/patches/100-10-cmd-add-a-new-command-for-NAND-flash-debugging.patch
@ -1,7 +1,7 @@
-From 88271cb3ae9c68dc200d627653df96fc557c2a64 Mon Sep 17 00:00:00 2001
+From e33ed7c216b6fc7416e205fffccfedf32e26ff8b Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 10:55:35 +0800
-Subject: [PATCH 47/71] cmd: add a new command for NAND flash debugging
+Subject: [PATCH 10/30] cmd: add a new command for NAND flash debugging

 Add a command 'nand-ext' for NAND flash debugging:
 - Dump a page with oob, with optional raw read support
@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1525,6 +1525,14 @@ config CMD_NAND_WATCH
+@@ -1535,6 +1535,14 @@ config CMD_NAND_WATCH
 
 endif # CMD_NAND
 
--- a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
+++ b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
@ -1,7 +1,7 @@
 From 240d98e6ad0aed3c11236aa40a60bbd6fe01fae5 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 10:50:46 +0800
-Subject: [PATCH 45/71] env: add support for NMBM upper MTD layer
+Subject: [PATCH 11/30] env: add support for NMBM upper MTD layer

 Add an env driver for NMBM upper MTD layer

@ -27,7 +27,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 	select ENV_IS_NOWHERE
 
 config ENV_IS_NOWHERE
-@@ -318,6 +318,21 @@ config ENV_IS_IN_NAND
+@@ -297,6 +297,21 @@ config ENV_IS_IN_NAND
 	  Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
 	  using CONFIG_ENV_OFFSET_OOB.
 
@ -49,7 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 config ENV_RANGE
 	hex "Length of the region in which the environment can be written"
 	depends on ENV_IS_IN_NAND
-@@ -604,7 +619,7 @@ config ENV_MTD_NAME
+@@ -596,7 +611,7 @@ config ENV_ADDR_REDUND
 config ENV_OFFSET
 	hex "Environment offset"
 	depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
@ -60,17 +60,17 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 	default 0xF0000 if ARCH_SUNXI
 --- a/env/Makefile
 +++ b/env/Makefile
-@@ -26,6 +26,7 @@ obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FAT) +=
+@@ -25,6 +25,7 @@ obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MMC) +=
+ obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FAT) += fat.o
 obj-$(CONFIG_$(PHASE_)ENV_IS_IN_EXT4) += ext4.o
- obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MTD) += mtd.o
 obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NAND) += nand.o
 +obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NMBM) += nmbm.o
 obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SPI_FLASH) += sf.o
+ obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MTD) += mtd.o
 obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o
- 
 --- a/env/env.c
 +++ b/env/env.c
-@@ -52,6 +52,9 @@ static enum env_location env_locations[]
+@@ -49,6 +49,9 @@ static enum env_location env_locations[]
 #ifdef CONFIG_ENV_IS_IN_NAND
 	ENVL_NAND,
 #endif
@ -240,9 +240,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +};
 --- a/include/env_internal.h
 +++ b/include/env_internal.h
-@@ -110,6 +110,7 @@ enum env_location {
+@@ -109,6 +109,7 @@ enum env_location {
+ 	ENVL_FLASH,
 	ENVL_MMC,
- 	ENVL_MTD,
 	ENVL_NAND,
 +	ENVL_NMBM,
 	ENVL_NVRAM,
@ -250,9 +250,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 	ENVL_REMOTE,
 --- a/tools/Makefile
 +++ b/tools/Makefile
-@@ -39,6 +39,7 @@ ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y
+@@ -38,6 +38,7 @@ ENVCRC-$(CONFIG_ENV_IS_IN_EEPROM) = y
+ ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y
 ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y
- ENVCRC-$(CONFIG_ENV_IS_IN_MTD) = y
 ENVCRC-$(CONFIG_ENV_IS_IN_NAND) = y
 +ENVCRC-$(CONFIG_ENV_IS_IN_NMBM) = y
 ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y
--- a/package/boot/uboot-mediatek/patches/100-12-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
+++ b/package/boot/uboot-mediatek/patches/100-12-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
@ -1,7 +1,7 @@
-From c4172a95df8a57a66c70a8b9948b9600a01c4cb7 Mon Sep 17 00:00:00 2001
+From b4c97d64ab00d74359112b8fc6e329d2fef792e3 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 11:32:08 +0800
-Subject: [PATCH 49/71] mtd: spi-nor: add support to read flash unique ID
+Subject: [PATCH 12/30] mtd: spi-nor: add support to read flash unique ID

 This patch adds support to read unique ID from spi-nor flashes.

@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/drivers/mtd/spi/spi-nor-core.c
 +++ b/drivers/mtd/spi/spi-nor-core.c
-@@ -3248,6 +3248,100 @@ static int spi_nor_init_params(struct sp
+@@ -3262,6 +3262,100 @@ static int spi_nor_init_params(struct sp
 	return 0;
 }
 
@ -114,7 +114,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
 {
 	size_t i;
-@@ -4450,6 +4544,7 @@ int spi_nor_scan(struct spi_nor *nor)
+@@ -4486,6 +4580,7 @@ int spi_nor_scan(struct spi_nor *nor)
 	nor->write = spi_nor_write_data;
 	nor->read_reg = spi_nor_read_reg;
 	nor->write_reg = spi_nor_write_reg;
--- a/package/boot/uboot-mediatek/patches/100-13-cmd-sf-add-support-to-read-flash-unique-ID.patch
+++ b/package/boot/uboot-mediatek/patches/100-13-cmd-sf-add-support-to-read-flash-unique-ID.patch
@ -1,14 +1,14 @@
-From e60939acbebd07161f3978d1c6f13123fdd2ebf2 Mon Sep 17 00:00:00 2001
+From 36d2aafec10998735f93b47a96a0f66c52484af7 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 11:27:02 +0800
-Subject: [PATCH 50/71] cmd: sf: add support to read flash unique ID
+Subject: [PATCH 13/30] cmd: sf: add support to read flash unique ID

 This patch adds support to display unique ID from spi-nor flashes

 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 ---
- cmd/sf.c | 13 ++++++++++++-
- 1 file changed, 12 insertions(+), 1 deletion(-)
+ cmd/sf.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)

 --- a/cmd/sf.c
 +++ b/cmd/sf.c
@ -36,14 +36,11 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 	else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test"))
 		ret = do_spi_flash_test(argc, argv);
 	else
-@@ -643,8 +653,9 @@ U_BOOT_LONGHELP(sf,
+@@ -638,6 +648,7 @@ U_BOOT_LONGHELP(sf,
+ 	"sf update addr offset|partition len	- erase and write `len' bytes from memory\n"
+ 	"					  at `addr' to flash at `offset'\n"
+ 	"					  or to start of mtd `partition'\n"
+	"sf uuid				- read uuid from flash\n"
+ #ifdef CONFIG_SPI_FLASH_LOCK
+ 	"sf protect lock/unlock sector len	- protect/unprotect 'len' bytes starting\n"
 	"					  at address 'sector'"
- #endif
- #ifdef CONFIG_CMD_SF_TEST
-	"\nsf test offset len		- run a very basic destructive test"
-+	"\nsf test offset len			- run a very basic destructive test"
- #endif
-+	"\nsf uuid					- read uuid from flash"
- 	);
- 
- U_BOOT_CMD(
--- a/package/boot/uboot-mediatek/patches/100-14-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch
+++ b/package/boot/uboot-mediatek/patches/100-14-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch
@ -1,7 +1,7 @@
-From 7ab891faaaf2b6126694352d4503dc40605a6aec Mon Sep 17 00:00:00 2001
+From d38f1f94531a792809f660ad5dcc4627eef1b9ec Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 15:10:02 +0800
-Subject: [PATCH 52/71] common: spl: spl_nand: enable
+Subject: [PATCH 14/30] common: spl: spl_nand: enable
 CONFIG_SYS_NAND_U_BOOT_OFFS undefined

 Enable using spl_nand with CONFIG_SYS_NAND_U_BOOT_OFFS undefined since
--- a/package/boot/uboot-mediatek/patches/100-16-board-mt7622-use-new-spi-nand-driver.patch
+++ b/package/boot/uboot-mediatek/patches/100-16-board-mt7622-use-new-spi-nand-driver.patch
@ -1,16 +1,15 @@
-From 4c1803cc08b1618d935c1386f43f43a4e9c97697 Mon Sep 17 00:00:00 2001
+From 3414e92ca55af9e4d0c20d93fcba0024ca35eb10 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Wed, 3 Mar 2021 10:51:43 +0800
-Subject: [PATCH 54/71] board: mt7622: use new spi-nand driver
+Subject: [PATCH 16/30] board: mt7622: use new spi-nand driver

 Enable new spi-nand driver support for mt7622_rfb_defconfig

 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 ---
- arch/arm/dts/mt7622-rfb.dts  |  7 +++++++
- arch/arm/dts/mt7622.dtsi     | 16 ++++++++++++++++
- configs/mt7622_rfb_defconfig |  5 +++++
- 3 files changed, 28 insertions(+)
+ arch/arm/dts/mt7622-rfb.dts |  7 +++++++
+ arch/arm/dts/mt7622.dtsi    | 16 ++++++++++++++++
+ 2 files changed, 23 insertions(+)

 --- a/arch/arm/dts/mt7622-rfb.dts
 +++ b/arch/arm/dts/mt7622-rfb.dts
@ -53,23 +52,3 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 	snor: snor@11014000 {
 		compatible = "mediatek,mtk-snor";
 		reg = <0x11014000 0x1000>;
--- a/configs/mt7622_rfb_defconfig
-+++ b/configs/mt7622_rfb_defconfig
-@@ -20,6 +20,7 @@ CONFIG_SYS_PROMPT="MT7622> "
- CONFIG_SYS_MAXARGS=8
- CONFIG_CMD_BOOTMENU=y
- CONFIG_CMD_MMC=y
-+CONFIG_CMD_MTD=y
- CONFIG_CMD_PCI=y
- CONFIG_CMD_SF_TEST=y
- CONFIG_CMD_PING=y
-@@ -37,6 +38,9 @@ CONFIG_CLK=y
- CONFIG_MMC_HS200_SUPPORT=y
- CONFIG_MMC_MTK=y
- CONFIG_MTD=y
-+CONFIG_DM_MTD=y
-+CONFIG_MTK_SPI_NAND=y
-+CONFIG_MTK_SPI_NAND_MTD=y
- CONFIG_DM_SPI_FLASH=y
- CONFIG_SPI_FLASH_EON=y
- CONFIG_SPI_FLASH_GIGADEVICE=y
--- a/package/boot/uboot-mediatek/patches/100-17-board-mt7981-add-reference-board-using-new-spi-nand-.patch
+++ b/package/boot/uboot-mediatek/patches/100-17-board-mt7981-add-reference-board-using-new-spi-nand-.patch
@ -1,7 +1,7 @@
-From d5841f8707dcb7a1f73607de67ab45dba93a56a4 Mon Sep 17 00:00:00 2001
+From 124ef4a79d8054f84c22a60d79ccd82646b6402a Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Fri, 29 Jul 2022 17:04:12 +0800
-Subject: [PATCH 55/71] board: mt7981: add reference board using new spi-nand
+Subject: [PATCH 17/30] board: mt7981: add reference board using new spi-nand
 driver

 Add a new reference board using new spi-nand driver for SPI-NAND flash on
@ -18,7 +18,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1136,6 +1136,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1119,6 +1119,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-bananapi-bpi-r64.dtb \
 	mt7623n-bananapi-bpi-r2.dtb \
 	mt7981-rfb.dtb \
@ -165,6 +165,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +++ b/configs/mt7981_snfi_nand_rfb_defconfig
@@ -0,0 +1,57 @@
 +CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
 +CONFIG_TEXT_BASE=0x41e00000
@ -172,6 +173,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +CONFIG_NR_DRAM_BANKS=1
 +CONFIG_ENV_SIZE=0x20000
 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-snfi-nand-rfb"
+CONFIG_SYS_PROMPT="MT7981> "
 +CONFIG_TARGET_MT7981=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
 +CONFIG_DEBUG_UART_CLOCK=40000000
@ -181,7 +183,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +CONFIG_DEFAULT_FDT_FILE="mt7981-snfi-nand-rfb"
 +CONFIG_LOGLEVEL=7
 +CONFIG_LOG=y
-+CONFIG_SYS_PROMPT="MT7981> "
 +CONFIG_SYS_CBSIZE=512
 +CONFIG_SYS_PBSIZE=1049
 +# CONFIG_BOOTM_NETBSD is not set
@ -211,7 +212,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +CONFIG_MTK_SPI_NAND=y
 +CONFIG_MTK_SPI_NAND_MTD=y
 +CONFIG_PHY_FIXED=y
-+CONFIG_DM_ETH=y
 +CONFIG_MEDIATEK_ETH=y
 +CONFIG_PINCTRL=y
 +CONFIG_PINCONF=y
--- a/package/boot/uboot-mediatek/patches/100-18-mtd-spi-nor-add-more-flash-ids.patch
+++ b/package/boot/uboot-mediatek/patches/100-18-mtd-spi-nor-add-more-flash-ids.patch
@ -1,15 +1,15 @@
-From a2df2df6fd1aec32572c7b30ccf5a184ec1763fd Mon Sep 17 00:00:00 2001
+From 56d3fcf9efe23f8334741d914f33c9351016d231 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Wed, 27 Jul 2022 16:32:17 +0800
-Subject: [PATCH 56/71] mtd: spi-nor: add more flash ids
+Subject: [PATCH 18/30] mtd: spi-nor: add more flash ids

 Add more spi-nor flash ids

 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 ---
 drivers/mtd/spi/spi-nor-core.c |  1 +
- drivers/mtd/spi/spi-nor-ids.c  | 23 ++++++++++++++++++++++-
- 2 files changed, 23 insertions(+), 1 deletion(-)
+ drivers/mtd/spi/spi-nor-ids.c  | 27 ++++++++++++++++++++++++++-
+ 2 files changed, 27 insertions(+), 1 deletion(-)

 --- a/drivers/mtd/spi/spi-nor-core.c
 +++ b/drivers/mtd/spi/spi-nor-core.c
@ -23,18 +23,19 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mtd/spi/spi-nor-ids.c
 +++ b/drivers/mtd/spi/spi-nor-ids.c
-@@ -83,7 +83,9 @@ const struct flash_info spi_nor_ids[] =
+@@ -83,7 +83,10 @@ const struct flash_info spi_nor_ids[] =
 	{ INFO("en25q32b",   0x1c3016, 0, 64 * 1024,   64, 0) },
 	{ INFO("en25q64",    0x1c3017, 0, 64 * 1024,  128, SECT_4K) },
 	{ INFO("en25q128b",  0x1c3018, 0, 64 * 1024,  256, 0) },
 -	{ INFO("en25qh128",  0x1c7018, 0, 64 * 1024,  256, 0) },
 +	{ INFO("en25qh128",  0x1c7018, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-+	{ INFO("en25qx128",  0x1c7118, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+	{ INFO("en25qx128a",  0x1c7118, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
 +	{ INFO("en25qh256",  0x1c7019, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("en25qx256a",  0x1c7119, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
 	{ INFO("en25s64",    0x1c3817, 0, 64 * 1024,  128, SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_GIGADEVICE	/* GIGADEVICE */
-@@ -149,6 +151,11 @@ const struct flash_info spi_nor_ids[] =
+@@ -149,6 +152,11 @@ const struct flash_info spi_nor_ids[] =
 	{INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096,	SECT_4K |
 	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
 	{
@ -46,7 +47,23 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 		INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
-@@ -520,6 +527,16 @@ const struct flash_info spi_nor_ids[] =
+@@ -257,6 +265,7 @@ const struct flash_info spi_nor_ids[] =
+ 	{ INFO("mx25u3235f",  0xc22536, 0, 4 * 1024,  1024, SECT_4K) },
+ 	{ INFO("mx25u6435f",  0xc22537, 0, 64 * 1024, 128, SECT_4K) },
+ 	{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) },
+	{ INFO("mx25l12833f", 0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ 	{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
+ 	{ INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
+ 	       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+@@ -265,6 +274,7 @@ const struct flash_info spi_nor_ids[] =
+ 	{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
+ 	{ INFO("mx25v8035f",  0xc22314, 0, 64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ 	{ INFO("mx25r1635f",  0xc22815, 0, 64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("mx25l25645g", 0xc22019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ 	{ INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
+ 	{ INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ 	{ INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+@@ -525,6 +535,16 @@ const struct flash_info spi_nor_ids[] =
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{
@ -63,7 +80,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 		INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
-@@ -583,6 +600,11 @@ const struct flash_info spi_nor_ids[] =
+@@ -588,6 +608,11 @@ const struct flash_info spi_nor_ids[] =
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
--- a/package/boot/uboot-mediatek/patches/100-19-mtd-spi-nand-add-more-spi-nand-chips.patch
+++ b/package/boot/uboot-mediatek/patches/100-19-mtd-spi-nand-add-more-spi-nand-chips.patch
@ -0,0 +1,296 @@
+From 001ce4e53f197a358b4307d36cc6d5048fc59158 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 27 Jul 2022 16:36:13 +0800
+Subject: [PATCH 19/30] mtd: spi-nand: add more spi-nand chips
+
+Support more spi-nand chips
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/mtd/nand/spi/Makefile     |   1 +
+ drivers/mtd/nand/spi/core.c       |   1 +
+ drivers/mtd/nand/spi/etron.c      | 181 ++++++++++++++++++++++++++++++
+ drivers/mtd/nand/spi/gigadevice.c |  38 +++++++
+ drivers/mtd/nand/spi/winbond.c    |   9 ++
+ include/linux/mtd/spinand.h       |   1 +
+ 6 files changed, 231 insertions(+)
+ create mode 100644 drivers/mtd/nand/spi/etron.c
+
+--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
+@@ -2,4 +2,5 @@
+ 
+ spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
+ spinand-objs += toshiba.o winbond.o xtx.o
+spinand-objs += etron.o
+ obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
+--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
+@@ -826,6 +826,7 @@ static const struct nand_ops spinand_ops
+ };
+ 
+ static const struct spinand_manufacturer *spinand_manufacturers[] = {
+	&etron_spinand_manufacturer,
+ 	&gigadevice_spinand_manufacturer,
+ 	&macronix_spinand_manufacturer,
+ 	&micron_spinand_manufacturer,
+--- /dev/null
+++ b/drivers/mtd/nand/spi/etron.c
+@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Etron Technology, Inc.
+ *
+ */
+#ifndef __UBOOT__
+#include <malloc.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/bug.h>
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_ETRON		0xD5
+
+#define STATUS_ECC_LIMIT_BITFLIPS (3 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int etron_ooblayout_ecc(struct mtd_info *mtd, int section,
+				  struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = (14 * section) + 72;
+	region->length = 14;
+
+	return 0;
+}
+
+static int etron_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	if (section) {
+		region->offset = 18 * section;
+		region->length = 18;
+	} else {
+		/* section 0 has one byte reserved for bad block mark */
+		region->offset = 2;
+		region->length = 16;
+	}
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops etron_ooblayout = {
+	.ecc = etron_ooblayout_ecc,
+	.rfree = etron_ooblayout_free,
+};
+
+static int etron_ecc_get_status(struct spinand_device *spinand,
+				   u8 status)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+
+	switch (status & STATUS_ECC_MASK) {
+	case STATUS_ECC_NO_BITFLIPS:
+		return 0;
+
+	case STATUS_ECC_UNCOR_ERROR:
+		return -EBADMSG;
+
+	case STATUS_ECC_HAS_BITFLIPS:
+		return nand->eccreq.strength >> 1;
+
+	case STATUS_ECC_LIMIT_BITFLIPS:
+		return nand->eccreq.strength;
+
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static const struct spinand_info etron_spinand_table[] = {
+	/* EM73C 1Gb 3.3V */
+	SPINAND_INFO("EM73C044VCF",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25),
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+	/* EM7xD 2Gb */
+	SPINAND_INFO("EM73D044VCR",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+	SPINAND_INFO("EM73D044VCO",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+	SPINAND_INFO("EM78D044VCM",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+	/* EM7xE 4Gb */
+	SPINAND_INFO("EM73E044VCE",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B),
+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+	SPINAND_INFO("EM78E044VCD",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F),
+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+	/* EM7xF044VCA 8Gb */
+	SPINAND_INFO("EM73F044VCA",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+	SPINAND_INFO("EM78F044VCA",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D),
+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer etron_spinand_manufacturer = {
+	.id = SPINAND_MFR_ETRON,
+	.name = "Etron",
+	.chips = etron_spinand_table,
+	.nchips = ARRAY_SIZE(etron_spinand_table),
+	.ops = &etron_spinand_manuf_ops,
+};
+--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
+@@ -284,7 +284,45 @@ static int gd5fxgq4ufxxg_ecc_get_status(
+ 	return -EINVAL;
+ }
+ 
+static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section,
+				  struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = (16 * section) + 8;
+	region->length = 8;
+
+	return 0;
+}
+
+static int esmt_1_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = (16 * section) + 2;
+	region->length = 6;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops esmt_1_ooblayout = {
+	.ecc = esmt_1_ooblayout_ecc,
+	.rfree = esmt_1_ooblayout_free,
+};
+
+ static const struct spinand_info gigadevice_spinand_table[] = {
+	SPINAND_INFO("F50L1G41LB",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)),
+ 	SPINAND_INFO("GD5F1GQ4xA",
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
+@@ -167,6 +167,15 @@ static const struct spinand_info winbond
+ 					      &update_cache_variants),
+ 		     0,
+ 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
+	SPINAND_INFO("W25N01KV",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
+ 	SPINAND_INFO("W25N02KV",
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
+@@ -244,6 +244,7 @@ struct spinand_manufacturer {
+ };
+ 
+ /* SPI NAND manufacturers */
+extern const struct spinand_manufacturer etron_spinand_manufacturer;
+ extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
+ extern const struct spinand_manufacturer macronix_spinand_manufacturer;
+ extern const struct spinand_manufacturer micron_spinand_manufacturer;
--- a/package/boot/uboot-mediatek/patches/100-20-mtd-spi-nand-add-support-for-FudanMicro-chips.patch
+++ b/package/boot/uboot-mediatek/patches/100-20-mtd-spi-nand-add-support-for-FudanMicro-chips.patch
@ -0,0 +1,154 @@
+From 83cd1b0984bf53da247eb8fca1119668eb0ba7ea Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 15 Jan 2025 14:41:03 +0800
+Subject: [PATCH 20/30] mtd: spi-nand: add support for FudanMicro chips
+
+Sdd support for FudanMicro SPI-NAND flashes
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/mtd/nand/spi/Makefile     |   1 +
+ drivers/mtd/nand/spi/core.c       |   1 +
+ drivers/mtd/nand/spi/fudanmicro.c | 107 ++++++++++++++++++++++++++++++
+ include/linux/mtd/spinand.h       |   1 +
+ 4 files changed, 110 insertions(+)
+ create mode 100644 drivers/mtd/nand/spi/fudanmicro.c
+
+--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
+@@ -3,4 +3,5 @@
+ spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
+ spinand-objs += toshiba.o winbond.o xtx.o
+ spinand-objs += etron.o
+spinand-objs += fudanmicro.o
+ obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
+--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
+@@ -827,6 +827,7 @@ static const struct nand_ops spinand_ops
+ 
+ static const struct spinand_manufacturer *spinand_manufacturers[] = {
+ 	&etron_spinand_manufacturer,
+	&fudan_spinand_manufacturer,
+ 	&gigadevice_spinand_manufacturer,
+ 	&macronix_spinand_manufacturer,
+ 	&micron_spinand_manufacturer,
+--- /dev/null
+++ b/drivers/mtd/nand/spi/fudanmicro.c
+@@ -0,0 +1,107 @@
+#ifndef __UBOOT__
+#include <malloc.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/bitops.h>
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_FUDAN		0xA1
+
+#define FM25S01B_STATUS_ECC_MASK		(7 << 4)
+#define STATUS_ECC_1_3_BITFLIPS	(1 << 4)
+#define STATUS_ECC_4_6_BITFLIPS	(3 << 4)
+#define STATUS_ECC_7_8_BITFLIPS	(5 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int fm25s01b_ooblayout_ecc(struct mtd_info *mtd, int section,
+				      struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	region->offset = 64;
+	region->length = 64;
+
+	return 0;
+}
+
+static int fm25s01b_ooblayout_free(struct mtd_info *mtd, int section,
+				       struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = (16 * section) + 4;
+	region->length = 12;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops fm25s01b_ooblayout = {
+	.ecc = fm25s01b_ooblayout_ecc,
+	.rfree = fm25s01b_ooblayout_free,
+};
+
+static int fm25s01b_ecc_get_status(struct spinand_device *spinand,
+				       u8 status)
+{
+	switch (status & FM25S01B_STATUS_ECC_MASK) {
+	case STATUS_ECC_NO_BITFLIPS:
+		return 0;
+
+	case STATUS_ECC_UNCOR_ERROR:
+		return -EBADMSG;
+
+	case STATUS_ECC_1_3_BITFLIPS:
+		return 3;
+
+	case STATUS_ECC_4_6_BITFLIPS:
+		return 6;
+
+	case STATUS_ECC_7_8_BITFLIPS:
+		return 8;
+
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static const struct spinand_info fudan_spinand_table[] = {
+	SPINAND_INFO("FM25s01B",
+			 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&fm25s01b_ooblayout,
+				     fm25s01b_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops fudan_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer fudan_spinand_manufacturer = {
+	.id = SPINAND_MFR_FUDAN,
+	.name = "FUDAN Micron",
+	.chips = fudan_spinand_table,
+	.nchips = ARRAY_SIZE(fudan_spinand_table),
+	.ops = &fudan_spinand_manuf_ops,
+};
+--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
+@@ -245,6 +245,7 @@ struct spinand_manufacturer {
+ 
+ /* SPI NAND manufacturers */
+ extern const struct spinand_manufacturer etron_spinand_manufacturer;
+extern const struct spinand_manufacturer fudan_spinand_manufacturer;
+ extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
+ extern const struct spinand_manufacturer macronix_spinand_manufacturer;
+ extern const struct spinand_manufacturer micron_spinand_manufacturer;
--- a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nand-add-CASN-page-support.patch
+++ b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nand-add-CASN-page-support.patch
--- a/package/boot/uboot-mediatek/patches/100-22-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
+++ b/package/boot/uboot-mediatek/patches/100-22-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
@ -1,7 +1,7 @@
-From 793bed29e78cc54d989333d756fef51efaca4e56 Mon Sep 17 00:00:00 2001
+From deccfea9a0f0aa889933073323764593fc2298f5 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Tue, 26 Jul 2022 09:29:18 +0800
-Subject: [PATCH 58/71] mmc: mtk-sd: add support to display verbose error log
+Subject: [PATCH 22/30] mmc: mtk-sd: add support to display verbose error log

 Add an option to enable debug log, and also display verbose error log for
 both command and data.
@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/drivers/mmc/Kconfig
 +++ b/drivers/mmc/Kconfig
-@@ -868,6 +868,14 @@ config MMC_MTK
+@@ -879,6 +879,14 @@ config MMC_MTK
 	  This is needed if support for any SD/SDIO/MMC devices is required.
 	  If unsure, say N.
 
@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 config FSL_SDHC_V2_3
 --- a/drivers/mmc/Makefile
 +++ b/drivers/mmc/Makefile
-@@ -85,3 +85,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
+@@ -86,3 +86,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
 obj-$(CONFIG_MMC_BCM2835)		+= bcm2835_sdhost.o
 obj-$(CONFIG_MMC_MTK)			+= mtk-sd.o
 obj-$(CONFIG_MMC_SDHCI_F_SDH30)		+= f_sdh30.o
--- a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
+++ b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
@ -1,550 +0,0 @@
-From 8d0665327819c41fce2c8d50f19c967b22eae564 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 27 Jul 2022 16:36:13 +0800
-Subject: [PATCH 57/71] mtd: spi-nand: backport from upstream kernel
-
-Backport new features from upstream kernel
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
- drivers/mtd/nand/spi/Kconfig      |   1 +
- drivers/mtd/nand/spi/Makefile     |   2 +-
- drivers/mtd/nand/spi/core.c       | 102 ++++++----
- drivers/mtd/nand/spi/etron.c      | 181 +++++++++++++++++
- drivers/mtd/nand/spi/gigadevice.c | 322 ++++++++++++++++++++++++++----
- drivers/mtd/nand/spi/macronix.c   | 173 +++++++++++++---
- drivers/mtd/nand/spi/micron.c     |  50 ++---
- drivers/mtd/nand/spi/toshiba.c    |  66 +++---
- drivers/mtd/nand/spi/winbond.c    | 164 ++++++++++++---
- include/linux/mtd/spinand.h       |  87 +++++---
- 10 files changed, 923 insertions(+), 225 deletions(-)
- create mode 100644 drivers/mtd/nand/spi/etron.c
-
--- a/drivers/mtd/nand/spi/Makefile
-+++ b/drivers/mtd/nand/spi/Makefile
-@@ -1,5 +1,5 @@
- # SPDX-License-Identifier: GPL-2.0
- 
-spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
-+spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o
- spinand-objs += toshiba.o winbond.o xtx.o
- obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -826,6 +826,7 @@ static const struct nand_ops spinand_ops
- };
- 
- static const struct spinand_manufacturer *spinand_manufacturers[] = {
-+	&etron_spinand_manufacturer,
- 	&gigadevice_spinand_manufacturer,
- 	&macronix_spinand_manufacturer,
- 	&micron_spinand_manufacturer,
--- /dev/null
-+++ b/drivers/mtd/nand/spi/etron.c
-@@ -0,0 +1,181 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2020 Etron Technology, Inc.
-+ *
-+ */
-+#ifndef __UBOOT__
-+#include <malloc.h>
-+#include <linux/device.h>
-+#include <linux/kernel.h>
-+#endif
-+#include <linux/bug.h>
-+#include <linux/mtd/spinand.h>
-+
-+#define SPINAND_MFR_ETRON		0xD5
-+
-+#define STATUS_ECC_LIMIT_BITFLIPS (3 << 4)
-+
-+static SPINAND_OP_VARIANTS(read_cache_variants,
-+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(write_cache_variants,
-+		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
-+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(update_cache_variants,
-+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
-+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
-+
-+static int etron_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (14 * section) + 72;
-+	region->length = 14;
-+
-+	return 0;
-+}
-+
-+static int etron_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	if (section) {
-+		region->offset = 18 * section;
-+		region->length = 18;
-+	} else {
-+		/* section 0 has one byte reserved for bad block mark */
-+		region->offset = 2;
-+		region->length = 16;
-+	}
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops etron_ooblayout = {
-+	.ecc = etron_ooblayout_ecc,
-+	.rfree = etron_ooblayout_free,
-+};
-+
-+static int etron_ecc_get_status(struct spinand_device *spinand,
-+				   u8 status)
-+{
-+	struct nand_device *nand = spinand_to_nand(spinand);
-+
-+	switch (status & STATUS_ECC_MASK) {
-+	case STATUS_ECC_NO_BITFLIPS:
-+		return 0;
-+
-+	case STATUS_ECC_UNCOR_ERROR:
-+		return -EBADMSG;
-+
-+	case STATUS_ECC_HAS_BITFLIPS:
-+		return nand->eccreq.strength >> 1;
-+
-+	case STATUS_ECC_LIMIT_BITFLIPS:
-+		return nand->eccreq.strength;
-+
-+	default:
-+		break;
-+	}
-+
-+	return -EINVAL;
-+}
-+
-+static const struct spinand_info etron_spinand_table[] = {
-+	/* EM73C 1Gb 3.3V */
-+	SPINAND_INFO("EM73C044VCF",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
-+	/* EM7xD 2Gb */
-+	SPINAND_INFO("EM73D044VCR",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
-+	SPINAND_INFO("EM73D044VCO",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
-+	SPINAND_INFO("EM78D044VCM",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
-+	/* EM7xE 4Gb */
-+	SPINAND_INFO("EM73E044VCE",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
-+	SPINAND_INFO("EM78E044VCD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
-+	/* EM7xF044VCA 8Gb */
-+	SPINAND_INFO("EM73F044VCA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
-+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
-+	SPINAND_INFO("EM78F044VCA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D),
-+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
-+};
-+
-+static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = {
-+};
-+
-+const struct spinand_manufacturer etron_spinand_manufacturer = {
-+	.id = SPINAND_MFR_ETRON,
-+	.name = "Etron",
-+	.chips = etron_spinand_table,
-+	.nchips = ARRAY_SIZE(etron_spinand_table),
-+	.ops = &etron_spinand_manuf_ops,
-+};
--- a/drivers/mtd/nand/spi/gigadevice.c
-+++ b/drivers/mtd/nand/spi/gigadevice.c
-@@ -43,6 +43,24 @@ static SPINAND_OP_VARIANTS(read_cache_va
- 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
- 
-+/* Q5 1Gb */
-+static SPINAND_OP_VARIANTS(dummy2_read_cache_variants,
-+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
-+/* Q5 2Gb & 4Gb */
-+static SPINAND_OP_VARIANTS(dummy4_read_cache_variants,
-+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
- static SPINAND_OP_VARIANTS(write_cache_variants,
- 		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
- 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
-@@ -268,7 +286,45 @@ static int gd5fxgq4ufxxg_ecc_get_status(
- 	return -EINVAL;
- }
- 
-+static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 8;
-+	region->length = 8;
-+
-+	return 0;
-+}
-+
-+static int esmt_1_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 2;
-+	region->length = 6;
-+
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops esmt_1_ooblayout = {
-+	.ecc = esmt_1_ooblayout_ecc,
-+	.rfree = esmt_1_ooblayout_free,
-+ };
-+
- static const struct spinand_info gigadevice_spinand_table[] = {
-+	SPINAND_INFO("F50L1G41LB",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
-+		          &write_cache_variants,
-+		          &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)),
- 	SPINAND_INFO("GD5F1GQ4xA",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-@@ -349,6 +405,87 @@ static const struct spinand_info gigadev
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- 				     gd5fxgq5xexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F2GQ5UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F4GQ6UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GM7UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F2GM7UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92),
-+			 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-+			 NAND_ECCREQ(8, 512),
-+			 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+			 SPINAND_HAS_QE_BIT,
-+			 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F4GM8UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95),
-+			 NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
-+			 NAND_ECCREQ(8, 512),
-+			 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+			 SPINAND_HAS_QE_BIT,
-+			 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ5UExxH",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
-+			 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+			 NAND_ECCREQ(4, 512),
-+			 SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+			 SPINAND_HAS_QE_BIT,
-+			 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F2GQ5UExxH",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
-+			 NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
-+			 NAND_ECCREQ(4, 512),
-+			 SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+			 SPINAND_HAS_QE_BIT,
-+			 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F4GQ6UExxH",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
-+			 NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1),
-+			 NAND_ECCREQ(4, 512),
-+			 SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+			 SPINAND_HAS_QE_BIT,
-+			 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+			     gd5fxgq5xexxg_ecc_get_status)),
-+
- };
- 
- static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
--- a/drivers/mtd/nand/spi/winbond.c
-+++ b/drivers/mtd/nand/spi/winbond.c
-@@ -18,6 +18,23 @@
- 
- #define WINBOND_CFG_BUF_READ		BIT(3)
- 
-+#define W25N02_N04KV_STATUS_ECC_MASK		(3 << 4)
-+#define W25N02_N04KV_STATUS_ECC_NO_BITFLIPS	(0 << 4)
-+#define W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS	(1 << 4)
-+#define W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS	(3 << 4)
-+#define W25N02_N04KV_STATUS_ECC_UNCOR_ERROR	(2 << 4)
-+
-+#define W25N01_M02GV_STATUS_ECC_MASK		(3 << 4)
-+#define W25N01_M02GV_STATUS_ECC_NO_BITFLIPS	(0 << 4)
-+#define W25N01_M02GV_STATUS_ECC_1_BITFLIPS	(1 << 4)
-+#define W25N01_M02GV_STATUS_ECC_UNCOR_ERROR	(2 << 4)
-+
-+#define W25N01KV_STATUS_ECC_MASK		(3 << 4)
-+#define W25N01KV_STATUS_ECC_NO_BITFLIPS		(0 << 4)
-+#define W25N01KV_STATUS_ECC_1_3_BITFLIPS	(1 << 4)
-+#define W25N01KV_STATUS_ECC_4_BITFLIPS		(3 << 4)
-+#define W25N01KV_STATUS_ECC_UNCOR_ERROR		(2 << 4)
-+
- static SPINAND_OP_VARIANTS(read_cache_variants,
- 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-@@ -34,6 +51,35 @@ static SPINAND_OP_VARIANTS(update_cache_
- 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
- 
-+static int w25n02kv_n04kv_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 64;
-+	region->length = 16;
-+
-+	return 0;
-+}
-+
-+static int w25n02kv_n04kv_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 2;
-+	region->length = 14;
-+
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops w25n02kv_n04kv_ooblayout = {
-+	.ecc = w25n02kv_n04kv_ooblayout_ecc,
-+	.rfree = w25n02kv_n04kv_ooblayout_free,
-+};
-+
- static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
- 				  struct mtd_oob_region *region)
- {
-@@ -106,6 +152,58 @@ static const struct mtd_ooblayout_ops w2
- 	.rfree = w25n02kv_ooblayout_free,
- };
- 
-+static int w25n01kv_ecc_get_status(struct spinand_device *spinand,
-+					u8 status)
-+{
-+	switch (status & W25N01KV_STATUS_ECC_MASK) {
-+	case W25N01KV_STATUS_ECC_NO_BITFLIPS:
-+		return 0;
-+
-+	case W25N01KV_STATUS_ECC_1_3_BITFLIPS:
-+		return 3;
-+
-+	case W25N01KV_STATUS_ECC_4_BITFLIPS:
-+		return 4;
-+
-+	case W25N01KV_STATUS_ECC_UNCOR_ERROR:
-+		return -EBADMSG;
-+
-+	default:
-+		break;
-+	}
-+
-+	return -EINVAL;
-+}
-+
-+static int w25n02kv_n04kv_ecc_get_status(struct spinand_device *spinand,
-+					u8 status)
-+{
-+	switch (status & W25N02_N04KV_STATUS_ECC_MASK) {
-+	case W25N02_N04KV_STATUS_ECC_NO_BITFLIPS:
-+		return 0;
-+
-+	case W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS:
-+		return 3;
-+
-+	case W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS:
-+		return 4;
-+
-+	/* W25N02_N04KV_use internal 8bit ECC algorithm.
-+	 * But the ECC strength is 4 bit requried.
-+	 * Return 3 if the bit bit flip count less than 5.
-+	 * Return 4 if the bit bit flip count more than 5 to 8.
-+	*/
-+
-+	case W25N02_N04KV_STATUS_ECC_UNCOR_ERROR:
-+		return -EBADMSG;
-+
-+	default:
-+		break;
-+	}
-+
-+	return -EINVAL;
-+}
-+
- static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
- 				   u8 status)
- {
-@@ -163,6 +261,15 @@ static const struct spinand_info winbond
- 					      &update_cache_variants),
- 		     0,
- 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
-+	SPINAND_INFO("W25N01KV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)),
- 	SPINAND_INFO("W25N02KV",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
-@@ -172,6 +279,16 @@ static const struct spinand_info winbond
- 					      &update_cache_variants),
- 		     0,
- 		     SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
-+	SPINAND_INFO("W25N04KV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
-+				     w25n02kv_n04kv_ecc_get_status)),
- };
- 
- static int winbond_spinand_init(struct spinand_device *spinand)
--- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -244,6 +244,7 @@ struct spinand_manufacturer {
- };
- 
- /* SPI NAND manufacturers */
-+extern const struct spinand_manufacturer etron_spinand_manufacturer;
- extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
- extern const struct spinand_manufacturer macronix_spinand_manufacturer;
- extern const struct spinand_manufacturer micron_spinand_manufacturer;
--- a/package/boot/uboot-mediatek/patches/100-23-cmd-ubi-make-volume-find-create-remove-APIs-public.patch
+++ b/package/boot/uboot-mediatek/patches/100-23-cmd-ubi-make-volume-find-create-remove-APIs-public.patch
@ -1,7 +1,7 @@
-From dd66fc817f7ab7a4fcab9836a9251a8f64f329df Mon Sep 17 00:00:00 2001
+From 3873a7f91bdfaa918b1593196df1da2de41662f4 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 16:58:36 +0800
-Subject: [PATCH 59/71] cmd: ubi: make volume find/create/remove APIs public
+Subject: [PATCH 23/30] cmd: ubi: make volume find/create/remove APIs public

 Export ubi_create_vol/ubi_find_volume/ubi_remove_vol to public so that they
 can be used by other programs.
--- a/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch
+++ b/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch
@ -1,7 +1,7 @@
-From f6a4130959af1e6d13d616203e42ed3c894666ad Mon Sep 17 00:00:00 2001
+From 98ac40f08a59a18198a676a5419bdc72d484c150 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 17:00:00 +0800
-Subject: [PATCH 60/71] cmd: ubi: allow creating volume with all free spaces
+Subject: [PATCH 24/30] cmd: ubi: allow creating volume with all free spaces

 Allow creating volume with all free spaces by giving a negative size value.

--- a/package/boot/uboot-mediatek/patches/100-25-env-ubi-add-support-to-create-environment-volume-if-.patch
+++ b/package/boot/uboot-mediatek/patches/100-25-env-ubi-add-support-to-create-environment-volume-if-.patch
@ -1,7 +1,7 @@
-From fc0c70a7c6a088072d0c77e5a59d5e9b7754c6db Mon Sep 17 00:00:00 2001
+From e1ea321b028c2af81770c55aa5f1f319228e9a39 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 17:01:20 +0800
-Subject: [PATCH 61/71] env: ubi: add support to create environment volume if
+Subject: [PATCH 25/30] env: ubi: add support to create environment volume if
 it does not exist

 Add an option to allow environment volume being auto created if not exist.
@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -701,6 +701,12 @@ config ENV_UBI_VOLUME_REDUND
+@@ -687,6 +687,12 @@ config ENV_UBI_VOLUME_REDUND
 	help
 	  Name of the redundant volume that you want to store the environment in.
 
@ -48,7 +48,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
 static int env_ubi_load(void)
 {
-@@ -134,6 +146,10 @@ static int env_ubi_load(void)
+@@ -134,6 +146,11 @@ static int env_ubi_load(void)
 		return -EIO;
 	}
 
@ -56,10 +56,11 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME);
 +		env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME_REDUND);
 +	}
+
 	read1_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)tmp_env1, 0,
 				     CONFIG_ENV_SIZE);
 	if (read1_fail)
-@@ -171,6 +187,9 @@ static int env_ubi_load(void)
+@@ -171,6 +188,9 @@ static int env_ubi_load(void)
 		return -EIO;
 	}
 
--- a/package/boot/uboot-mediatek/patches/100-26-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch
+++ b/package/boot/uboot-mediatek/patches/100-26-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch
@ -1,7 +1,7 @@
-From 189a2fe96931ef3ea0e187c8e9bfa589c2a0ae10 Mon Sep 17 00:00:00 2001
+From 501b4d1a43ce6bce4e8fa07ba164af1eec05c8be Mon Sep 17 00:00:00 2001
 From: Weijie Gao <weijie.gao@mediatek.com>
 Date: Mon, 25 Jul 2022 17:24:56 +0800
-Subject: [PATCH 62/71] mtd: ubi: add support for UBI end-of-filesystem marker
+Subject: [PATCH 26/30] mtd: ubi: add support for UBI end-of-filesystem marker
 used by OpenWrt

 Add support for UBI end-of-filesystem marker used by OpenWrt to allow
--- a/package/boot/uboot-mediatek/patches/100-27-net-phy-aquantia-add-support-to-use-embedded-firmwar.patch
+++ b/package/boot/uboot-mediatek/patches/100-27-net-phy-aquantia-add-support-to-use-embedded-firmwar.patch
--- a/package/boot/uboot-mediatek/patches/100-28-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
+++ b/package/boot/uboot-mediatek/patches/100-28-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
--- a/package/boot/uboot-mediatek/patches/100-29-net-phy-add-Marvell-CUX3410.patch
+++ b/package/boot/uboot-mediatek/patches/100-29-net-phy-add-Marvell-CUX3410.patch
@ -0,0 +1,32 @@
+From cedc08e33bf608765464dd80ce3cc170a636a3dd Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Thu, 16 Jan 2025 09:13:10 +0800
+Subject: [PATCH 29/30] net: phy: add Marvell CUX3410
+
+Add support for Marvell CUX3410 ethernet PHY
+
+Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
+---
+ drivers/net/phy/aquantia.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
+@@ -744,3 +744,17 @@ U_BOOT_PHY_DRIVER(aqr412) = {
+ 	.shutdown = &gen10g_shutdown,
+ 	.data = AQUANTIA_GEN3,
+ };
+
+U_BOOT_PHY_DRIVER(cux3410) = {
+	.name = "Marvell CUX3410",
+	.uid = 0x31c31dd3,
+	.mask = 0xfffffff0,
+	.features = PHY_10G_FEATURES,
+	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
+		 MDIO_MMD_PHYXS | MDIO_MMD_AN |
+		 MDIO_MMD_VEND1),
+	.config = &aquantia_config,
+	.startup = &aquantia_startup,
+	.shutdown = &gen10g_shutdown,
+	.data = AQUANTIA_GEN3,
+};
--- a/package/boot/uboot-mediatek/patches/100-30-net-phy-add-support-for-MediaTek-built-in-2.5Gbps-PH.patch
+++ b/package/boot/uboot-mediatek/patches/100-30-net-phy-add-support-for-MediaTek-built-in-2.5Gbps-PH.patch
--- a/package/boot/uboot-mediatek/patches/101-01-mtd-spinand-add-support-for-FORESEE-F35SQA002G.patch
+++ b/package/boot/uboot-mediatek/patches/101-01-mtd-spinand-add-support-for-FORESEE-F35SQA002G.patch
@ -20,16 +20,17 @@ Link: https://lore.kernel.org/linux-mtd/20231002140458.147605-1-mmkurbanov@salut

 --- a/drivers/mtd/nand/spi/Makefile
 +++ b/drivers/mtd/nand/spi/Makefile
-@@ -1,5 +1,5 @@
+@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 
-spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o
-+spinand-objs := core.o esmt.o foresee.o etron.o gigadevice.o macronix.o micron.o paragon.o
+-spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o
+spinand-objs := core.o esmt.o foresee.o gigadevice.o macronix.o micron.o paragon.o
 spinand-objs += toshiba.o winbond.o xtx.o
- obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
+ spinand-objs += etron.o
+ spinand-objs += fudanmicro.o
 --- a/drivers/mtd/nand/spi/core.c
 +++ b/drivers/mtd/nand/spi/core.c
-@@ -834,6 +834,7 @@ static const struct spinand_manufacturer
+@@ -895,6 +895,7 @@ static const struct spinand_manufacturer
 	&toshiba_spinand_manufacturer,
 	&winbond_spinand_manufacturer,
 	&esmt_c8_spinand_manufacturer,
@ -139,7 +140,7 @@ Link: https://lore.kernel.org/linux-mtd/20231002140458.147605-1-mmkurbanov@salut
 +};
 --- a/include/linux/mtd/spinand.h
 +++ b/include/linux/mtd/spinand.h
-@@ -252,6 +252,7 @@ extern const struct spinand_manufacturer
+@@ -306,6 +306,7 @@ extern const struct spinand_manufacturer
 extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
 extern const struct spinand_manufacturer winbond_spinand_manufacturer;
 extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
--- a/package/boot/uboot-mediatek/patches/101-03-mtd-spinand-fix-support-for-FORESEE.patch
+++ b/package/boot/uboot-mediatek/patches/101-03-mtd-spinand-fix-support-for-FORESEE.patch
@ -6,7 +6,7 @@ Signed-off-by: Dim Fish <dimfish@gmail.com>

 --- a/drivers/mtd/nand/spi/foresee.c
 +++ b/drivers/mtd/nand/spi/foresee.c
-@@ -22,8 +22,8 @@ static SPINAND_OP_VARIANTS(write_cache_v
+@@ -24,8 +24,8 @@ static SPINAND_OP_VARIANTS(write_cache_v
 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
 
 static SPINAND_OP_VARIANTS(update_cache_variants,
--- a/package/boot/uboot-mediatek/patches/104-snfi-add-support-for-GD5F1GQ5UE.patch
+++ b/package/boot/uboot-mediatek/patches/104-snfi-add-support-for-GD5F1GQ5UE.patch
@ -0,0 +1,26 @@
+From ec8c3dc701cfd53e1ddc9817041e710fb4bbb0f3 Mon Sep 17 00:00:00 2001
+From: Chuanhong Guo <gch981213@gmail.com>
+Date: Sat, 9 Mar 2024 12:06:31 +0800
+Subject: [PATCH] snfi: add support for GD5F1GQ5UE
+
+This patch adds support for GigaDevice GD5F1GQ5UExxG to the
+mtk-snfi driver in u-boot.
+
+Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
+---
+ drivers/mtd/mtk-snand/mtk-snand-ids.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/mtd/mtk-snand/mtk-snand-ids.c
+++ b/drivers/mtd/mtk-snand/mtk-snand-ids.c
+@@ -115,6 +115,10 @@ static const struct snand_flash_info sna
+ 		   SNAND_MEMORG_1G_2K_64,
+ 		   &snand_cap_read_from_cache_quad_q2d,
+ 		   &snand_cap_program_load_x4),
+	SNAND_INFO("GD5F1GQ5UExxG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x51),
+		   SNAND_MEMORG_1G_2K_128,
+		   &snand_cap_read_from_cache_quad,
+		   &snand_cap_program_load_x4),
+ 	SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2),
+ 		   SNAND_MEMORG_2G_2K_128,
+ 		   &snand_cap_read_from_cache_quad_q2d,
--- a/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch
+++ b/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch
@ -12,29 +12,15 @@
 CONFIG_REGMAP=y
 --- a/configs/mt7981_snfi_nand_rfb_defconfig
 +++ b/configs/mt7981_snfi_nand_rfb_defconfig
-@@ -1,11 +1,12 @@
- CONFIG_ARM=y
-+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
- CONFIG_POSITION_INDEPENDENT=y
- CONFIG_ARCH_MEDIATEK=y
+@@ -5,7 +5,6 @@ CONFIG_ARCH_MEDIATEK=y
 CONFIG_TEXT_BASE=0x41e00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
 -CONFIG_ENV_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="mt7981-snfi-nand-rfb"
-+CONFIG_SYS_PROMPT="MT7981> "
+ CONFIG_SYS_PROMPT="MT7981> "
 CONFIG_TARGET_MT7981=y
- CONFIG_DEBUG_UART_BASE=0x11002000
- CONFIG_DEBUG_UART_CLOCK=40000000
-@@ -15,7 +16,6 @@ CONFIG_DEBUG_UART=y
- CONFIG_DEFAULT_FDT_FILE="mt7981-snfi-nand-rfb"
- CONFIG_LOGLEVEL=7
- CONFIG_LOG=y
-CONFIG_SYS_PROMPT="MT7981> "
- CONFIG_SYS_CBSIZE=512
- CONFIG_SYS_PBSIZE=1049
- # CONFIG_BOOTM_NETBSD is not set
-@@ -29,8 +29,6 @@ CONFIG_CMD_GPIO=y
+@@ -30,8 +29,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SMC=y
@ -43,14 +29,6 @@
 CONFIG_CMD_UBI=y
 CONFIG_CMD_UBI_RENAME=y
 CONFIG_ENV_OVERWRITE=y
-@@ -45,7 +43,6 @@ CONFIG_DM_MTD=y
- CONFIG_MTK_SPI_NAND=y
- CONFIG_MTK_SPI_NAND_MTD=y
- CONFIG_PHY_FIXED=y
-CONFIG_DM_ETH=y
- CONFIG_MEDIATEK_ETH=y
- CONFIG_PINCTRL=y
- CONFIG_PINCONF=y
@@ -55,3 +52,4 @@ CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_SERIAL=y
 CONFIG_MTK_SERIAL=y
--- a/package/boot/uboot-mediatek/patches/109-snfi-FM35Q1GA-is-x4-only.patch
+++ b/package/boot/uboot-mediatek/patches/109-snfi-FM35Q1GA-is-x4-only.patch
@ -0,0 +1,24 @@
+From a6487e393b1b073ba0895e10f00d0fbb2a5e88d9 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 8 Apr 2024 19:35:27 +0100
+Subject: [PATCH 2/2] snfi: FM35Q1GA is x4-only
+
+Dont allow x2 read and cache read operations on FM35Q1GA as they seem
+to be unstable. Also the Linux drivers does not allow x2 ops.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/mtk-snand/mtk-snand-ids.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/mtk-snand/mtk-snand-ids.c
+++ b/drivers/mtd/mtk-snand/mtk-snand-ids.c
+@@ -431,7 +431,7 @@ static const struct snand_flash_info sna
+ 
+ 	SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
+ 		   SNAND_MEMORG_1G_2K_64,
+-		   &snand_cap_read_from_cache_x4,
+		   &snand_cap_read_from_cache_x4_only,
+ 		   &snand_cap_program_load_x4),
+ 
+ 	SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),
--- a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch
+++ b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch
--- a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch
+++ b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch
@ -1,24 +0,0 @@
--- a/tools/image-host.c
-+++ b/tools/image-host.c
-@@ -1175,6 +1175,7 @@ static int fit_config_add_verification_d
-  * 2) get public key (X509_get_pubkey)
-  * 3) provide der format (d2i_RSAPublicKey)
-  */
-+#ifdef CONFIG_TOOLS_LIBCRYPTO
- static int read_pub_key(const char *keydir, const void *name,
- 			unsigned char **pubkey, int *pubkey_len)
- {
-@@ -1228,6 +1229,13 @@ err_cert:
- 	fclose(f);
- 	return ret;
- }
-+#else
-+static int read_pub_key(const char *keydir, const void *name,
-+			unsigned char **pubkey, int *pubkey_len)
-+{
-+	return -ENOSYS;
-+}
-+#endif
- 
- int fit_pre_load_data(const char *keydir, void *keydest, void *fit)
- {
--- a/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
+++ b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
--- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
+++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
@ -1,17 +1,16 @@
 --- a/cmd/bootm.c
 +++ b/cmd/bootm.c
-@@ -260,6 +260,67 @@ U_BOOT_CMD(
+@@ -260,6 +260,76 @@ U_BOOT_CMD(
 /* iminfo - print header info for a requested image */
 /*******************************************************************/
 #if defined(CONFIG_CMD_IMI)
-+#if defined(CONFIG_FIT)
 +#define SECTOR_SHIFT 9
 +static int image_totalsize(struct cmd_tbl *cmdtp, int flag, int argc,
 +			   char *const argv[], short int in_blocks)
 +{
 +	ulong addr;
-+	void *fit;
-+	int bsize, tsize;
+	void *hdr;
+	uint32_t bsize, tsize = 0;
 +	char buf[16];
 +
 +	if (argc >= 2)
@ -19,9 +18,20 @@
 +	else
 +		addr = image_load_addr;
 +
-+	fit = (void *)map_sysmem(addr, 0);
-+	tsize = fit_get_totalsize(fit);
-+	unmap_sysmem(fit);
+	hdr = (void *)map_sysmem(addr, 0);
+
+	switch (genimg_get_format(hdr)) {
+	case IMAGE_FORMAT_LEGACY:
+		if(CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT))
+			tsize = image_get_image_size(hdr);
+		break;
+	case IMAGE_FORMAT_FIT:
+		if(CONFIG_IS_ENABLED(FIT))
+			tsize = fit_get_totalsize(hdr);
+		break;
+	}
+
+	unmap_sysmem(hdr);
 +	if (tsize == 0)
 +		return 1;
 +
@ -64,7 +74,6 @@
 +	"addr [maxhdrlen] [varname]\n"
 +);
 +
-+#endif
 static int do_iminfo(struct cmd_tbl *cmdtp, int flag, int argc,
 		     char *const argv[])
 {
--- a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
+++ b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
@ -1,6 +1,6 @@
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -707,6 +707,12 @@ config CMD_ENV_EXISTS
+@@ -709,6 +709,12 @@ config CMD_ENV_EXISTS
 	  Check if a variable is defined in the environment for use in
 	  shell scripting.
 
--- a/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch
+++ b/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch
@ -6,6 +6,6 @@
 	lbaint_t blk = 0, blk_r = 0;
 -	int timeout_ms = 1000;
 +	int timeout_ms = blkcnt;
+ 	u32 grpcnt;
+ 
 
- 	if (!mmc)
- 		return -1;
--- a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch
+++ b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch
@ -16,7 +16,7 @@ Reviewed-by: Tom Rini <trini@konsulko.com>

 --- a/boot/image-fdt.c
 +++ b/boot/image-fdt.c
-@@ -613,6 +613,12 @@ int image_setup_libfdt(struct bootm_head
+@@ -614,6 +614,12 @@ int image_setup_libfdt(struct bootm_head
 					images->fit_uname_cfg,
 					strlen(images->fit_uname_cfg) + 1, 1);
 
--- a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch
+++ b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch
@ -48,7 +48,7 @@
 #ifdef CONFIG_ENABLE_NAND_NMBM
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
-@@ -170,4 +170,11 @@ config MTK_TZ_MOVABLE
+@@ -165,4 +165,11 @@ config MTK_TZ_MOVABLE
 	select OF_SYSTEM_SETUP
 	bool
 
--- a/package/boot/uboot-mediatek/patches/407-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
+++ b/package/boot/uboot-mediatek/patches/407-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
@ -1,33 +0,0 @@
-From 93d7086edb0db4b05149dfea21a2a82d8f160944 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Sat, 6 Mar 2021 16:29:33 +0800
-Subject: [PATCH 10/12] configs: mt7622: enable environment for mt7622_rfb
-
-Enable environment vairables for mt7622_rfb
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
- configs/mt7622_rfb_defconfig | 5 +++++
- 1 file changed, 5 insertions(+)
-
--- a/configs/mt7622_rfb_defconfig
-+++ b/configs/mt7622_rfb_defconfig
-@@ -5,6 +5,8 @@ CONFIG_ARCH_MEDIATEK=y
- CONFIG_TEXT_BASE=0x41e00000
- CONFIG_SYS_MALLOC_F_LEN=0x4000
- CONFIG_NR_DRAM_BANKS=1
-+CONFIG_ENV_SIZE=0x20000
-+CONFIG_ENV_OFFSET=0x280000
- CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb"
- CONFIG_SYS_LOAD_ADDR=0x4007ff28
- CONFIG_DEBUG_UART_BASE=0x11002000
-@@ -26,6 +28,9 @@ CONFIG_CMD_SF_TEST=y
- CONFIG_CMD_PING=y
- CONFIG_CMD_SMC=y
- CONFIG_ENV_OVERWRITE=y
-+CONFIG_ENV_IS_IN_MTD=y
-+CONFIG_ENV_MTD_NAME="spi-nand0"
-+CONFIG_ENV_SIZE_REDUND=0x40000
- CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
- CONFIG_USE_IPADDR=y
- CONFIG_IPADDR="192.168.1.1"
--- a/package/boot/uboot-mediatek/patches/408-arm-mediatek-add-back-mt7622-LK-image-header.patch
+++ b/package/boot/uboot-mediatek/patches/408-arm-mediatek-add-back-mt7622-LK-image-header.patch
@ -0,0 +1,24 @@
+From 1845b514511398cc0ba219a47958f078a2f7f67d Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Tue, 8 Jul 2025 19:50:53 +0800
+Subject: [PATCH] arm: mediatek: add back mt7622 LK image header
+
+The LK image header was lost since commit df3ab898f644
+("arm: mediatek: merge board Kconfigs into mach-mediatek").
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/arm/mach-mediatek/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
+@@ -158,7 +158,7 @@ config MTK_BROM_HEADER_INFO
+ 	string
+ 	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629
+ 	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
+-	default "lk=1" if TARGET_MT7623
+	default "lk=1" if TARGET_MT7622 || TARGET_MT7623
+ 
+ config MTK_TZ_MOVABLE
+ 	select ARCH_MISC_INIT
--- a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
+++ b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
@ -331,7 +331,7 @@
 +};
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1134,6 +1134,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1117,6 +1117,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-rfb.dtb \
 	mt7623a-unielec-u7623-02-emmc.dtb \
 	mt7622-bananapi-bpi-r64.dtb \
--- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
+++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
@ -742,7 +742,7 @@
 +};
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1135,6 +1135,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1118,6 +1118,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7623a-unielec-u7623-02-emmc.dtb \
 	mt7622-bananapi-bpi-r64.dtb \
 	mt7622-linksys-e8450-ubi.dtb \
@ -920,7 +920,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-@@ -402,6 +403,20 @@ static int initr_onenand(void)
+@@ -423,6 +424,20 @@ static int initr_onenand(void)
 }
 #endif
 
@ -941,13 +941,13 @@
 #ifdef CONFIG_MMC
 static int initr_mmc(void)
 {
-@@ -710,6 +725,9 @@ static init_fnc_t init_sequence_r[] = {
- #ifdef CONFIG_NMBM_MTD
- 	initr_nmbm,
+@@ -735,6 +750,9 @@ static void initcall_run_r(void)
+ #if CONFIG_IS_ENABLED(NMBM_MTD)
+ 	INITCALL(initr_nmbm);
 #endif
-+#ifdef CONFIG_SPI_FLASH
-+	initr_spiflash,
+#if CONFIG_IS_ENABLED(SPI_FLASH)
+	INITCALL(initr_spiflash);
 +#endif
- #ifdef CONFIG_MMC
- 	initr_mmc,
+ #if CONFIG_IS_ENABLED(MMC)
+ 	INITCALL(initr_mmc);
 #endif
--- a/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch
+++ b/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch
@ -22,7 +22,7 @@ Subject: [PATCH] add support for RAVPower RP-WD009

 --- a/arch/mips/dts/Makefile
 +++ b/arch/mips/dts/Makefile
-@@ -26,6 +26,7 @@ dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += m
+@@ -25,6 +25,7 @@ dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += m
 dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
--- a/package/boot/uboot-mediatek/patches/452-add-xiaomi-redmi-ax6s.patch
+++ b/package/boot/uboot-mediatek/patches/452-add-xiaomi-redmi-ax6s.patch
@ -15,7 +15,7 @@ Subject: [PATCH] add xiaomi redmi ax6s

 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1137,6 +1137,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1120,6 +1120,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-linksys-e8450-ubi.dtb \
 	mt7622-ubnt-unifi-6-lr.dtb \
 	mt7622-ubnt-unifi-6-lr-v3.dtb \
--- a/package/boot/uboot-mediatek/patches/457-initialized-the-watchdog-subsystem-later.patch
+++ b/package/boot/uboot-mediatek/patches/457-initialized-the-watchdog-subsystem-later.patch
@ -13,42 +13,42 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>

 --- a/common/board_r.c
 +++ b/common/board_r.c
-@@ -681,19 +681,13 @@ static init_fnc_t init_sequence_r[] = {
- 	serial_initialize,
- 	initr_announce,
- 	dm_announce,
+@@ -691,19 +691,13 @@ static void initcall_run_r(void)
+ 	INITCALL(serial_initialize);
+ 	INITCALL(initr_announce);
+ 	INITCALL(dm_announce);
 -#if CONFIG_IS_ENABLED(WDT)
-	initr_watchdog,
+-	INITCALL(initr_watchdog);
 -#endif
-	INIT_FUNC_WATCHDOG_RESET
- 	arch_initr_trap,
- #if defined(CONFIG_BOARD_EARLY_INIT_R)
- 	board_early_init_r,
+-	WATCHDOG_RESET();
+ 	INITCALL(arch_initr_trap);
+ #if CONFIG_IS_ENABLED(BOARD_EARLY_INIT_R)
+ 	INITCALL(board_early_init_r);
 #endif
-	INIT_FUNC_WATCHDOG_RESET
- #ifdef CONFIG_POST
- 	post_output_backlog,
+-	WATCHDOG_RESET();
+ #if CONFIG_IS_ENABLED(POST)
+ 	INITCALL(post_output_backlog);
 #endif
-	INIT_FUNC_WATCHDOG_RESET
- #if defined(CONFIG_PCI_INIT_R) && defined(CONFIG_SYS_EARLY_PCI_INIT)
+-	WATCHDOG_RESET();
+ #if CONFIG_IS_ENABLED(PCI_INIT_R) && CONFIG_IS_ENABLED(SYS_EARLY_PCI_INIT)
 	/*
 	 * Do early PCI configuration _before_ the flash gets initialised,
-@@ -708,7 +702,6 @@ static init_fnc_t init_sequence_r[] = {
- #ifdef CONFIG_MTD_NOR_FLASH
- 	initr_flash,
+@@ -718,7 +712,6 @@ static void initcall_run_r(void)
+ #if CONFIG_IS_ENABLED(MTD_NOR_FLASH)
+ 	INITCALL(initr_flash);
 #endif
-	INIT_FUNC_WATCHDOG_RESET
- #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86)
+-	WATCHDOG_RESET();
+ #if CONFIG_IS_ENABLED(PPC) || CONFIG_IS_ENABLED(M68K) || CONFIG_IS_ENABLED(X86)
 	/* initialize higher level parts of CPU like time base and timers */
- 	cpu_init_r,
-@@ -737,6 +730,10 @@ static init_fnc_t init_sequence_r[] = {
- #ifdef CONFIG_PVBLOCK
- 	initr_pvblock,
+ 	INITCALL(cpu_init_r);
+@@ -744,6 +737,10 @@ static void initcall_run_r(void)
+ #if CONFIG_IS_ENABLED(PVBLOCK)
+ 	INITCALL(initr_pvblock);
 #endif
 +#if CONFIG_IS_ENABLED(WDT)
-+	initr_watchdog,
+	INITCALL(initr_watchdog);
 +#endif
-+	INIT_FUNC_WATCHDOG_RESET
- 	initr_env,
- #ifdef CONFIG_SYS_MALLOC_BOOTPARAMS
- 	initr_malloc_bootparams,
+	WATCHDOG_RESET();
+ 	INITCALL(initr_env);
+ #if CONFIG_IS_ENABLED(SYS_MALLOC_BOOTPARAMS)
+ 	INITCALL(initr_malloc_bootparams);
--- a/package/kernel/linux/modules/i2c.mk
+++ b/package/kernel/linux/modules/i2c.mk
@ -169,7 +169,7 @@ define KernelPackage/i2c-hid
  $(call i2c_defaults,$(I2C_HID_MODULES),60)
  TITLE:=I2C HID support
  KCONFIG+= CONFIG_I2C_HID
-  DEPENDS:=+kmod-hid
+  DEPENDS:=+kmod-drm +kmod-hid
  HIDDEN:=1
 endef

--- a/package/kernel/linux/modules/input.mk
+++ b/package/kernel/linux/modules/input.mk
@ -246,3 +246,71 @@ define KernelPackage/input-uinput/description
 endef

 $(eval $(call KernelPackage,input-uinput))
+
+
+define KernelPackage/input-mouse-ps2
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=PS/2 mouse support
+  DEPENDS:=+kmod-i2c-core +kmod-input-core +kmod-input-serio-libps2
+  KCONFIG:= \
+	CONFIG_INPUT_MOUSE=y \
+	CONFIG_MOUSE_PS2 \
+	CONFIG_MOUSE_PS2_ALPS=y \
+	CONFIG_MOUSE_PS2_BYD=y \
+	CONFIG_MOUSE_PS2_LOGIPS2PP=y \
+	CONFIG_MOUSE_PS2_SYNAPTICS=y \
+	CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y \
+	CONFIG_MOUSE_PS2_CYPRESS=y \
+	CONFIG_MOUSE_PS2_LIFEBOOK=y \
+	CONFIG_MOUSE_PS2_TRACKPOINT=y \
+	CONFIG_MOUSE_PS2_ELANTECH=y \
+	CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y \
+	CONFIG_MOUSE_PS2_SENTELIC=y \
+	CONFIG_MOUSE_PS2_TOUCHKIT=y \
+	CONFIG_MOUSE_PS2_OLPC=y \
+	CONFIG_MOUSE_PS2_FOCALTECH=y \
+	CONFIG_MOUSE_PS2_VMMOUSE=y
+  FILES:=$(LINUX_DIR)/drivers/input/mouse/psmouse.ko
+  AUTOLOAD:=$(call AutoProbe,psmouse)
+endef
+
+define KernelPackage/input-mouse-ps2/description
+  Support for standard 2 or 3-button PS/2 mouse, as well as PS/2
+  mice with wheels and extra buttons, Microsoft, Logitech or Genius
+  compatible, and many touchpads as well.
+endef
+
+$(eval $(call KernelPackage,input-mouse-ps2))
+
+
+define KernelPackage/input-serio
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=Serial I/O support
+  KCONFIG:= CONFIG_SERIO
+  FILES:=$(LINUX_DIR)/drivers/input/serio/serio.ko
+  AUTOLOAD:=$(call AutoProbe,serio,1)
+endef
+
+define KernelPackage/input-serio/description
+ Kernel module to support input device that uses serial I/O to
+ communicate with the system
+endef
+
+$(eval $(call KernelPackage,input-serio))
+
+
+define KernelPackage/input-serio-libps2
+  SUBMENU:=$(INPUT_MODULES_MENU)
+  TITLE:=PS/2 Serial I/O support
+  DEPENDS:=+kmod-input-serio
+  KCONFIG:= CONFIG_SERIO_LIBPS2
+  FILES:=$(LINUX_DIR)/drivers/input/serio/libps2.ko
+  AUTOLOAD:=$(call AutoProbe,libps2,1)
+endef
+
+define KernelPackage/input-serio-libps2/description
+ Kernel module to support devices connected to a PS/2 port, such
+ as PS/2 mouse or standard AT keyboard.
+endef
+
+$(eval $(call KernelPackage,input-serio-libps2))
--- a/target/linux/generic/config-6.12
+++ b/target/linux/generic/config-6.12
@ -3738,6 +3738,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MOST is not set
 # CONFIG_MOTORCOMM_PHY is not set
 # CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
 # CONFIG_MOUSE_ELAN_I2C is not set
 # CONFIG_MOUSE_GPIO is not set
 # CONFIG_MOUSE_INPORT is not set
@ -3745,8 +3747,10 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MOUSE_PC110PAD is not set
 # CONFIG_MOUSE_PS2_FOCALTECH is not set
 # CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_SERIAL is not set
 # CONFIG_MOUSE_SYNAPTICS_I2C is not set
 # CONFIG_MOUSE_SYNAPTICS_USB is not set
+# CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_MOXTET is not set
 # CONFIG_MPL115 is not set
 # CONFIG_MPL115_I2C is not set
@ -5810,6 +5814,7 @@ CONFIG_SERIAL_EARLYCON=y
 # CONFIG_SERIO_RAW is not set
 # CONFIG_SERIO_SERPORT is not set
 # CONFIG_SERIO_SUN4I_PS2 is not set
+# CONFIG_SERIO_XILINX_XPS_PS2 is not set
 # CONFIG_SFC is not set
 # CONFIG_SFC_FALCON is not set
 # CONFIG_SFC_SIENA is not set
--- a/target/linux/generic/config-6.6
+++ b/target/linux/generic/config-6.6
@ -3625,7 +3625,10 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MOST is not set
 # CONFIG_MOTORCOMM_PHY is not set
+# CONFIG_MOUSE_SERIAL is not set
 # CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
 # CONFIG_MOUSE_ELAN_I2C is not set
 # CONFIG_MOUSE_GPIO is not set
 # CONFIG_MOUSE_INPORT is not set
@ -3635,6 +3638,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MOUSE_PS2_SENTELIC is not set
 # CONFIG_MOUSE_SYNAPTICS_I2C is not set
 # CONFIG_MOUSE_SYNAPTICS_USB is not set
+# CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_MOXTET is not set
 # CONFIG_MPL115 is not set
 # CONFIG_MPL115_I2C is not set
@ -5651,6 +5655,7 @@ CONFIG_SERIAL_EARLYCON=y
 # CONFIG_SERIO_RAW is not set
 # CONFIG_SERIO_SERPORT is not set
 # CONFIG_SERIO_SUN4I_PS2 is not set
+# CONFIG_SERIO_XILINX_XPS_PS2 is not set
 # CONFIG_SFC is not set
 # CONFIG_SFC_FALCON is not set
 # CONFIG_SFC_SIENA is not set
--- a/target/linux/mediatek/image/mt7622.mk
+++ b/target/linux/mediatek/image/mt7622.mk
@ -260,6 +260,9 @@ define Device/mediatek_mt7622-rfb1
  DEVICE_MODEL := MTK7622 rfb1 AP
  DEVICE_DTS := mt7622-rfb1
  DEVICE_PACKAGES := kmod-ata-ahci-mtk kmod-btmtkuart kmod-usb3
+  UBOOT_PATH := $(STAGING_DIR_IMAGE)/mt7622_rfb1-u-boot-mtk.bin
+  ARTIFACTS := u-boot.bin
+  ARTIFACT/u-boot.bin := append-uboot
 endef
 TARGET_DEVICES += mediatek_mt7622-rfb1

@ -279,6 +282,9 @@ define Device/mediatek_mt7622-rfb1-ubi
  IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \
                check-size $$$$(IMAGE_SIZE)
  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+  UBOOT_PATH := $(STAGING_DIR_IMAGE)/mt7622_rfb1-u-boot-mtk.bin
+  ARTIFACTS := u-boot.bin
+  ARTIFACT/u-boot.bin := append-uboot
 endef
 TARGET_DEVICES += mediatek_mt7622-rfb1-ubi

--- a/target/linux/mediatek/image/mt7629.mk
+++ b/target/linux/mediatek/image/mt7629.mk
@ -7,6 +7,9 @@ define Device/mediatek_mt7629-rfb
  DEVICE_MODEL := MT7629 rfb AP
  DEVICE_DTS := mt7629-rfb
  DEVICE_PACKAGES := swconfig
+  UBOOT_PATH := $(STAGING_DIR_IMAGE)/mt7629_rfb-u-boot-mtk.bin
+  ARTIFACTS := u-boot.bin
+  ARTIFACT/u-boot.bin := append-uboot
 endef
 TARGET_DEVICES += mediatek_mt7629-rfb
Author	SHA1	Message	Date
Shiji Yang	7b4ee9b17d	arm-trusted-firmware-mediatek: update to new release 20250711 Update mediatek arm-trusted-firmware to the latest version. Remove upstream patch: 0004-mediatek-snfi-fix-return-code-when-reading.patch Signed-off-by: Shiji Yang <yangshiji66@outlook.com>	2025-07-19 02:59:16 +01:00
Shiji Yang	332645a610	uboot-mediatek: sync with mtk-openwrt/u-boot 20250711 - Backport upstream Winbond W25N04KV Flash support. - Backport upstream GigaDevice series Flash support. - Backport pending Airoha AN8855 switch TPID value fix. - Backport Mediatek UART baudrate accuracy compensation support. - Pull mtk patchset from MTK SDK mtksoc-20250711 branch: Remove mt7622_rfb changes. The MTK SDK already dropped them. Replace Airoha ethernet PHY driver with new version. Split downstream snfi changes into independent patches. Add new Marvell CUX3410 PHY driver. Add new MediaTek built-in 2.5Gbps PHY driver. Signed-off-by: Shiji Yang <yangshiji66@outlook.com>	2025-07-19 02:59:16 +01:00
Shiji Yang	bbd3db4c57	uboot-mediatek: drop build without OpenSSL fix The build error has been fixed by the upstream commit: 03e598263e38 ("tools: fix build without LIBCRYPTO support") Signed-off-by: Shiji Yang <yangshiji66@outlook.com>	2025-07-19 02:59:16 +01:00
Shiji Yang	bc62080529	uboot-mediatek: support getting legacy uImage size Most ramips target devices use the legacy uImage format. This patch extends the imsz/imszb commands to support detecting the image size of legacy uImage. Signed-off-by: Shiji Yang <yangshiji66@outlook.com>	2025-07-19 02:59:16 +01:00
Shiji Yang	f8c0da8525	mediatek: stage mt7622/mt7629 rfb u-boot images to bin folder These u-boot images are no longer automatically copied to the bindir since commit: `ed50004319` ("uboot-mediatek: add support for Linksys E8450") Signed-off-by: Shiji Yang <yangshiji66@outlook.com>	2025-07-19 02:59:16 +01:00
Shiji Yang	ce659cba14	uboot-mediatek: fix mt7622 rfb1 build Add back the default LK image header to generate u-boot-mtk.bin. This is the default behavior before u-boot v2022.01. If "u-boot-mtk.bin" doesn't boot, please try "u-boot.bin" and report it. Signed-off-by: Shiji Yang <yangshiji66@outlook.com>	2025-07-19 02:59:15 +01:00
Shiji Yang	41a9c9de66	uboot-mediatek: update to v2025.07 Update to the latest version. Suppressed patch: 100-04-env-add-support-for-generic-MTD-device.patch[1] [1] `03fb08d4ae` Signed-off-by: Shiji Yang <yangshiji66@outlook.com>	2025-07-19 02:59:15 +01:00
Daniel Golle	c5a6dc31d2	kernel: modules: input: add modules for PS/2 mouse support Package kernel modules for PS/2 mouse support, mostly to allow using touchpads and trackpoints built-into laptops (many of those are connected using classic i8052-compatible PS/2 I/O). Signed-off-by: Daniel Golle <daniel@makrotopia.org>	2025-07-19 02:56:26 +01:00
Daniel Golle	719c9059b2	kernel: add missing dependency on kmod-drm to kmod-i2c-hid Buildbot revealed that on the x86/geode target, on which CONFIG_DRM=y isn't set, kmod-i2c-hid misses the dependency on kmod-drm. Fix that to fix the build for x86/geode. Fixes: `c83e275c9b` ("kernel: package modules for I2C HID devices") Signed-off-by: Daniel Golle <daniel@makrotopia.org>	2025-07-19 02:53:22 +01:00