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Author SHA1 Message Date
Yanase Yuki
ce81918d4b projectsmirrors: drop ftp.kddilabs.jp
ftp.kddilabs.jp has been shutdown and
now returns 404.

Signed-off-by: Yanase Yuki <dev@zpc.st>
Link: https://github.com/openwrt/openwrt/pull/19407
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2025-07-19 00:28:01 +02:00
Rosen Penev
b0df4795b1 apm821xx: enable kernel 6.12
It builds now.

Tested on Cisco Meraki MX60W.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18798
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2025-07-19 00:01:12 +02:00
Rosen Penev
4a30ded7e6 apm821xx: refresh 6.12 kernel config
Some symbols changed.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18798
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2025-07-19 00:01:12 +02:00
Rosen Penev
38fd269993 apm821xx: refresh 6.12 patches
pci driver went to a different directory and thus manually edited.

All else done with kernel_oldconfig.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18798
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2025-07-19 00:01:12 +02:00
Rosen Penev
623a200bfc apm821xx: restore 6.6 kernel config/patches
Copy kernel config and patches from 6.12 to restore the default 6.6
kernel support files.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18798
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2025-07-19 00:01:12 +02:00
Rosen Penev
d15ed1614d apm821xx: rename kernel config/patches to 6.12
This is a preparation for 6.12 kernel support. It can help us
track the files history by using the Git tool.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18798
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2025-07-19 00:01:12 +02:00
Markus Stockhausen
963ee6ac3f realtek: avoid interrupt storm on mass packet receive
RTL83xx devices have two types of receive interrupts for each of its
8 rings. One for packet received and another for ring overflow. When
the switch is flooded with incoming packets the receive handler will
disable the packet receive notification but still keeps the overflow
notification enabled. While the receive path "slowly" processes the
received packets each new packet triggers the overflow IRQ again. The
device becomes unresponsive and eventually produces messages like:

[18441.709764] rcu: Stack dump where RCU GP kthread last ran:
[18441.727892] Sending NMI from CPU 1 to CPUs 0:
[18441.742300] NMI backtrace for cpu 0 skipped: idling at 0x8080e994
[18415.251700] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[18415.271350] rcu:     0-...!: (0 ticks this GP) idle=d740/0/0x0 ...
[18415.303046] rcu:     (detected by 1, t=6004 jiffies, g=230925, ...
[18415.326095] Sending NMI from CPU 1 to CPUs 0:
[18415.340540] NMI backtrace for cpu 0

Fix this issue by always disabling receive and overflow interrupts at
the same time.

Test with hping3 --udp -p 5021 -d 1400 --flood 192.168.2.72

Before (3sec run):
[183260.324846] rtl838x-eth 1b00a300.ethernet eth0: RX buffer overrun: status 0x101, mask: 0x7ffeff
[183260.340524] rtl838x-eth 1b00a300.ethernet eth0: RX buffer overrun: status 0x1, mask: 0x7ffeff
[183260.345799] net_ratelimit: 489997 callbacks suppressed

After (3 sec run):
[  373.981479] rtl838x-eth 1b00a300.ethernet eth0: rx ring overrun: status 0x101, mask: 0x7fffff
[  374.031118] rtl838x-eth 1b00a300.ethernet eth0: rx ring overrun: status 0x101, mask: 0x7fffff
[  377.919996] net_ratelimit: 34 callbacks suppressed

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19365
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2025-07-18 23:52:54 +02:00
Markus Stockhausen
926ffa10b4 realtek: simplify RTL8218B/RTL8214Fx detection
The current implementation has several issues:

- it uses the hacky phy_port* macros
- it uses SoC dependent raw pages
- it disables/enables SoC dependent polling

Get rid of these dependencies and access the mdio bus the normal way.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19372
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2025-07-18 23:36:51 +02:00
11 changed files with 465 additions and 66 deletions

View file

@ -29,7 +29,6 @@
"https://ftpmirror.gnu.org",
"https://mirror.csclub.uwaterloo.ca/gnu",
"https://mirror.netcologne.de/gnu",
"https://ftp.kddilabs.jp/GNU/gnu",
"https://www.nic.funet.fi/pub/gnu/gnu",
"https://mirror.navercorp.com/gnu",
"https://mirrors.rit.edu/gnu",

View file

@ -10,6 +10,7 @@ FEATURES:=fpu dt gpio ramdisk squashfs usb
SUBTARGETS:=nand sata
KERNEL_PATCHVER:=6.6
KERNEL_TESTING_PATCHVER:=6.12
define Target/Description
Build images for AppliedMicro APM821xx based boards.

View file

@ -0,0 +1,281 @@
# CONFIG_440_CPU is not set
CONFIG_44x=y
CONFIG_464_CPU=y
CONFIG_4xx=y
# CONFIG_ADVANCED_OPTIONS is not set
CONFIG_APM821xx=y
# CONFIG_APOLLO3G is not set
# CONFIG_ARCHES is not set
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_ARCH_MMAP_RND_BITS=11
CONFIG_ARCH_MMAP_RND_BITS_MAX=17
CONFIG_ARCH_MMAP_RND_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_PKEY_BITS=5
CONFIG_ARCH_SPLIT_ARG64=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y
CONFIG_AUDIT_ARCH=y
# CONFIG_BAMBOO is not set
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_BLK_MQ_PCI=y
CONFIG_BLUESTONE=y
CONFIG_BOOKE=y
CONFIG_BOOKE_WDT=y
# CONFIG_CANYONLANDS is not set
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
CONFIG_COMMON_CLK=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CRC16=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
CONFIG_CRYPTO_JITTERENTROPY_OSR=1
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
# CONFIG_CRYPTO_MD5_PPC is not set
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
# CONFIG_CRYPTO_SHA1_PPC is not set
CONFIG_CRYPTO_SHA3=y
CONFIG_DATA_SHIFT=12
CONFIG_DEBUG_INFO=y
CONFIG_DMADEVICES=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_NEED_SYNC=y
CONFIG_DMA_OF=y
CONFIG_DTC=y
CONFIG_DW_DMAC=y
CONFIG_DW_DMAC_CORE=y
CONFIG_EARLY_PRINTK=y
# CONFIG_EBONY is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
# CONFIG_EIGER is not set
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXTRA_TARGETS="uImage"
CONFIG_FIXED_PHY=y
CONFIG_FORCE_NR_CPUS=y
CONFIG_FORCE_PCI=y
# CONFIG_FSL_LBC is not set
CONFIG_FS_IOMAP=y
CONFIG_FUNCTION_ALIGNMENT=4
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
# CONFIG_GEN_RTC is not set
# CONFIG_GLACIER is not set
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IBM_IIC=y
CONFIG_IBM_EMAC=y
CONFIG_IBM_EMAC_EMAC4=y
CONFIG_IBM_EMAC_POLL_WEIGHT=32
CONFIG_IBM_EMAC_RGMII=y
CONFIG_IBM_EMAC_RXB=128
CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256
CONFIG_IBM_EMAC_TAH=y
CONFIG_IBM_EMAC_TXB=128
# CONFIG_ICON is not set
# CONFIG_IDPF is not set
CONFIG_ILLEGAL_POINTER_VALUE=0
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_ISA_DMA_API=y
# CONFIG_JFFS2_FS is not set
# CONFIG_KATMAI is not set
CONFIG_KERNEL_START=0xc0000000
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOWMEM_SIZE=0x30000000
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MATH_EMULATION is not set
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MIGRATION=y
CONFIG_MMU_GATHER_MERGE_VMAS=y
CONFIG_MMU_GATHER_PAGE_SIZE=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_SIZE=1
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
# CONFIG_MTD_CFI_GEOMETRY is not set
# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NET_EGRESS=y
CONFIG_NET_INGRESS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_XGRESS=y
CONFIG_NOT_COHERENT_CACHE=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=1
CONFIG_NR_IRQS=512
CONFIG_NVMEM=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_U_BOOT_ENV=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_GPIO_MM_GPIOCHIP=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND=y
CONFIG_PACKING=y
CONFIG_PAGE_OFFSET=0xc0000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_ARCH_FALLBACKS=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYSICAL_START=0x00000000
CONFIG_PHYS_64BIT=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_PMU_SYSFS is not set
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_PPC44x_SIMPLE=y
CONFIG_PPC4xx_GPIO=y
CONFIG_PPC4xx_PCI_EXPRESS=y
# CONFIG_PPC64 is not set
# CONFIG_PPC_47x is not set
# CONFIG_PPC_85xx is not set
# CONFIG_PPC_8xx is not set
CONFIG_PPC_ADV_DEBUG_DACS=2
CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y
CONFIG_PPC_ADV_DEBUG_DVCS=2
CONFIG_PPC_ADV_DEBUG_IACS=4
CONFIG_PPC_ADV_DEBUG_REGS=y
# CONFIG_PPC_BOOK3S_32 is not set
CONFIG_PPC_DCR=y
CONFIG_PPC_DCR_NATIVE=y
# CONFIG_PPC_EARLY_DEBUG is not set
CONFIG_PPC_FPU=y
CONFIG_PPC_FPU_REGS=y
CONFIG_PPC_INDIRECT_PCI=y
CONFIG_PPC_KUAP=y
# CONFIG_PPC_KUAP_DEBUG is not set
CONFIG_PPC_KUEP=y
CONFIG_PPC_MMU_NOHASH=y
# CONFIG_PPC_PCI_BUS_NUM_DOMAIN_DEPENDENT is not set
CONFIG_PPC_UDBG_16550=y
CONFIG_PPC_WERROR=y
CONFIG_PTE_64BIT=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
# CONFIG_RAINIER is not set
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGULATOR=y
CONFIG_RSEQ=y
# CONFIG_SAM440EP is not set
# CONFIG_SCOM_DEBUGFS is not set
# CONFIG_SEQUOIA is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SGL_ALLOC=y
CONFIG_SMT_NUM_THREADS_DYNAMIC=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSE_IRQ=y
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
# CONFIG_STATIC_CALL_SELFTEST is not set
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
# CONFIG_TAISHAN is not set
CONFIG_TARGET_CPU="464"
CONFIG_TARGET_CPU_BOOL=y
CONFIG_TASK_SIZE=0xc0000000
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_THREAD_SHIFT=13
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TINY_SRCU=y
# CONFIG_TOOLCHAIN_DEFAULT_CPU is not set
CONFIG_USB_SUPPORT=y
CONFIG_VDSO32=y
CONFIG_VDSO_GETRANDOM=y
# CONFIG_VIRTIO_MENU is not set
# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
# CONFIG_WARP is not set
CONFIG_WATCHDOG_CORE=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_XZ_DEC_POWERPC=y
# CONFIG_YOSEMITE is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

View file

@ -0,0 +1,30 @@
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -118,6 +118,17 @@ config CANYONLANDS
help
This option enables support for the AMCC PPC460EX evaluation board.
+config APOLLO3G
+ bool "Apollo3G"
+ depends on 44x
+ default n
+ select PPC44x_SIMPLE
+ select APM821xx
+ select IBM_EMAC_RGMII
+ select 460EX
+ help
+ This option enables support for the AMCC Apollo 3G board.
+
config GLACIER
bool "Glacier"
depends on 44x
--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
@@ -46,6 +46,7 @@ machine_device_initcall(ppc44x_simple, p
* board.c file for it rather than adding it to this list.
*/
static char *board[] __initdata = {
+ "amcc,apollo3g",
"amcc,arches",
"amcc,bamboo",
"apm,bluestone",

View file

@ -0,0 +1,51 @@
--- a/arch/powerpc/platforms/44x/pci.c
+++ b/arch/powerpc/platforms/44x/pci.c
@@ -1058,15 +1058,24 @@ static int __init apm821xx_pciex_init_po
u32 val;
/*
- * Do a software reset on PCIe ports.
- * This code is to fix the issue that pci drivers doesn't re-assign
- * bus number for PCIE devices after Uboot
- * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
- * PT quad port, SAS LSI 1064E)
+ * Only reset the PHY when no link is currently established.
+ * This is for the Atheros PCIe board which has problems to establish
+ * the link (again) after this PHY reset. All other currently tested
+ * PCIe boards don't show this problem.
*/
-
- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
- mdelay(10);
+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
+ if (!(val & 0x00001000)) {
+ /*
+ * Do a software reset on PCIe ports.
+ * This code is to fix the issue that pci drivers doesn't re-assign
+ * bus number for PCIE devices after Uboot
+ * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
+ * PT quad port, SAS LSI 1064E)
+ */
+
+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
+ mdelay(10);
+ }
if (port->endpoint)
val = PTYPE_LEGACY_ENDPOINT << 20;
@@ -1083,9 +1092,12 @@ static int __init apm821xx_pciex_init_po
mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
- mdelay(50);
- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
+ if (!(val & 0x00001000)) {
+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
+ mdelay(50);
+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
+ }
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |

View file

@ -0,0 +1,14 @@
--- a/arch/powerpc/platforms/44x/pci.c
+++ b/arch/powerpc/platforms/44x/pci.c
@@ -1800,9 +1800,9 @@ static void __init ppc4xx_configure_pcie
* if it works
*/
out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
- out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
+ out_le32(mbase + PECFG_PIM0LAH, 0x00000008);
out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
- out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
+ out_le32(mbase + PECFG_PIM1LAH, 0x0000000c);
out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
out_le32(mbase + PECFG_PIM01SAL, 0x00000000);

View file

@ -0,0 +1,29 @@
From c9395ad54e2cabb87d408becc37566f3d8248933 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 1 Dec 2019 02:08:23 +0100
Subject: [PATCH] powerpc: bootwrapper: force gzip as mkimage's compression
method
Due to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to
instruct the mkimage to use the xz compression, which isn't
supported. This patch forces the gzip compression, which is
supported and doesn't matter because the generated uImage for
the apm821xx target gets ignored as the OpenWrt toolchain will
do separate U-Boot kernel images for each device individually.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/powerpc/boot/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -271,7 +271,7 @@ compressor-$(CONFIG_KERNEL_LZO) := lzo
# args (to if_changed): 1 = (this rule), 2 = platform, 3 = dts 4=dtb 5=initrd
quiet_cmd_wrap = WRAP $@
- cmd_wrap =$(CONFIG_SHELL) $(wrapper) -Z $(compressor-y) -c -o $@ -p $2 \
+ cmd_wrap =$(CONFIG_SHELL) $(wrapper) -Z gzip -c -o $@ -p $2 \
$(CROSSWRAP) $(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) \
vmlinux

View file

@ -1,43 +1,52 @@
CONFIG_APOLLO3G=y
CONFIG_ATA=y
CONFIG_ATA_BMDMA=y
CONFIG_ATA_SFF=y
CONFIG_BCM_NET_PHYLIB=y
CONFIG_BLK_DEV_DM=y
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_MD=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_STACKING=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BROADCOM_PHY=y
CONFIG_BUFFER_HEAD=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_MD5_PPC=y
CONFIG_CRYPTO_SHA1_PPC=y
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_INIT is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_SNAPSHOT is not set
CONFIG_EXT4_FS=y
CONFIG_F2FS_FS=y
CONFIG_FREEZER=y
CONFIG_FS_MBCACHE=y
CONFIG_FW_CACHE=y
CONFIG_GLOB=y
CONFIG_GPIO_74XX_MMIO=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_JBD2=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_MD=y
CONFIG_MD_AUTODETECT=y
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_MULTIPATH is not set
CONFIG_MD_RAID0=y
CONFIG_MD_RAID1=y
# CONFIG_MD_RAID10 is not set
# CONFIG_MD_RAID456 is not set
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_PHYSMAP=y
CONFIG_NLS=y
CONFIG_PCIE_PME=y
CONFIG_PM=y
CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_CLK=y
CONFIG_PM_SLEEP=y
# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_GC=y
CONFIG_PM_WAKELOCKS_LIMIT=100
CONFIG_PPC4xx_CPM=y
CONFIG_PPC_EARLY_DEBUG=y
# CONFIG_PPC_EARLY_DEBUG_16550 is not set
CONFIG_PPC_EARLY_DEBUG_44x=y
@ -46,10 +55,11 @@ CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0xef600300
# CONFIG_PPC_EARLY_DEBUG_MEMCONS is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_SATA_DWC=y
# CONFIG_SATA_DWC_DEBUG is not set
# CONFIG_SATA_DWC_OLD_DMA is not set
CONFIG_SATA_HOST=y
CONFIG_SATA_PMP=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
CONFIG_SG_POOL=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_USB=y

View file

@ -452,28 +452,25 @@ static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)
struct net_device *ndev = dev_id;
struct rtl838x_eth_priv *priv = netdev_priv(ndev);
u32 status = sw_r32(priv->r->dma_if_intr_sts);
unsigned long ring, rings;
netdev_dbg(ndev, "RX IRQ received: %08x\n", status);
netdev_dbg(ndev, "rx interrupt received, status %08x\n", status);
if ((status & RTL83XX_DMA_IF_INTR_STS_RX_RUN_OUT_MASK) && net_ratelimit())
netdev_warn(ndev, "RX buffer overrun: status 0x%x, mask: 0x%x\n",
status, sw_r32(priv->r->dma_if_intr_msk));
if (status & RTL83XX_DMA_IF_INTR_RX_RUN_OUT_MASK)
if (net_ratelimit())
netdev_warn(ndev, "rx ring overrun, status 0x%08x, mask 0x%08x\n",
status, sw_r32(priv->r->dma_if_intr_msk));
if (status & RTL83XX_DMA_IF_INTR_STS_RX_DONE_MASK) {
/* Disable rx interrupts */
sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);
for (int i = 0; i < priv->rxrings; i++) {
if (status & BIT(i + 8)) {
pr_debug("Scheduling queue: %d\n", i);
napi_schedule(&priv->rx_qs[i].napi);
}
}
rings = FIELD_GET(RTL83XX_DMA_IF_INTR_RX_DONE_MASK, status);
for_each_set_bit(ring, &rings, priv->rxrings) {
netdev_dbg(ndev, "schedule rx ring %lu\n", ring);
sw_w32_mask(RTL83XX_DMA_IF_INTR_RX_MASK(ring), 0, priv->r->dma_if_intr_msk);
napi_schedule(&priv->rx_qs[ring].napi);
}
if ((status & RTL83XX_DMA_IF_INTR_STS_NOTIFY_MASK) && priv->family_id == RTL8390_FAMILY_ID)
if (status & RTL839X_DMA_IF_INTR_NOTIFY_MASK)
rtl839x_l2_notification_handler(priv);
/* Acknowledge all interrupts */
sw_w32(status, priv->r->dma_if_intr_sts);
return IRQ_HANDLED;
@ -1353,25 +1350,22 @@ static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
{
struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi);
struct rtl838x_eth_priv *priv = rx_q->priv;
int ring = rx_q->id;
int work_done = 0;
int r = rx_q->id;
int work;
while (work_done < budget) {
work = rtl838x_hw_receive(priv->netdev, r, budget - work_done);
int work = rtl838x_hw_receive(priv->netdev, ring, budget - work_done);
if (!work)
break;
work_done += work;
}
if (work_done < budget) {
napi_complete_done(napi, work_done);
/* Enable RX interrupt */
if (work_done < budget && napi_complete_done(napi, work_done)) {
/* Re-enable rx interrupts */
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
else
sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk);
sw_w32_mask(0, RTL83XX_DMA_IF_INTR_RX_MASK(ring), priv->r->dma_if_intr_msk);
}
return work_done;

View file

@ -48,9 +48,10 @@
#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
#define RTL931X_MAC_FORCE_MODE_CTRL (0x0dcc)
#define RTL83XX_DMA_IF_INTR_STS_NOTIFY_MASK GENMASK(22, 20)
#define RTL83XX_DMA_IF_INTR_STS_RX_DONE_MASK GENMASK(15, 8)
#define RTL83XX_DMA_IF_INTR_STS_RX_RUN_OUT_MASK GENMASK(7, 0)
#define RTL839X_DMA_IF_INTR_NOTIFY_MASK GENMASK(22, 20)
#define RTL83XX_DMA_IF_INTR_RX_DONE_MASK GENMASK(15, 8)
#define RTL83XX_DMA_IF_INTR_RX_RUN_OUT_MASK GENMASK(7, 0)
#define RTL83XX_DMA_IF_INTR_RX_MASK(ring) (BIT(ring) | BIT(ring + 8))
/* MAC address settings */
#define RTL838X_MAC (0xa9ec)

View file

@ -22,10 +22,8 @@ extern struct rtl83xx_soc_info soc_info;
extern struct mutex smi_lock;
extern int phy_package_port_write_paged(struct phy_device *phydev, int port, int page, u32 regnum, u16 val);
extern int phy_package_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val);
extern int phy_port_write_paged(struct phy_device *phydev, int port, int page, u32 regnum, u16 val);
extern int phy_package_port_read_paged(struct phy_device *phydev, int port, int page, u32 regnum);
extern int phy_package_read_paged(struct phy_device *phydev, int page, u32 regnum);
extern int phy_port_read_paged(struct phy_device *phydev, int port, int page, u32 regnum);
#define PHY_PAGE_2 2
#define PHY_PAGE_4 4
@ -157,9 +155,9 @@ static int resume_polling(u64 saved_state)
static int rtl821x_match_phy_device(struct phy_device *phydev)
{
u64 poll_state;
int rawpage, port = phydev->mdio.addr & ~3;
int oldpage, chip_mode, chip_cfg_mode;
int oldpage, oldxpage, chip_mode, chip_cfg_mode;
struct mii_bus *bus = phydev->mdio.bus;
int addr = phydev->mdio.addr & ~3;
if (phydev->phy_id == PHY_ID_RTL8218B_E)
return PHY_IS_RTL8218B_E;
@ -167,36 +165,27 @@ static int rtl821x_match_phy_device(struct phy_device *phydev)
if (phydev->phy_id != PHY_ID_RTL8214_OR_8218)
return PHY_IS_NOT_RTL821X;
if (soc_info.family == RTL8380_FAMILY_ID)
rawpage = RTL838X_PAGE_RAW;
else if (soc_info.family == RTL8390_FAMILY_ID)
rawpage = RTL839X_PAGE_RAW;
else
return PHY_IS_NOT_RTL821X;
poll_state = disable_polling(port);
/*
* At this stage the write_page()/read_page() PHY functions are not yet
* registered and normal paged access is not possible. The following
* detection routine works because our MDIO bus has all the Realtek
* PHY page handling (register 31) integrated into the port functions.
* RTL8214FC and RTL8218B are the same PHYs with different configurations. That info is
* stored in the first PHY of the package. In all known configurations packages start at
* bus addresses that are multiples of four. Avoid paged access as this is not available
* during detection.
*/
oldpage = phy_port_read_paged(phydev, port, rawpage, 31);
phy_port_write_paged(phydev, port, rawpage, 31, 0xa42);
phy_port_write_paged(phydev, port, rawpage, 29, 0x008);
phy_port_write_paged(phydev, port, rawpage, 31, 0x278);
phy_port_write_paged(phydev, port, rawpage, 18, 0x455);
phy_port_write_paged(phydev, port, rawpage, 31, 0x260);
chip_mode = phy_port_read_paged(phydev, port, rawpage, 18);
phy_port_write_paged(phydev, port, rawpage, 31, 0xa42);
phy_port_write_paged(phydev, port, rawpage, 29, 0x000);
phy_port_write_paged(phydev, port, rawpage, 31, oldpage);
resume_polling(poll_state);
oldpage = mdiobus_read(bus, addr, 0x1f);
oldxpage = mdiobus_read(bus, addr, 0x1e);
pr_debug("%s(%d): got chip mode %x\n", __func__, phydev->mdio.addr, chip_mode);
mdiobus_write(bus, addr, 0x1e, 0x8);
mdiobus_write(bus, addr, 0x1f, 0x278);
mdiobus_write(bus, addr, 0x12, 0x455);
mdiobus_write(bus, addr, 0x1f, 0x260);
chip_mode = mdiobus_read(bus, addr, 0x12);
dev_dbg(&phydev->mdio.dev, "got RTL8218B/RTL8214Fx chip mode %04x\n", chip_mode);
/* we checked the 4th port of a RTL8218B and got no config values */
mdiobus_write(bus, addr, 0x1e, oldxpage);
mdiobus_write(bus, addr, 0x1f, oldpage);
/* no values while reading the 5th port during 5-8th port detection of RTL8218B */
if (!chip_mode)
return PHY_IS_RTL8218B_E;