uboot-mediatek: GatoNetworks GDSP support fixes and updates

This commit updates the OpenWrt-based U-Boot for this device, allowing
to boot a FIT firmware image stored in an SD card.
The environment has been updated accordingly to allow for managing images
on the two different supported firmware boot media configurations
(NOR or SDMMC).
Erasing the U-Boot environment when upgrading is recommended, so that
the correct DTS overlay is applied.

New behaviour
-------------

The default environment "bootconf" variable is set to
config-1#mt7981b-gatonetworks-gdsp-gps
rendering the GPS module accessible.
You may set it to something like
config-1#mt7981b-gatonetworks-gdsp-sd
to be able to use the MMC controller.
To boot from a firmware image stored in an SD card, you may set the
bootmedia environment variable:
# fw_setenv bootmedia sd
and reboot.
Should the bootmedia variable be absent or it's content not recognized
as valid (e.g., does not contain "nor" or "sd"), NOR boot will be
attempted.

Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>

package/boot/uboot-mediatek/patches/458-add-GatoNetworks-GDSP.patch

@@ -15,7 +15,7 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
 
 --- /dev/null
 +++ b/arch/arm/dts/mt7981-gatonetworks_gdsp.dts
-@@ -0,0 +1,200 @@
+@@ -0,0 +1,235 @@
 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 +
 +/dts-v1/;
@@ -99,6 +99,15 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
 +		always-running;
 +		u-boot,autostart;
 +	};
++
++	reg_3p3v: regulator-3p3v {
++		  compatible = "regulator-fixed";
++		  regulator-name = "fixed-3.3V";
++		  regulator-min-microvolt = <3300000>;
++		  regulator-max-microvolt = <3300000>;
++		  regulator-boot-on;
++		  regulator-always-on;
++	};
 +};
 +
 +&eth {
@@ -167,10 +176,28 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
 +};
 +
 +&pio {
-+	uart1_pins: uart1-pins {
++	mmc0_pins_default: mmc0default {
 +		mux {
-+			function = "uart";
-+			groups = "uart1_0";
++			function = "flash";
++			groups =  "emmc_45";
++		};
++		conf-cmd-dat {
++			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
++				"SPI0_CS",  "SPI0_HOLD", "SPI0_WP",
++				"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
++			input-enable;
++			drive-strength = <MTK_DRIVE_4mA>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
++		};
++		conf-clk {
++			pins = "SPI1_CS";
++			drive-strength = <MTK_DRIVE_8mA>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
++		};
++		conf-rst {
++			pins = "PWM0";
++			drive-strength = <MTK_DRIVE_4mA>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 +		};
 +	};
 +
@@ -205,9 +232,17 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
 +	status = "okay";
 +};
 +
-+&uart1 {
++&mmc0 {
++	assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>,
++				 <&topckgen CLK_TOP_CB_NET2_D2>;
 +	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>;
++	pinctrl-0 = <&mmc0_pins_default>;
++	bus-width = <4>;
++	max-frequency = <50000000>;
++	cap-sd-highspeed;
++	r_smpl = <0>;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_3p3v>;
 +	status = "okay";
 +};
 +
@@ -218,7 +253,7 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
 +};
 --- /dev/null
 +++ b/configs/mt7981_gatonetworks_gdsp_defconfig
-@@ -0,0 +1,142 @@
+@@ -0,0 +1,146 @@
 +CONFIG_ARM=y
 +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 +CONFIG_POSITION_INDEPENDENT=y
@@ -275,8 +310,10 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
 +CONFIG_CMD_GPIO=y
 +CONFIG_CMD_GPIO_READ=y
 +CONFIG_CMD_PWM=y
++CONFIG_CMD_MMC=y
 +CONFIG_CMD_MTD=y
 +# CONFIG_CMD_NAND_EXT is not set
++CONFIG_CMD_PART=y
 +CONFIG_CMD_SF_TEST=y
 +CONFIG_CMD_CAT=y
 +CONFIG_CMD_SETEXPR_FMT=y
@@ -301,6 +338,7 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
 +CONFIG_CMD_FAT=y
 +CONFIG_CMD_FS_GENERIC=y
 +CONFIG_CMD_FS_UUID=y
++CONFIG_EFI_PARTITION=y
 +CONFIG_ENV_OVERWRITE=y
 +CONFIG_ENV_IS_IN_MTD=y
 +CONFIG_ENV_MTD_NAME="u-boot-env"
@@ -319,7 +357,8 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
 +CONFIG_LED=y
 +CONFIG_LED_BLINK=y
 +CONFIG_LED_GPIO=y
-+# CONFIG_MMC is not set
++# CONFIG_MMC_HW_PARTITIONING is not set
++CONFIG_MMC_MTK=y
 +CONFIG_MTD=y
 +CONFIG_DM_MTD=y
 +CONFIG_MTD_SPI_NAND=y
@@ -363,7 +402,7 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
 +CONFIG_HEXDUMP=y
 --- /dev/null
 +++ b/defenvs/gatonetworks_gdsp_env
-@@ -0,0 +1,38 @@
+@@ -0,0 +1,48 @@
 +load_factory_data=if env exists factory_data_present ; then else mtd read Factory $loadaddr 0x0 0x1000 ; setenv factory_data_present 1 ; fi
 +lan_mac_factory=run load_factory_data ; setexpr macoffs $loadaddr + 0x2a ; env readmem -b lan_mac $macoffs 0x6 ; setenv lan_mac_factory ; setenv macoffs
 +wan_mac_factory=run load_factory_data ; setexpr macoffs $loadaddr + 0x24 ; env readmem -b wan_mac $macoffs 0x6 ; setenv wan_mac_factory ; setenv macoffs
@@ -374,10 +413,13 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
 +ipaddr=192.168.1.1
 +serverip=192.168.1.10
 +loadaddr=0x46000000
-+bootcmd=run boot_nor
++bootargs=root=/dev/fit0 rootwait
++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
++bootcmd=run validate_bootmedia; if test $bootmedia = "nor"; then run boot_nor; else if test $bootmedia = "sd"; then run boot_sd_firmware; fi; fi
++bootconf=config-1#mt7981b-gatonetworks-gdsp-gps
 +bootdelay=0
 +bootfile=openwrt-mediatek-filogic-gatonetworks_gdsp-initramfs-kernel.bin
-+bootfile_upg=openwrt-mediatek-filogic-gatonetworks_gdsp-squashfs-sysupgrade.bin
++bootfile_upg=openwrt-mediatek-filogic-gatonetworks_gdsp-squashfs-sysupgrade.itb
 +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
 +bootmenu_default=0
 +bootmenu_delay=0
@@ -385,20 +427,27 @@ Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
 +bootmenu_0=Initialize environment.=run _firstboot
 +bootmenu_0d=Run default boot command.=run boot_default
 +bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
-+bootmenu_2=Boot system from flash.=run boot_nor ; run bootmenu_confirm_return
-+bootmenu_3=Load system via TFTP then write to flash.=run boot_tftp_sysupgrade ; run bootmenu_confirm_return
++bootmenu_2=Boot system from selected boot media.=run bootcmd ; run bootmenu_confirm_return
++bootmenu_3=Load system via TFTP then write to selected boot media.=run load_tftp_sysupgrade ; run bootmenu_confirm_return
 +bootmenu_4=Reset all settings to factory defaults.=run reset_factory ; reset
 +bootmenu_5=Reboot.=reset
 +boot_first=if button reset ; then run boot_tftp ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
 +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_tftp_forever
-+boot_nor=mtd read firmware ${loadaddr} ; bootm $loadaddr
-+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr
++boot_nor=mtd read firmware ${loadaddr} ; bootm $loadaddr#$bootconf
++boot_sd_firmware=setenv bootconf "config-1#mt7981b-gatonetworks-gdsp-sd#mt7981b-gatonetworks-gdsp-sd-boot"; run sdmmc_read_firmware && bootm $loadaddr#$bootconf
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
 +boot_tftp_forever=while true ; do run boot_tftp ; sleep 1 ; done
-+boot_tftp_sysupgrade=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && run nor_write_production
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++sd_part_default=FIT
++sdmmc_read_firmware=part start mmc 0 $sd_part_default part_addr && part size mmc 0 $sd_part_default part_size && run mmc_read_vol
++sdmmc_write_firmware=part start mmc 0 $sd_part_default part_addr && part size mmc 0 $sd_part_default part_size && run mmc_write_vol
++load_tftp_sysupgrade=run validate_bootmedia; tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && if test $bootmedia = "nor"; then run nor_write_firmware; else if test $bootmedia = "sd"; then run sdmmc_write_firmware; fi; fi
 +reset_factory=env default -a && saveenv && reset
 +nor_pad_size=setexpr image_eb $filesize / 0x1000 ; setexpr tmp1 image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb $image_eb + 1 ; setexpr image_eb $image_eb * 0x1000
-+nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x1e80000 && mtd erase firmware 0x0 0x$image_eb && mtd write firmware $loadaddr 0x0 $filesize
++nor_write_firmware=run nor_pad_size ; test 0x$image_eb -le 0x1e80000 && mtd erase firmware 0x0 0x$image_eb && mtd write firmware $loadaddr 0x0 $filesize
 +_init_env=setenv _init_env ; saveenv
 +_firstboot=setenv _firstboot ; run _switch_to_menu ; run lan_mac_factory ; run wan_mac_factory ; run label_mac_factory ; run env_cleanup ; run ethaddr_factory ; run wifi_mac_factory ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
++validate_bootmedia=test $bootmedia != "nor" -a $bootmedia != "sd" && setenv bootmedia "nor"

target/linux/lantiq/Makefile

@@ -10,6 +10,7 @@ FEATURES:=squashfs
 SUBTARGETS:=xrx200 xrx200_legacy xway xway_legacy falcon ase
 
 KERNEL_PATCHVER:=6.6
+KERNEL_TESTING_PATCHVER:=6.12
 
 define Target/Description
 	Build firmware images for Lantiq SoC

target/linux/lantiq/ase/config-6.12

@@ -0,0 +1,23 @@
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+CONFIG_CPU_MIPSR1=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_HW_RANDOM=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+# CONFIG_NET_SWITCHDEV is not set
+CONFIG_NLS=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SOC_AMAZON_SE=y
+# CONFIG_SOC_XWAY is not set
+CONFIG_TARGET_ISA_REV=1
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y

target/linux/lantiq/ase/config-6.6

@@ -4,7 +4,6 @@ CONFIG_CPU_MIPSR1=y
 CONFIG_CRC16=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_FORCE_NR_CPUS=y
 CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y

target/linux/lantiq/config-6.12

@@ -0,0 +1,189 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NEED_SYNC=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+# CONFIG_DT_EASY50712 is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FORCE_NR_CPUS=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_MM_LANTIQ=y
+CONFIG_GPIO_STP_XWAY=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LANTIQ=y
+CONFIG_LANTIQ_DT_NONE=y
+# CONFIG_LANTIQ_ETOP is not set
+CONFIG_LANTIQ_WDT=y
+# CONFIG_LANTIQ_XRX200 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_LANTIQ=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
+CONFIG_MTD_SPLIT_EVA_FW=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_EXCEPT_FILL=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_GPIO_MM_GPIOCHIP=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHY_LANTIQ_RCU_USB2=y
+# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_LANTIQ=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL_XWAY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_LANTIQ=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_LANTIQ=y
+CONFIG_SERIAL_LANTIQ_CONSOLE=y
+# CONFIG_SOC_AMAZON_SE is not set
+# CONFIG_SOC_FALCON is not set
+CONFIG_SOC_TYPE_XWAY=y
+CONFIG_SOC_XWAY=y
+CONFIG_SPI=y
+CONFIG_SPI_LANTIQ_SSC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_VPE_LOADER=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y

target/linux/lantiq/config-6.6

@@ -37,6 +37,7 @@ CONFIG_DTC=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
 CONFIG_FIXED_PHY=y
+CONFIG_FORCE_NR_CPUS=y
 CONFIG_FS_IOMAP=y
 CONFIG_FUNCTION_ALIGNMENT=0
 CONFIG_FWNODE_MDIO=y

target/linux/lantiq/falcon/config-6.12

@@ -0,0 +1,10 @@
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
+# CONFIG_NET_SWITCHDEV is not set
+CONFIG_PINCTRL_FALCON=y
+CONFIG_SOC_FALCON=y
+# CONFIG_SOC_XWAY is not set
+CONFIG_SPI_FALCON=y

target/linux/lantiq/patches-6.12/004-MIPS-lantiq-add-atm-hack.patch

@@ -0,0 +1,482 @@
+From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 3 Aug 2012 10:27:25 +0200
+Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-lantiq/lantiq_atm.h |  196 +++++++++++++++++++++++
+ arch/mips/include/asm/mach-lantiq/lantiq_ptm.h |  203 ++++++++++++++++++++++++
+ arch/mips/lantiq/irq.c                         |    2 +
+ arch/mips/mm/cache.c                           |    4 +
+ include/uapi/linux/atm.h                       |    6 +
+ net/atm/common.c                               |    6 +
+ net/atm/proc.c                                 |    2 +-
+ 7 files changed, 416 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
+@@ -0,0 +1,196 @@
++/******************************************************************************
++**
++** FILE NAME    : ifx_atm.h
++** PROJECT      : UEIP
++** MODULES      : ATM
++**
++** DATE         : 17 Jun 2009
++** AUTHOR       : Xu Liang
++** DESCRIPTION  : Global ATM driver header file
++** COPYRIGHT    :       Copyright (c) 2006
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++**
++** HISTORY
++** $Date        $Author         $Comment
++** 07 JUL 2009  Xu Liang        Init Version
++*******************************************************************************/
++
++#ifndef IFX_ATM_H
++#define IFX_ATM_H
++
++
++
++/*!
++  \defgroup IFX_ATM UEIP Project - ATM driver module
++  \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
++ */
++
++/*!
++  \defgroup IFX_ATM_IOCTL IOCTL Commands
++  \ingroup IFX_ATM
++  \brief IOCTL Commands used by user application.
++ */
++
++/*!
++  \defgroup IFX_ATM_STRUCT Structures
++  \ingroup IFX_ATM
++  \brief Structures used by user application.
++ */
++
++/*!
++  \file ifx_atm.h
++  \ingroup IFX_ATM
++  \brief ATM driver header file
++ */
++
++
++
++/*
++ * ####################################
++ *              Definition
++ * ####################################
++ */
++
++/*!
++  \addtogroup IFX_ATM_STRUCT
++ */
++/*@{*/
++
++/*
++ *  ATM MIB
++ */
++
++/*!
++  \struct atm_cell_ifEntry_t
++  \brief Structure used for Cell Level MIB Counters.
++
++  User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
++ */
++typedef struct {
++	__u32	ifHCInOctets_h;     /*!< byte counter of ingress cells (upper 32 bits, total 64 bits)   */
++	__u32	ifHCInOctets_l;     /*!< byte counter of ingress cells (lower 32 bits, total 64 bits)   */
++	__u32	ifHCOutOctets_h;    /*!< byte counter of egress cells (upper 32 bits, total 64 bits)    */
++	__u32	ifHCOutOctets_l;    /*!< byte counter of egress cells (lower 32 bits, total 64 bits)    */
++	__u32	ifInErrors;         /*!< counter of error ingress cells     */
++	__u32	ifInUnknownProtos;  /*!< counter of unknown ingress cells   */
++	__u32	ifOutErrors;        /*!< counter of error egress cells      */
++} atm_cell_ifEntry_t;
++
++/*!
++  \struct atm_aal5_ifEntry_t
++  \brief Structure used for AAL5 Frame Level MIB Counters.
++
++  User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
++ */
++typedef struct {
++	__u32	ifHCInOctets_h;     /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
++	__u32	ifHCInOctets_l;     /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
++	__u32	ifHCOutOctets_h;    /*!< byte counter of egress packets (upper 32 bits, total 64 bits)  */
++	__u32	ifHCOutOctets_l;    /*!< byte counter of egress packets (lower 32 bits, total 64 bits)  */
++	__u32	ifInUcastPkts;      /*!< counter of ingress packets         */
++	__u32	ifOutUcastPkts;     /*!< counter of egress packets          */
++	__u32	ifInErrors;         /*!< counter of error ingress packets   */
++	__u32	ifInDiscards;       /*!< counter of dropped ingress packets */
++	__u32	ifOutErros;         /*!< counter of error egress packets    */
++	__u32	ifOutDiscards;      /*!< counter of dropped egress packets  */
++} atm_aal5_ifEntry_t;
++
++/*!
++  \struct atm_aal5_vcc_t
++  \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
++
++  This structure is a part of structure "atm_aal5_vcc_x_t".
++ */
++typedef struct {
++	__u32	aal5VccCrcErrors;       /*!< counter of ingress packets with CRC error  */
++	__u32	aal5VccSarTimeOuts;     /*!< counter of ingress packets with Re-assemble timeout    */  //no timer support yet
++	__u32	aal5VccOverSizedSDUs;   /*!< counter of oversized ingress packets       */
++} atm_aal5_vcc_t;
++
++/*!
++  \struct atm_aal5_vcc_x_t
++  \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
++
++  User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
++ */
++typedef struct {
++	int             vpi;        /*!< VPI of the VCC to get MIB counters */
++	int             vci;        /*!< VCI of the VCC to get MIB counters */
++	atm_aal5_vcc_t  mib_vcc;    /*!< structure to get MIB counters      */
++} atm_aal5_vcc_x_t;
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ *                IOCTL
++ * ####################################
++ */
++
++/*!
++  \addtogroup IFX_ATM_IOCTL
++ */
++/*@{*/
++
++/*
++ *  ioctl Command
++ */
++/*!
++  \brief ATM IOCTL Magic Number
++ */
++#define PPE_ATM_IOC_MAGIC       'o'
++/*!
++  \brief ATM IOCTL Command - Get Cell Level MIB Counters
++
++   This command is obsolete. User can get cell level MIB from DSL API.
++   This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
++ */
++#define PPE_ATM_MIB_CELL        _IOW(PPE_ATM_IOC_MAGIC,  0, atm_cell_ifEntry_t)
++/*!
++  \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
++
++   Get AAL5 packet counters.
++   This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
++ */
++#define PPE_ATM_MIB_AAL5        _IOW(PPE_ATM_IOC_MAGIC,  1, atm_aal5_ifEntry_t)
++/*!
++  \brief ATM IOCTL Command - Get Per PVC MIB Counters
++
++   Get AAL5 packet counters for each PVC.
++   This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
++ */
++#define PPE_ATM_MIB_VCC         _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
++/*!
++  \brief Total Number of ATM IOCTL Commands
++ */
++#define PPE_ATM_IOC_MAXNR       3
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ *                 API
++ * ####################################
++ */
++
++#ifdef __KERNEL__
++struct port_cell_info {
++    unsigned int    port_num;
++    unsigned int    tx_link_rate[2];
++};
++#endif
++
++
++
++#endif  //  IFX_ATM_H
++
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
+@@ -0,0 +1,203 @@
++/******************************************************************************
++**
++** FILE NAME    : ifx_ptm.h
++** PROJECT      : UEIP
++** MODULES      : PTM
++**
++** DATE         : 17 Jun 2009
++** AUTHOR       : Xu Liang
++** DESCRIPTION  : Global PTM driver header file
++** COPYRIGHT    :       Copyright (c) 2006
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++**
++** HISTORY
++** $Date        $Author         $Comment
++** 07 JUL 2009  Xu Liang        Init Version
++*******************************************************************************/
++
++#ifndef IFX_PTM_H
++#define IFX_PTM_H
++
++
++
++/*!
++  \defgroup IFX_PTM UEIP Project - PTM driver module
++  \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
++ */
++
++/*!
++  \defgroup IFX_PTM_IOCTL IOCTL Commands
++  \ingroup IFX_PTM
++  \brief IOCTL Commands used by user application.
++ */
++
++/*!
++  \defgroup IFX_PTM_STRUCT Structures
++  \ingroup IFX_PTM
++  \brief Structures used by user application.
++ */
++
++/*!
++  \file ifx_ptm.h
++  \ingroup IFX_PTM
++  \brief PTM driver header file
++ */
++
++
++
++/*
++ * ####################################
++ *              Definition
++ * ####################################
++ */
++
++
++
++/*
++ * ####################################
++ *                IOCTL
++ * ####################################
++ */
++
++/*!
++  \addtogroup IFX_PTM_IOCTL
++ */
++/*@{*/
++
++/*
++ *  ioctl Command
++ */
++/*!
++  \brief PTM IOCTL Command - Get codeword MIB counters.
++
++  This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
++ */
++#define IFX_PTM_MIB_CW_GET              SIOCDEVPRIVATE + 1
++/*!
++  \brief PTM IOCTL Command - Get packet MIB counters.
++
++  This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
++ */
++#define IFX_PTM_MIB_FRAME_GET           SIOCDEVPRIVATE + 2
++/*!
++  \brief PTM IOCTL Command - Get firmware configuration (CRC).
++
++  This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
++ */
++#define IFX_PTM_CFG_GET                 SIOCDEVPRIVATE + 3
++/*!
++  \brief PTM IOCTL Command - Set firmware configuration (CRC).
++
++  This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
++ */
++#define IFX_PTM_CFG_SET                 SIOCDEVPRIVATE + 4
++/*!
++  \brief PTM IOCTL Command - Program priority value to TX queue mapping.
++
++  This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
++ */
++#define IFX_PTM_MAP_PKT_PRIO_TO_Q       SIOCDEVPRIVATE + 14
++
++/*@}*/
++
++
++/*!
++  \addtogroup IFX_PTM_STRUCT
++ */
++/*@{*/
++
++/*
++ *  ioctl Data Type
++ */
++
++/*!
++  \typedef PTM_CW_IF_ENTRY_T
++  \brief Wrapping of structure "ptm_cw_ifEntry_t".
++ */
++/*!
++  \struct ptm_cw_ifEntry_t
++  \brief Structure used for CodeWord level MIB counters.
++ */
++typedef struct ptm_cw_ifEntry_t {
++    uint32_t    ifRxNoIdleCodewords;    /*!< output, number of ingress user codeword */
++    uint32_t    ifRxIdleCodewords;      /*!< output, number of ingress idle codeword */
++    uint32_t    ifRxCodingViolation;    /*!< output, number of error ingress codeword */
++    uint32_t    ifTxNoIdleCodewords;    /*!< output, number of egress user codeword */
++    uint32_t    ifTxIdleCodewords;      /*!< output, number of egress idle codeword */
++} PTM_CW_IF_ENTRY_T;
++
++/*!
++  \typedef PTM_FRAME_MIB_T
++  \brief Wrapping of structure "ptm_frame_mib_t".
++ */
++/*!
++  \struct ptm_frame_mib_t
++  \brief Structure used for packet level MIB counters.
++ */
++typedef struct ptm_frame_mib_t {
++    uint32_t    RxCorrect;      /*!< output, number of ingress packet */
++    uint32_t    TC_CrcError;    /*!< output, number of egress packet with CRC error */
++    uint32_t    RxDropped;      /*!< output, number of dropped ingress packet */
++    uint32_t    TxSend;         /*!< output, number of egress packet */
++} PTM_FRAME_MIB_T;
++
++/*!
++  \typedef IFX_PTM_CFG_T
++  \brief Wrapping of structure "ptm_cfg_t".
++ */
++/*!
++  \struct ptm_cfg_t
++  \brief Structure used for ETH/TC CRC configuration.
++ */
++typedef struct ptm_cfg_t {
++    uint32_t    RxEthCrcPresent;    /*!< input/output, ingress packet has ETH CRC */
++    uint32_t    RxEthCrcCheck;      /*!< input/output, check ETH CRC of ingress packet */
++    uint32_t    RxTcCrcCheck;       /*!< input/output, check TC CRC of ingress codeword */
++    uint32_t    RxTcCrcLen;         /*!< input/output, length of TC CRC of ingress codeword */
++    uint32_t    TxEthCrcGen;        /*!< input/output, generate ETH CRC for egress packet */
++    uint32_t    TxTcCrcGen;         /*!< input/output, generate TC CRC for egress codeword */
++    uint32_t    TxTcCrcLen;         /*!< input/output, length of TC CRC of egress codeword */
++} IFX_PTM_CFG_T;
++
++/*!
++  \typedef IFX_PTM_PRIO_Q_MAP_T
++  \brief Wrapping of structure "ppe_prio_q_map".
++ */
++/*!
++  \struct ppe_prio_q_map
++  \brief Structure used for Priority Value to TX Queue mapping.
++ */
++typedef struct ppe_prio_q_map {
++    int             pkt_prio;
++    int             qid;
++    int             vpi;    //  ignored in eth interface
++    int             vci;    //  ignored in eth interface
++} IFX_PTM_PRIO_Q_MAP_T;
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ *                 API
++ * ####################################
++ */
++
++#ifdef __KERNEL__
++struct port_cell_info {
++    unsigned int    port_num;
++    unsigned int    tx_link_rate[2];
++};
++#endif
++
++
++
++#endif  //  IFX_PTM_H
++
+--- a/arch/mips/lantiq/irq.c
++++ b/arch/mips/lantiq/irq.c
+@@ -13,6 +13,7 @@
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
++#include <linux/module.h>
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/irq_cpu.h>
+@@ -92,6 +93,7 @@ void ltq_disable_irq(struct irq_data *d)
+ 	}
+ 	raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
+ }
++EXPORT_SYMBOL(ltq_mask_and_ack_irq);
+ 
+ void ltq_mask_and_ack_irq(struct irq_data *d)
+ {
+--- a/arch/mips/mm/cache.c
++++ b/arch/mips/mm/cache.c
+@@ -80,6 +80,10 @@ void (*_dma_cache_wback_inv)(unsigned lo
+ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
+ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+ 
++EXPORT_SYMBOL(_dma_cache_wback_inv);
++EXPORT_SYMBOL(_dma_cache_wback);
++EXPORT_SYMBOL(_dma_cache_inv);
++
+ #endif /* CONFIG_DMA_NONCOHERENT */
+ 
+ /*
+--- a/include/uapi/linux/atm.h
++++ b/include/uapi/linux/atm.h
+@@ -131,8 +131,14 @@
+ #define ATM_ABR		4
+ #define ATM_ANYCLASS	5		/* compatible with everything */
+ 
++#define ATM_VBR_NRT     ATM_VBR
++#define ATM_VBR_RT      6
++#define ATM_UBR_PLUS    7
++#define ATM_GFR         8
++
+ #define ATM_MAX_PCR	-1		/* maximum available PCR */
+ 
++
+ struct atm_trafprm {
+ 	unsigned char	traffic_class;	/* traffic class (ATM_UBR, ...) */
+ 	int		max_pcr;	/* maximum PCR in cells per second */
+--- a/net/atm/proc.c
++++ b/net/atm/proc.c
+@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil
+ static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
+ {
+ 	static const char *const class_name[] = {
+-		"off", "UBR", "CBR", "VBR", "ABR"};
++		"off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
+ 	static const char *const aal_name[] = {
+ 		"---",	"1",	"2",	"3/4",	/*  0- 3 */
+ 		"???",	"5",	"???",	"???",	/*  4- 7 */

target/linux/lantiq/patches-6.12/018-MTD-nand-lots-of-xrx200-fixes.patch

@@ -0,0 +1,121 @@
+From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 9 Sep 2014 23:12:15 +0200
+Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/nand/raw/xway_nand.c |   63 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 63 insertions(+)
+
+--- a/drivers/mtd/nand/raw/xway_nand.c
++++ b/drivers/mtd/nand/raw/xway_nand.c
+@@ -61,6 +61,24 @@
+ #define NAND_CON_CSMUX		(1 << 1)
+ #define NAND_CON_NANDM		1
+ 
++#define DANUBE_PCI_REG32( addr )    (*(volatile u32 *)(addr))
++#define PCI_CR_PR_OFFSET	    (KSEG1+0x1E105400)
++#define PCI_CR_PC_ARB		    (PCI_CR_PR_OFFSET + 0x0080)
++
++/*
++ * req_mask provides a mechanism to prevent interference between
++ * nand and pci (probably only relevant for the BT Home Hub 2B).
++ * Setting it causes the corresponding pci req pins to be masked
++ * during nand access, and also moves ebu locking from the read/write
++ * functions to the chip select function to ensure that the whole
++ * operation runs with interrupts disabled.
++ * In addition it switches on some extra waiting in xway_cmd_ctrl().
++ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
++ * which in turn seems to be necessary for the nor chip to be recognised
++ * reliably, on a board (Home Hub 2B again) which has both nor and nand.
++ */
++static __be32 req_mask = 0;
++
+ struct xway_nand_data {
+ 	struct nand_controller	controller;
+ 	struct nand_chip	chip;
+@@ -92,10 +110,22 @@ static void xway_select_chip(struct nand
+ 	case -1:
+ 		ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
+ 		ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
++
++		if (req_mask) {
++			/* Unmask all external PCI request */
++			DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
++		}
++
+ 		spin_unlock_irqrestore(&ebu_lock, data->csflags);
+ 		break;
+ 	case 0:
+ 		spin_lock_irqsave(&ebu_lock, data->csflags);
++
++		if (req_mask) {
++			/* Mask all external PCI request */
++			DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
++		}
++
+ 		ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
+ 		ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
+ 		break;
+@@ -108,6 +138,11 @@ static void xway_cmd_ctrl(struct nand_ch
+ {
+ 	struct mtd_info *mtd = nand_to_mtd(chip);
+ 
++	if (req_mask) {
++		if (cmd != NAND_CMD_STATUS)
++			ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */
++	}
++
+ 	if (cmd == NAND_CMD_NONE)
+ 		return;
+ 
+@@ -118,6 +153,24 @@ static void xway_cmd_ctrl(struct nand_ch
+ 
+ 	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ 		;
++
++	if (req_mask) {
++	       /*
++		* program and erase have their own busy handlers
++		* status and sequential in needs no delay
++		*/
++		switch (cmd) {
++			case NAND_CMD_ERASE1:
++			case NAND_CMD_SEQIN:
++			case NAND_CMD_STATUS:
++			case NAND_CMD_READID:
++			return;
++		}
++
++		/* wait until command is processed */
++		while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
++			;
++	}
+ }
+ 
+ static int xway_dev_ready(struct nand_chip *chip)
+@@ -169,6 +222,7 @@ static int xway_nand_probe(struct platfo
+ 	int err;
+ 	u32 cs;
+ 	u32 cs_flag = 0;
++	const __be32 *req_mask_ptr;
+ 
+ 	/* Allocate memory for the device structure (and zero it) */
+ 	data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),
+@@ -204,6 +258,15 @@ static int xway_nand_probe(struct platfo
+ 	if (!err && cs == 1)
+ 		cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
+ 
++	req_mask_ptr = of_get_property(pdev->dev.of_node,
++					"req-mask", NULL);
++
++	/*
++	 * Load the PCI req lines to mask from the device tree. If the
++	 * property is not present, setting req_mask to 0 disables masking.
++	 */
++	req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
++
+ 	/* setup the EBU to run in NAND mode on our base addr */
+ 	ltq_ebu_w32(CPHYSADDR(data->nandaddr)
+ 		    | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);

target/linux/lantiq/patches-6.12/020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch

@@ -0,0 +1,25 @@
+From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:18:00 +0200
+Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/maps/lantiq-flash.c |    6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/maps/lantiq-flash.c
++++ b/drivers/mtd/maps/lantiq-flash.c
+@@ -127,7 +127,11 @@ ltq_mtd_probe(struct platform_device *pd
+ 	if (!ltq_mtd->map)
+ 		return -ENOMEM;
+ 
+-	ltq_mtd->map->phys = ltq_mtd->res->start;
++	if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
++		ltq_mtd->map->phys = NO_XIP;
++	else
++		ltq_mtd->map->phys = ltq_mtd->res->start;
++	ltq_mtd->res->start;
+ 	ltq_mtd->map->size = resource_size(ltq_mtd->res);
+ 
+ 	ltq_mtd->map->name = ltq_map_name;

target/linux/lantiq/patches-6.12/028-NET-lantiq-various-etop-fixes.patch

@@ -0,0 +1,891 @@
+From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 9 Sep 2014 22:45:34 +0200
+Subject: [PATCH 28/36] NET: lantiq: various etop fixes
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/ethernet/lantiq_etop.c | 534 ++++++++++++++++++++---------
+ 1 file changed, 379 insertions(+), 155 deletions(-)
+
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -1,7 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /*
+  *
+- *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ *   Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
+  */
+ 
+ #include <linux/kernel.h>
+@@ -20,12 +20,17 @@
+ #include <linux/mm.h>
+ #include <linux/platform_device.h>
+ #include <linux/ethtool.h>
++#include <linux/if_vlan.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/module.h>
+ #include <linux/property.h>
++#include <linux/clk.h>
++#include <linux/of_net.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
+ 
+ #include <asm/checksum.h>
+ 
+@@ -33,7 +38,7 @@
+ #include <xway_dma.h>
+ #include <lantiq_platform.h>
+ 
+-#define LTQ_ETOP_MDIO		0x11804
++#define LTQ_ETOP_MDIO_ACC	0x11804
+ #define MDIO_REQUEST		0x80000000
+ #define MDIO_READ		0x40000000
+ #define MDIO_ADDR_MASK		0x1f
+@@ -42,44 +47,91 @@
+ #define MDIO_REG_OFFSET		0x10
+ #define MDIO_VAL_MASK		0xffff
+ 
+-#define PPE32_CGEN		0x800
+-#define LQ_PPE32_ENET_MAC_CFG	0x1840
++#define LTQ_ETOP_MDIO_CFG       0x11800
++#define MDIO_CFG_MASK           0x6
++
++#define LTQ_ETOP_CFG            0x11808
++#define LTQ_ETOP_IGPLEN         0x11820
++#define LTQ_ETOP_MAC_CFG	0x11840
+ 
+ #define LTQ_ETOP_ENETS0		0x11850
+ #define LTQ_ETOP_MAC_DA0	0x1186C
+ #define LTQ_ETOP_MAC_DA1	0x11870
+-#define LTQ_ETOP_CFG		0x16020
+-#define LTQ_ETOP_IGPLEN		0x16080
++
++#define MAC_CFG_MASK		0xfff
++#define MAC_CFG_CGEN		BIT(11)
++#define MAC_CFG_DUPLEX		BIT(2)
++#define MAC_CFG_SPEED		BIT(1)
++#define MAC_CFG_LINK		BIT(0)
+ 
+ #define MAX_DMA_CHAN		0x8
+ #define MAX_DMA_CRC_LEN		0x4
+ #define MAX_DMA_DATA_LEN	0x600
+ 
+ #define ETOP_FTCU		BIT(28)
+-#define ETOP_MII_MASK		0xf
+-#define ETOP_MII_NORMAL		0xd
+-#define ETOP_MII_REVERSE	0xe
+ #define ETOP_PLEN_UNDER		0x40
+-#define ETOP_CGEN		0x800
++#define ETOP_CFG_MII0		0x01
+ 
+-/* use 2 static channels for TX/RX */
+-#define LTQ_ETOP_TX_CHANNEL	1
+-#define LTQ_ETOP_RX_CHANNEL	6
+-#define IS_TX(x)		((x) == LTQ_ETOP_TX_CHANNEL)
+-#define IS_RX(x)		((x) == LTQ_ETOP_RX_CHANNEL)
++#define ETOP_CFG_MASK           0xfff
++#define ETOP_CFG_FEN0		BIT(8)
++#define ETOP_CFG_SEN0		BIT(6)
++#define ETOP_CFG_OFF1		BIT(3)
++#define ETOP_CFG_REMII0		BIT(1)
++#define ETOP_CFG_OFF0		BIT(0)
++
++#define LTQ_GBIT_MDIO_CTL	0xCC
++#define LTQ_GBIT_MDIO_DATA	0xd0
++#define LTQ_GBIT_GCTL0		0x68
++#define LTQ_GBIT_PMAC_HD_CTL	0x8c
++#define LTQ_GBIT_P0_CTL		0x4
++#define LTQ_GBIT_PMAC_RX_IPG	0xa8
++#define LTQ_GBIT_RGMII_CTL	0x78
++
++#define PMAC_HD_CTL_AS		BIT(19)
++#define PMAC_HD_CTL_RXSH	BIT(22)
++
++/* Switch Enable (0=disable, 1=enable) */
++#define GCTL0_SE		0x80000000
++/* Disable MDIO auto polling (0=disable, 1=enable) */
++#define PX_CTL_DMDIO		0x00400000
++
++/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
++#define MDC_CLOCK_MASK		0xff000000
++#define MDC_CLOCK_OFFSET	24
++
++/* register information for the gbit's MDIO bus */
++#define MDIO_XR9_REQUEST	0x00008000
++#define MDIO_XR9_READ		0x00000800
++#define MDIO_XR9_WRITE		0x00000400
++#define MDIO_XR9_REG_MASK	0x1f
++#define MDIO_XR9_ADDR_MASK	0x1f
++#define MDIO_XR9_RD_MASK	0xffff
++#define MDIO_XR9_REG_OFFSET	0
++#define MDIO_XR9_ADDR_OFFSET	5
++#define MDIO_XR9_WR_OFFSET	16
+ 
++#define LTQ_DMA_ETOP	((of_machine_is_compatible("lantiq,ase")) ? \
++			(INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
++
++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
+ #define ltq_etop_r32(x)		ltq_r32(ltq_etop_membase + (x))
+ #define ltq_etop_w32(x, y)	ltq_w32(x, ltq_etop_membase + (y))
+ #define ltq_etop_w32_mask(x, y, z)	\
+ 		ltq_w32_mask(x, y, ltq_etop_membase + (z))
+ 
+-#define DRV_VERSION	"1.0"
++#define ltq_gbit_r32(x)		ltq_r32(ltq_gbit_membase + (x))
++#define ltq_gbit_w32(x, y)	ltq_w32(x, ltq_gbit_membase + (y))
++#define ltq_gbit_w32_mask(x, y, z)	\
++		ltq_w32_mask(x, y, ltq_gbit_membase + (z))
++
++#define DRV_VERSION	"1.2"
+ 
+ static void __iomem *ltq_etop_membase;
++static void __iomem *ltq_gbit_membase;
+ 
+ struct ltq_etop_chan {
+-	int idx;
+ 	int tx_free;
++	int irq;
+ 	struct net_device *netdev;
+ 	struct napi_struct napi;
+ 	struct ltq_dma_channel dma;
+@@ -89,25 +141,39 @@ struct ltq_etop_chan {
+ struct ltq_etop_priv {
+ 	struct net_device *netdev;
+ 	struct platform_device *pdev;
+-	struct ltq_eth_data *pldata;
+ 	struct resource *res;
+ 
+ 	struct mii_bus *mii_bus;
+ 
+-	struct ltq_etop_chan ch[MAX_DMA_CHAN];
++	struct ltq_etop_chan txch;
++	struct ltq_etop_chan rxch;
+ 
+ 	int tx_burst_len;
+ 	int rx_burst_len;
+ 
++	int tx_irq;
++	int rx_irq;
++
++	unsigned char mac[6];
++	phy_interface_t mii_mode;
++
+ 	spinlock_t lock;
++
++	struct clk *clk_ppe;
++	struct clk *clk_switch;
++	struct clk *clk_ephy;
++	struct clk *clk_ephycgu;
+ };
+ 
++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
++			    int phy_reg, u16 phy_data);
++
+ static int
+ ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ 
+-	ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
++	ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
+ 	if (!ch->skb[ch->dma.desc])
+ 		return -ENOMEM;
+ 	ch->dma.desc_base[ch->dma.desc].addr =
+@@ -142,8 +208,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+ 	skb_put(skb, len);
++	skb->dev = ch->netdev;
+ 	skb->protocol = eth_type_trans(skb, ch->netdev);
+ 	netif_receive_skb(skb);
++	ch->netdev->stats.rx_packets++;
++	ch->netdev->stats.rx_bytes += len;
+ }
+ 
+ static int
+@@ -151,7 +220,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
+ {
+ 	struct ltq_etop_chan *ch = container_of(napi,
+ 				struct ltq_etop_chan, napi);
++	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ 	int work_done = 0;
++	unsigned long flags;
+ 
+ 	while (work_done < budget) {
+ 		struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+@@ -163,7 +234,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
+ 	}
+ 	if (work_done < budget) {
+ 		napi_complete_done(&ch->napi, work_done);
++		spin_lock_irqsave(&priv->lock, flags);
+ 		ltq_dma_ack_irq(&ch->dma);
++		spin_unlock_irqrestore(&priv->lock, flags);
+ 	}
+ 	return work_done;
+ }
+@@ -175,12 +248,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
+ 		container_of(napi, struct ltq_etop_chan, napi);
+ 	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ 	struct netdev_queue *txq =
+-		netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
++		netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&priv->lock, flags);
+ 	while ((ch->dma.desc_base[ch->tx_free].ctl &
+ 			(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
++		ch->netdev->stats.tx_packets++;
++		ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
+ 		dev_kfree_skb_any(ch->skb[ch->tx_free]);
+ 		ch->skb[ch->tx_free] = NULL;
+ 		memset(&ch->dma.desc_base[ch->tx_free], 0,
+@@ -193,7 +268,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
+ 	if (netif_tx_queue_stopped(txq))
+ 		netif_tx_start_queue(txq);
+ 	napi_complete(&ch->napi);
++	spin_lock_irqsave(&priv->lock, flags);
+ 	ltq_dma_ack_irq(&ch->dma);
++	spin_unlock_irqrestore(&priv->lock, flags);
+ 	return 1;
+ }
+ 
+@@ -201,9 +278,11 @@ static irqreturn_t
+ ltq_etop_dma_irq(int irq, void *_priv)
+ {
+ 	struct ltq_etop_priv *priv = _priv;
+-	int ch = irq - LTQ_DMA_CH0_INT;
+ 
+-	napi_schedule(&priv->ch[ch].napi);
++	if (irq == priv->txch.dma.irq)
++		napi_schedule(&priv->txch.napi);
++	else
++		napi_schedule(&priv->rxch.napi);
+ 	return IRQ_HANDLED;
+ }
+ 
+@@ -215,7 +294,7 @@ ltq_etop_free_channel(struct net_device
+ 	ltq_dma_free(&ch->dma);
+ 	if (ch->dma.irq)
+ 		free_irq(ch->dma.irq, priv);
+-	if (IS_RX(ch->idx)) {
++	if (ch == &priv->rxch) {
+ 		struct ltq_dma_channel *dma = &ch->dma;
+ 
+ 		for (dma->desc = 0; dma->desc < LTQ_DESC_NUM; dma->desc++)
+@@ -227,80 +306,137 @@ static void
+ ltq_etop_hw_exit(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
+ 
+-	ltq_pmu_disable(PMU_PPE);
+-	for (i = 0; i < MAX_DMA_CHAN; i++)
+-		if (IS_TX(i) || IS_RX(i))
+-			ltq_etop_free_channel(dev, &priv->ch[i]);
++	clk_disable(priv->clk_ppe);
++
++	if (of_machine_is_compatible("lantiq,ar9"))
++		clk_disable(priv->clk_switch);
++
++	if (of_machine_is_compatible("lantiq,ase")) {
++		clk_disable(priv->clk_ephy);
++		clk_disable(priv->clk_ephycgu);
++	}
++
++	ltq_etop_free_channel(dev, &priv->txch);
++	ltq_etop_free_channel(dev, &priv->rxch);
++}
++
++static void
++ltq_etop_gbit_init(struct net_device *dev)
++{
++	struct ltq_etop_priv *priv = netdev_priv(dev);
++
++	clk_enable(priv->clk_switch);
++
++	/* enable gbit port0 on the SoC */
++	ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
++
++	ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
++	/* disable MDIO auto polling mode */
++	ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
++	/* set 1522 packet size */
++	ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
++	/* disable pmac & dmac headers */
++	ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
++			  LTQ_GBIT_PMAC_HD_CTL);
++	/* Due to traffic halt when burst length 8,
++	 *replace default IPG value with 0x3B
++	 */
++	ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
++	/* set mdc clock to 2.5 MHz */
++	ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
++			  LTQ_GBIT_RGMII_CTL);
+ }
+ 
+ static int
+ ltq_etop_hw_init(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
+-	int err;
++	phy_interface_t mii_mode = priv->mii_mode;
++
++	clk_enable(priv->clk_ppe);
+ 
+-	ltq_pmu_enable(PMU_PPE);
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		ltq_etop_gbit_init(dev);
++		/* force the etops link to the gbit to MII */
++		mii_mode = PHY_INTERFACE_MODE_MII;
++	}
++	ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
++	ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
++			MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
+ 
+-	switch (priv->pldata->mii_mode) {
++	switch (mii_mode) {
+ 	case PHY_INTERFACE_MODE_RMII:
+-		ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_REVERSE,
+-				  LTQ_ETOP_CFG);
++		ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
++			ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
+ 		break;
+ 
+ 	case PHY_INTERFACE_MODE_MII:
+-		ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_NORMAL,
+-				  LTQ_ETOP_CFG);
++		ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
++			ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
+ 		break;
+ 
+ 	default:
++		if (of_machine_is_compatible("lantiq,ase")) {
++			clk_enable(priv->clk_ephy);
++			/* disable external MII */
++			ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
++			/* enable clock for internal PHY */
++			clk_enable(priv->clk_ephycgu);
++			/* we need to write this magic to the internal phy to
++			 * make it work
++			 */
++			ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
++			pr_info("Selected EPHY mode\n");
++			break;
++		}
+ 		netdev_err(dev, "unknown mii mode %d\n",
+-			   priv->pldata->mii_mode);
++			   mii_mode);
+ 		return -ENOTSUPP;
+ 	}
+ 
+-	/* enable crc generation */
+-	ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
++	return 0;
++}
++
++static int
++ltq_etop_dma_init(struct net_device *dev)
++{
++	struct ltq_etop_priv *priv = netdev_priv(dev);
++	int tx = priv->tx_irq - LTQ_DMA_ETOP;
++	int rx = priv->rx_irq - LTQ_DMA_ETOP;
++	int err;
+ 
+ 	ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len);
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		int irq = LTQ_DMA_CH0_INT + i;
+-		struct ltq_etop_chan *ch = &priv->ch[i];
+-
+-		ch->dma.nr = i;
+-		ch->idx = ch->dma.nr;
+-		ch->dma.dev = &priv->pdev->dev;
+-
+-		if (IS_TX(i)) {
+-			ltq_dma_alloc_tx(&ch->dma);
+-			err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
+-			if (err) {
+-				netdev_err(dev,
+-					   "Unable to get Tx DMA IRQ %d\n",
+-					   irq);
+-				return err;
+-			}
+-		} else if (IS_RX(i)) {
+-			ltq_dma_alloc_rx(&ch->dma);
+-			for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
+-					ch->dma.desc++)
+-				if (ltq_etop_alloc_skb(ch))
+-					return -ENOMEM;
+-			ch->dma.desc = 0;
+-			err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
+-			if (err) {
+-				netdev_err(dev,
+-					   "Unable to get Rx DMA IRQ %d\n",
+-					   irq);
+-				return err;
+-			}
++	priv->txch.dma.nr = tx;
++	priv->txch.dma.dev = &priv->pdev->dev;
++	ltq_dma_alloc_tx(&priv->txch.dma);
++	err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
++	if (err) {
++		netdev_err(dev, "failed to allocate tx irq\n");
++		goto err_out;
++	}
++	priv->txch.dma.irq = priv->tx_irq;
++
++	priv->rxch.dma.nr = rx;
++	priv->rxch.dma.dev = &priv->pdev->dev;
++	ltq_dma_alloc_rx(&priv->rxch.dma);
++	for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
++			priv->rxch.dma.desc++) {
++		if (ltq_etop_alloc_skb(&priv->rxch)) {
++			netdev_err(dev, "failed to allocate skbs\n");
++			err = -ENOMEM;
++			goto err_out;
+ 		}
+-		ch->dma.irq = irq;
+ 	}
+-	return 0;
++	priv->rxch.dma.desc = 0;
++	err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
++	if (err)
++		netdev_err(dev, "failed to allocate rx irq\n");
++	else
++		priv->rxch.dma.irq = priv->rx_irq;
++err_out:
++	return err;
+ }
+ 
+ static void
+@@ -319,6 +455,39 @@ static const struct ethtool_ops ltq_etop
+ };
+ 
+ static int
++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
++		     int phy_reg, u16 phy_data)
++{
++	u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
++		(phy_data << MDIO_XR9_WR_OFFSET) |
++		((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
++		((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
++
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	return 0;
++}
++
++static int
++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
++{
++	u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
++		((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
++		((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
++
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
++	return val;
++}
++
++static int
+ ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
+ {
+ 	u32 val = MDIO_REQUEST |
+@@ -326,9 +495,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
+ 		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
+ 		phy_data;
+ 
+-	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++	while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ 		;
+-	ltq_etop_w32(val, LTQ_ETOP_MDIO);
++	ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
+ 	return 0;
+ }
+ 
+@@ -339,12 +508,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
+ 		((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
+ 		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
+ 
+-	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++	while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ 		;
+-	ltq_etop_w32(val, LTQ_ETOP_MDIO);
+-	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++	ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
++	while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ 		;
+-	val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
++	val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
+ 	return val;
+ }
+ 
+@@ -360,7 +529,10 @@ ltq_etop_mdio_probe(struct net_device *d
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 	struct phy_device *phydev;
+ 
+-	phydev = phy_find_first(priv->mii_bus);
++	if (of_machine_is_compatible("lantiq,ase"))
++		phydev = mdiobus_get_phy(priv->mii_bus, 8);
++	else
++		phydev = mdiobus_get_phy(priv->mii_bus, 0);
+ 
+ 	if (!phydev) {
+ 		netdev_err(dev, "no PHY found\n");
+@@ -368,14 +540,17 @@ ltq_etop_mdio_probe(struct net_device *d
+ 	}
+ 
+ 	phydev = phy_connect(dev, phydev_name(phydev),
+-			     &ltq_etop_mdio_link, priv->pldata->mii_mode);
++			     &ltq_etop_mdio_link, priv->mii_mode);
+ 
+ 	if (IS_ERR(phydev)) {
+ 		netdev_err(dev, "Could not attach to PHY\n");
+ 		return PTR_ERR(phydev);
+ 	}
+ 
+-	phy_set_max_speed(phydev, SPEED_100);
++	if (of_machine_is_compatible("lantiq,ar9"))
++		phy_set_max_speed(phydev, SPEED_1000);
++	else
++		phy_set_max_speed(phydev, SPEED_100);
+ 
+ 	phy_attached_info(phydev);
+ 
+@@ -396,8 +571,13 @@ ltq_etop_mdio_init(struct net_device *de
+ 	}
+ 
+ 	priv->mii_bus->priv = dev;
+-	priv->mii_bus->read = ltq_etop_mdio_rd;
+-	priv->mii_bus->write = ltq_etop_mdio_wr;
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
++		priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
++	} else {
++		priv->mii_bus->read = ltq_etop_mdio_rd;
++		priv->mii_bus->write = ltq_etop_mdio_wr;
++	}
+ 	priv->mii_bus->name = "ltq_mii";
+ 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+ 		 priv->pdev->name, priv->pdev->id);
+@@ -434,18 +614,21 @@ static int
+ ltq_etop_open(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
++	unsigned long flags;
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		struct ltq_etop_chan *ch = &priv->ch[i];
++	napi_enable(&priv->txch.napi);
++	napi_enable(&priv->rxch.napi);
++
++	spin_lock_irqsave(&priv->lock, flags);
++	ltq_dma_open(&priv->txch.dma);
++	ltq_dma_enable_irq(&priv->txch.dma);
++	ltq_dma_open(&priv->rxch.dma);
++	ltq_dma_enable_irq(&priv->rxch.dma);
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	if (dev->phydev)
++		phy_start(dev->phydev);
+ 
+-		if (!IS_TX(i) && (!IS_RX(i)))
+-			continue;
+-		ltq_dma_open(&ch->dma);
+-		ltq_dma_enable_irq(&ch->dma);
+-		napi_enable(&ch->napi);
+-	}
+-	phy_start(dev->phydev);
+ 	netif_tx_start_all_queues(dev);
+ 	return 0;
+ }
+@@ -454,18 +637,19 @@ static int
+ ltq_etop_stop(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
++	unsigned long flags;
+ 
+ 	netif_tx_stop_all_queues(dev);
+-	phy_stop(dev->phydev);
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		struct ltq_etop_chan *ch = &priv->ch[i];
+-
+-		if (!IS_RX(i) && !IS_TX(i))
+-			continue;
+-		napi_disable(&ch->napi);
+-		ltq_dma_close(&ch->dma);
+-	}
++	if (dev->phydev)
++		phy_stop(dev->phydev);
++	napi_disable(&priv->txch.napi);
++	napi_disable(&priv->rxch.napi);
++
++	spin_lock_irqsave(&priv->lock, flags);
++	ltq_dma_close(&priv->txch.dma);
++	ltq_dma_close(&priv->rxch.dma);
++	spin_unlock_irqrestore(&priv->lock, flags);
++
+ 	return 0;
+ }
+ 
+@@ -475,17 +659,21 @@ ltq_etop_tx(struct sk_buff *skb, struct
+ 	int queue = skb_get_queue_mapping(skb);
+ 	struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
+-	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+-	int len;
++	struct ltq_dma_desc *desc =
++		&priv->txch.dma.desc_base[priv->txch.dma.desc];
+ 	unsigned long flags;
+ 	u32 byte_offset;
++	int len;
+ 
+-	if (skb_put_padto(skb, ETH_ZLEN))
++	if (skb_put_padto(skb, ETH_ZLEN)) {
++		dev->stats.tx_dropped++;
+ 		return NETDEV_TX_OK;
++	}
++
+ 	len = skb->len;
+ 
+-	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
++	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
++	    priv->txch.skb[priv->txch.dma.desc]) {
+ 		netdev_err(dev, "tx ring full\n");
+ 		netif_tx_stop_queue(txq);
+ 		return NETDEV_TX_BUSY;
+@@ -493,7 +681,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
+ 
+ 	/* dma needs to start on a burst length value aligned address */
+ 	byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4);
+-	ch->skb[ch->dma.desc] = skb;
++	priv->txch.skb[priv->txch.dma.desc] = skb;
+ 
+ 	netif_trans_update(dev);
+ 
+@@ -504,11 +692,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
+ 	wmb();
+ 	desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
+ 		LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
+-	ch->dma.desc++;
+-	ch->dma.desc %= LTQ_DESC_NUM;
++	priv->txch.dma.desc++;
++	priv->txch.dma.desc %= LTQ_DESC_NUM;
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+-	if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
++	if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
+ 		netif_tx_stop_queue(txq);
+ 
+ 	return NETDEV_TX_OK;
+@@ -519,11 +707,14 @@ ltq_etop_change_mtu(struct net_device *d
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 	unsigned long flags;
++	int max;
+ 
+ 	WRITE_ONCE(dev->mtu, new_mtu);
+ 
++	max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
++
+ 	spin_lock_irqsave(&priv->lock, flags);
+-	ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
++	ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN);
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+ 	return 0;
+@@ -576,6 +767,9 @@ ltq_etop_init(struct net_device *dev)
+ 	if (err)
+ 		goto err_hw;
+ 	ltq_etop_change_mtu(dev, 1500);
++	err = ltq_etop_dma_init(dev);
++	if (err)
++		goto err_hw;
+ 
+ 	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
+ 	if (!is_valid_ether_addr(mac.sa_data)) {
+@@ -593,9 +787,10 @@ ltq_etop_init(struct net_device *dev)
+ 		dev->addr_assign_type = NET_ADDR_RANDOM;
+ 
+ 	ltq_etop_set_multicast_list(dev);
+-	err = ltq_etop_mdio_init(dev);
+-	if (err)
+-		goto err_netdev;
++	if (!ltq_etop_mdio_init(dev))
++		dev->ethtool_ops = &ltq_etop_ethtool_ops;
++	else
++		pr_warn("etop: mdio probe failed\n");
+ 	return 0;
+ 
+ err_netdev:
+@@ -615,6 +810,9 @@ ltq_etop_tx_timeout(struct net_device *d
+ 	err = ltq_etop_hw_init(dev);
+ 	if (err)
+ 		goto err_hw;
++	err = ltq_etop_dma_init(dev);
++	if (err)
++		goto err_hw;
+ 	netif_trans_update(dev);
+ 	netif_wake_queue(dev);
+ 	return;
+@@ -638,14 +836,18 @@ static const struct net_device_ops ltq_e
+ 	.ndo_tx_timeout = ltq_etop_tx_timeout,
+ };
+ 
+-static int __init
+-ltq_etop_probe(struct platform_device *pdev)
++static int ltq_etop_probe(struct platform_device *pdev)
+ {
+ 	struct net_device *dev;
+ 	struct ltq_etop_priv *priv;
+-	struct resource *res;
++	struct resource *res, *gbit_res, irqres[2];
+ 	int err;
+-	int i;
++
++	err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
++	if (err != 2) {
++		dev_err(&pdev->dev, "failed to get etop irqs\n");
++		return -EINVAL;
++	}
+ 
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	if (!res) {
+@@ -671,18 +873,54 @@ ltq_etop_probe(struct platform_device *p
+ 		goto err_out;
+ 	}
+ 
+-	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
+-	if (!dev) {
+-		err = -ENOMEM;
+-		goto err_out;
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++		if (!gbit_res) {
++			dev_err(&pdev->dev, "failed to get gbit resource\n");
++			err = -ENOENT;
++			goto err_out;
++		}
++		ltq_gbit_membase = devm_ioremap(&pdev->dev,
++						gbit_res->start, resource_size(gbit_res));
++		if (!ltq_gbit_membase) {
++			dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
++				pdev->id);
++			err = -ENOMEM;
++			goto err_out;
++		}
+ 	}
++
++	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
+ 	dev->netdev_ops = &ltq_eth_netdev_ops;
+-	dev->ethtool_ops = &ltq_etop_ethtool_ops;
+ 	priv = netdev_priv(dev);
+ 	priv->res = res;
+ 	priv->pdev = pdev;
+-	priv->pldata = dev_get_platdata(&pdev->dev);
+ 	priv->netdev = dev;
++	priv->tx_irq = irqres[0].start;
++	priv->rx_irq = irqres[1].start;
++	err = of_get_phy_mode(pdev->dev.of_node, &priv->mii_mode);
++	if (err)
++		pr_err("Can't find phy-mode for port\n");
++
++	of_get_mac_address(pdev->dev.of_node, priv->mac);
++
++	priv->clk_ppe = clk_get(&pdev->dev, NULL);
++	if (IS_ERR(priv->clk_ppe))
++		return PTR_ERR(priv->clk_ppe);
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		priv->clk_switch = clk_get(&pdev->dev, "switch");
++		if (IS_ERR(priv->clk_switch))
++			return PTR_ERR(priv->clk_switch);
++	}
++	if (of_machine_is_compatible("lantiq,ase")) {
++		priv->clk_ephy = clk_get(&pdev->dev, "ephy");
++		if (IS_ERR(priv->clk_ephy))
++			return PTR_ERR(priv->clk_ephy);
++		priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
++		if (IS_ERR(priv->clk_ephycgu))
++			return PTR_ERR(priv->clk_ephycgu);
++	}
++
+ 	spin_lock_init(&priv->lock);
+ 	SET_NETDEV_DEV(dev, &pdev->dev);
+ 
+@@ -698,15 +936,10 @@ ltq_etop_probe(struct platform_device *p
+ 		goto err_free;
+ 	}
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		if (IS_TX(i))
+-			netif_napi_add_weight(dev, &priv->ch[i].napi,
+-					      ltq_etop_poll_tx, 8);
+-		else if (IS_RX(i))
+-			netif_napi_add_weight(dev, &priv->ch[i].napi,
+-					      ltq_etop_poll_rx, 32);
+-		priv->ch[i].netdev = dev;
+-	}
++	netif_napi_add_weight(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
++	netif_napi_add_weight(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
++	priv->txch.netdev = dev;
++	priv->rxch.netdev = dev;
+ 
+ 	err = register_netdev(dev);
+ 	if (err)
+@@ -733,31 +966,22 @@ static void ltq_etop_remove(struct platf
+ 	}
+ }
+ 
++static const struct of_device_id ltq_etop_match[] = {
++	{ .compatible = "lantiq,etop-xway" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ltq_etop_match);
++
+ static struct platform_driver ltq_mii_driver = {
++	.probe = ltq_etop_probe,
+ 	.remove_new = ltq_etop_remove,
+ 	.driver = {
+ 		.name = "ltq_etop",
++		.of_match_table = ltq_etop_match,
+ 	},
+ };
+ 
+-static int __init
+-init_ltq_etop(void)
+-{
+-	int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
+-
+-	if (ret)
+-		pr_err("ltq_etop: Error registering platform driver!");
+-	return ret;
+-}
+-
+-static void __exit
+-exit_ltq_etop(void)
+-{
+-	platform_driver_unregister(&ltq_mii_driver);
+-}
+-
+-module_init(init_ltq_etop);
+-module_exit(exit_ltq_etop);
++module_platform_driver(ltq_mii_driver);
+ 
+ MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+ MODULE_DESCRIPTION("Lantiq SoC ETOP");

target/linux/lantiq/patches-6.12/035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch

@@ -0,0 +1,239 @@
+From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 10 Sep 2014 22:42:14 +0200
+Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   3 +
+ arch/mips/lantiq/xway/Makefile                     |   3 +
+ arch/mips/lantiq/xway/ath5k_eep.c                  | 136 +++++++++++++++++++++
+ arch/mips/lantiq/xway/eth_mac.c                    |  25 ++++
+ drivers/net/ethernet/lantiq_etop.c                 |   6 +-
+ 5 files changed, 172 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c
+ create mode 100644 arch/mips/lantiq/xway/eth_mac.c
+
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -99,5 +99,8 @@ extern __iomem void *ltq_cgu_membase;
+ extern void ltq_pmu_enable(unsigned int module);
+ extern void ltq_pmu_disable(unsigned int module);
+ 
++/* allow the ethernet driver to load a flash mapped mac addr */
++const u8* ltq_get_eth_mac(void);
++
+ #endif /* CONFIG_SOC_TYPE_XWAY */
+ #endif /* _LTQ_XWAY_H__ */
+--- a/arch/mips/lantiq/xway/Makefile
++++ b/arch/mips/lantiq/xway/Makefile
+@@ -8,3 +8,6 @@ obj-y += timer.o
+ endif
+ 
+ obj-y += vmmc.o
++
++obj-y += eth_mac.o
++obj-$(CONFIG_PCI) += ath5k_eep.o
+--- /dev/null
++++ b/arch/mips/lantiq/xway/ath5k_eep.c
+@@ -0,0 +1,135 @@
++/*
++ *  Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
++ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ *  Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
++ *  Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
++ *  Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
++ *  Copyright (C) 2015 Vittorio Gambaletta <openwrt@vittgam.net>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/etherdevice.h>
++#include <linux/ath5k_platform.h>
++#include <linux/pci.h>
++#include <linux/err.h>
++#include <linux/mtd/mtd.h>
++#include <lantiq_soc.h>
++
++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
++struct ath5k_platform_data ath5k_pdata;
++static u8 athxk_eeprom_mac[6];
++
++static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
++{
++	dev->dev.platform_data = &ath5k_pdata;
++	return 0;
++}
++
++static int ath5k_eep_load;
++static int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node, *mtd_np = NULL;
++	int mac_offset;
++	u32 mac_inc = 0;
++	int i;
++	struct mtd_info *the_mtd;
++	size_t flash_readlen;
++	const __be32 *list;
++	const char *part;
++	phandle phandle;
++
++	list = of_get_property(np, "ath,eep-flash", &i);
++	if (!list || (i != (2 * sizeof(*list))))
++		return -ENODEV;
++
++	phandle = be32_to_cpup(list++);
++	if (phandle)
++		mtd_np = of_find_node_by_phandle(phandle);
++
++	if (!mtd_np)
++		return -ENODEV;
++
++	part = of_get_property(mtd_np, "label", NULL);
++	if (!part)
++		part = mtd_np->name;
++
++	the_mtd = get_mtd_device_nm(part);
++	if (IS_ERR(the_mtd))
++		return -ENODEV;
++
++	ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL);
++
++	i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1,
++		&flash_readlen, (void *) ath5k_pdata.eeprom_data);
++
++	if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
++		size_t mac_readlen;
++		mtd_read(the_mtd, mac_offset, 6, &mac_readlen,
++			(void *) athxk_eeprom_mac);
++	}
++	put_mtd_device(the_mtd);
++
++	if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) {
++		dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
++		return -ENODEV;
++	}
++
++	if (of_find_property(np, "ath,eep-swap", NULL))
++		for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)
++			ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]);
++
++	if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac())
++		ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac());
++
++	if (!is_valid_ether_addr(athxk_eeprom_mac)) {
++		dev_warn(&pdev->dev, "using random mac\n");
++		eth_random_addr(athxk_eeprom_mac);
++	}
++
++	if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
++		athxk_eeprom_mac[5] += mac_inc;
++
++	ath5k_pdata.macaddr = athxk_eeprom_mac;
++	ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
++
++	dev_info(&pdev->dev, "loaded ath5k eeprom\n");
++
++	return 0;
++}
++
++static struct of_device_id ath5k_eeprom_ids[] = {
++	{ .compatible = "ath5k,eeprom" },
++	{ }
++};
++
++static struct platform_driver ath5k_eeprom_driver = {
++	.driver		= {
++		.name		= "ath5k,eeprom",
++		.of_match_table	= ath5k_eeprom_ids,
++	},
++};
++
++static int __init of_ath5k_eeprom_init(void)
++{
++	int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
++
++	if (ret)
++		ath5k_eep_load = 1;
++
++	return ret;
++}
++
++static int __init of_ath5k_eeprom_init_late(void)
++{
++	if (!ath5k_eep_load)
++		return 0;
++
++	return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
++}
++late_initcall(of_ath5k_eeprom_init_late);
++subsys_initcall(of_ath5k_eeprom_init);
+--- /dev/null
++++ b/arch/mips/lantiq/xway/eth_mac.c
+@@ -0,0 +1,26 @@
++/*
++ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <lantiq_soc.h>
++#include <linux/init.h>
++#include <linux/if_ether.h>
++
++static u8 eth_mac[6];
++static int eth_mac_set;
++
++const u8* ltq_get_eth_mac(void)
++{
++	return eth_mac;
++}
++
++static int __init setup_ethaddr(char *str)
++{
++	eth_mac_set = mac_pton(str, eth_mac);
++	return !eth_mac_set;
++}
++early_param("ethaddr", setup_ethaddr);
+--- a/arch/mips/pci/fixup-lantiq.c
++++ b/arch/mips/pci/fixup-lantiq.c
+@@ -9,12 +9,18 @@
+ #include <linux/pci.h>
+ #include "ifxmips_pci_common.h"
+ 
++int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL;
++
+ int pcibios_plat_dev_init(struct pci_dev *dev)
+ {
+ #ifdef CONFIG_PCIE_LANTIQ
+ 	if (pci_find_capability(dev, PCI_CAP_ID_EXP))
+ 		ifx_pcie_bios_plat_dev_init(dev);
+ #endif
++
++	if (ltq_pci_plat_dev_init)
++		return ltq_pci_plat_dev_init(dev);
++
+ 	return 0;
+ }
+ 
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -771,7 +771,11 @@ ltq_etop_init(struct net_device *dev)
+ 	if (err)
+ 		goto err_hw;
+ 
+-	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
++	memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN);
++
++	if (!is_valid_ether_addr(mac.sa_data))
++		memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
++
+ 	if (!is_valid_ether_addr(mac.sa_data)) {
+ 		pr_warn("etop: invalid MAC, using random\n");
+ 		eth_random_addr(mac.sa_data);

target/linux/lantiq/patches-6.12/042-arch-mips-increase-io_space_limit.patch

@@ -0,0 +1,24 @@
+From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Fri, 3 Jun 2016 13:12:20 +0200
+Subject: [PATCH] arch: mips: increase io_space_limit
+
+this value comes from x86 and breaks some pci devices
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/include/asm/mach-lantiq/spaces.h | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/spaces.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/spaces.h
+@@ -0,0 +1,8 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef __ASM_MACH_LANTIQ_SPACES_H_
++#define __ASM_MACH_LANTIQ_SPACES_H_
++
++#define IO_SPACE_LIMIT  0xffffffff
++
++#include <asm/mach-generic/spaces.h>
++#endif

target/linux/lantiq/patches-6.12/101-find_active_root.patch

@@ -0,0 +1,103 @@
+From 2c82524000cca691c89c9fda251b55ef04eabcb6 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <openwrt@kresin.me>
+Date: Mon, 2 May 2016 18:50:00 +0000
+Subject: [PATCH] find active root
+
+Signed-off-by: Mathias Kresin <openwrt@kresin.me>
+---
+ drivers/mtd/parsers/ofpart_core.c | 49 ++++++++++++++++++++++++++++++-
+ 1 file changed, 48 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/parsers/ofpart_core.c
++++ b/drivers/mtd/parsers/ofpart_core.c
+@@ -38,6 +38,38 @@ static bool node_has_compatible(struct d
+ 	return of_get_property(pp, "compatible", NULL);
+ }
+ 
++static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master,
++						loff_t offset)
++{
++	static uint8_t root_id;
++	int err, len;
++
++	err = mtd_read(master, offset, 0x01, &len, &root_id);
++
++	if (mtd_is_bitflip(err) || !err)
++		return &root_id;
++
++	return NULL;
++}
++
++static void brnboot_set_active_root_part(struct mtd_partition *pparts,
++					 struct device_node **part_nodes,
++					 int nr_parts,
++					 uint8_t *root_id)
++{
++	int i;
++
++	for (i = 0; i < nr_parts; i++) {
++		int part_root_id;
++
++		if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id)
++		    && part_root_id == *root_id) {
++			pparts[i].name = "firmware";
++			break;
++		}
++	}
++}
++
+ static int parse_fixed_partitions(struct mtd_info *master,
+ 				  const struct mtd_partition **pparts,
+ 				  struct mtd_part_parser_data *data)
+@@ -51,6 +83,8 @@ static int parse_fixed_partitions(struct
+ 	struct device_node *pp;
+ 	int nr_parts, i, ret = 0;
+ 	bool dedicated = true;
++	uint8_t *proot_id = NULL;
++	struct device_node **part_nodes;
+ 
+ 	/* Pull of_node from the master device node */
+ 	mtd_node = mtd_get_of_node(master);
+@@ -95,7 +129,9 @@ static int parse_fixed_partitions(struct
+ 		return 0;
+ 
+ 	parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
+-	if (!parts)
++	part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL);
++
++	if (!parts || !part_nodes)
+ 		return -ENOMEM;
+ 
+ 	i = 0;
+@@ -166,6 +202,11 @@ static int parse_fixed_partitions(struct
+ 		if (of_property_read_bool(pp, "slc-mode"))
+ 			parts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION;
+ 
++		if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector"))
++			proot_id = brnboot_get_selected_root_part(master, parts[i].offset);
++
++		part_nodes[i] = pp;
++
+ 		i++;
+ 	}
+ 
+@@ -175,6 +216,11 @@ static int parse_fixed_partitions(struct
+ 	if (quirks && quirks->post_parse)
+ 		quirks->post_parse(master, parts, nr_parts);
+ 
++	if (proot_id)
++		brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id);
++
++	kfree(part_nodes);
++
+ 	*pparts = parts;
+ 	return nr_parts;
+ 
+@@ -185,6 +231,7 @@ ofpart_fail:
+ ofpart_none:
+ 	of_node_put(pp);
+ 	kfree(parts);
++	kfree(part_nodes);
+ 	return ret;
+ }
+ 

target/linux/lantiq/patches-6.12/102-01-MIPS-lantiq-xway-mark-ltq_ar9_sys_hz-as-static.patch

@@ -0,0 +1,27 @@
+From 3004522ddba0a23941222d2044badd4436ce776f Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 18:08:35 +0800
+Subject: [PATCH 01/16] MIPS: lantiq: xway: mark ltq_ar9_sys_hz() as static
+
+Fix the following missing-prototypes warning:
+
+arch/mips/lantiq/xway/clk.c:77:15: error: no previous prototype for 'ltq_ar9_sys_hz' [-Werror=missing-prototypes]
+   77 | unsigned long ltq_ar9_sys_hz(void)
+      |               ^~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/xway/clk.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/lantiq/xway/clk.c
++++ b/arch/mips/lantiq/xway/clk.c
+@@ -74,7 +74,7 @@ unsigned long ltq_danube_pp32_hz(void)
+ 	return clk;
+ }
+ 
+-unsigned long ltq_ar9_sys_hz(void)
++static unsigned long ltq_ar9_sys_hz(void)
+ {
+ 	if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
+ 		return CLOCK_393M;

target/linux/lantiq/patches-6.12/102-02-MIPS-lantiq-xway-mark-dma_init-as-static.patch

@@ -0,0 +1,27 @@
+From ada0c7fd1b2e6daaf64bf8649cc58afaceed1a3d Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 18:11:41 +0800
+Subject: [PATCH 02/16] MIPS: lantiq: xway: mark dma_init() as static
+
+Fix the following missing-prototypes build warning:
+
+arch/mips/lantiq/xway/dma.c:293:1: error: no previous prototype for 'dma_init' [-Werror=missing-prototypes]
+  293 | dma_init(void)
+      | ^~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/xway/dma.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/lantiq/xway/dma.c
++++ b/arch/mips/lantiq/xway/dma.c
+@@ -289,7 +289,7 @@ static struct platform_driver dma_driver
+ 	},
+ };
+ 
+-int __init
++static int __init
+ dma_init(void)
+ {
+ 	return platform_driver_register(&dma_driver);

target/linux/lantiq/patches-6.12/102-03-MIPS-lantiq-xway-mark-dcdc_init-as-static.patch

@@ -0,0 +1,27 @@
+From d27f9ab0f53886152b717e44eeca0217519ad323 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 18:18:26 +0800
+Subject: [PATCH 03/16] MIPS: lantiq: xway: mark dcdc_init() as static
+
+Fix the following missing-prototypes build warning:
+
+arch/mips/lantiq/xway/dcdc.c:49:12: error: no previous prototype for 'dcdc_init' [-Werror=missing-prototypes]
+   49 | int __init dcdc_init(void)
+      |            ^~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/xway/dcdc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/lantiq/xway/dcdc.c
++++ b/arch/mips/lantiq/xway/dcdc.c
+@@ -46,7 +46,7 @@ static struct platform_driver dcdc_drive
+ 	},
+ };
+ 
+-int __init dcdc_init(void)
++static int __init dcdc_init(void)
+ {
+ 	int ret = platform_driver_register(&dcdc_driver);
+ 

target/linux/lantiq/patches-6.12/102-04-MIPS-lantiq-irq-fix-misc-missing-prototypes-warnings.patch

@@ -0,0 +1,42 @@
+From 9729233d2ef318cdb6954c8b5cb032d7d0f03473 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 19:53:12 +0800
+Subject: [PATCH 04/16] MIPS: lantiq: irq: fix misc missing-prototypes warnings
+
+Fix the following build warnings:
+
+arch/mips/lantiq/irq.c:340:12: error: no previous prototype for 'icu_of_init' [-Werror=missing-prototypes]
+  340 | int __init icu_of_init(struct device_node *node, struct device_node *parent)
+      |            ^~~~~~~~~~~
+arch/mips/lantiq/irq.c:418:5: error: no previous prototype for 'get_c0_perfcount_int' [-Werror=missing-prototypes]
+  418 | int get_c0_perfcount_int(void)
+      |     ^~~~~~~~~~~~~~~~~~~~
+arch/mips/lantiq/irq.c:424:14: error: no previous prototype for 'get_c0_compare_int' [-Werror=missing-prototypes]
+  424 | unsigned int get_c0_compare_int(void)
+      |              ^~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/irq.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/lantiq/irq.c
++++ b/arch/mips/lantiq/irq.c
+@@ -17,6 +17,7 @@
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/irq_cpu.h>
++#include <asm/time.h>
+ 
+ #include <lantiq_soc.h>
+ #include <irq.h>
+@@ -337,7 +338,8 @@ static const struct irq_domain_ops irq_d
+ 	.map = icu_map,
+ };
+ 
+-int __init icu_of_init(struct device_node *node, struct device_node *parent)
++static int __init
++icu_of_init(struct device_node *node, struct device_node *parent)
+ {
+ 	struct device_node *eiu_node;
+ 	struct resource res;

target/linux/lantiq/patches-6.12/102-05-MIPS-lantiq-xway-add-prototype-for-ltq_get_cp1_base.patch

@@ -0,0 +1,29 @@
+From 5759385fb2b1fafcb0073add3cf4dc7a918ac7f2 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 20:19:15 +0800
+Subject: [PATCH 05/16] MIPS: lantiq: xway: add prototype for
+ ltq_get_cp1_base()
+
+ltq_get_cp1_base() is an exported function, we must define
+its prototype on header file. Fix warning:
+
+arch/mips/lantiq/xway/vmmc.c:22:15: error: no previous prototype for 'ltq_get_cp1_base' [-Werror=missing-prototypes]
+   22 | unsigned int *ltq_get_cp1_base(void)
+      |               ^~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -102,5 +102,8 @@ extern void ltq_pmu_disable(unsigned int
+ /* allow the ethernet driver to load a flash mapped mac addr */
+ const u8* ltq_get_eth_mac(void);
+ 
++/* VMMC */
++extern unsigned int *ltq_get_cp1_base(void);
++
+ #endif /* CONFIG_SOC_TYPE_XWAY */
+ #endif /* _LTQ_XWAY_H__ */

target/linux/lantiq/patches-6.12/102-06-MIPS-pci-lantiq-marks-pcibios_init-as-static.patch

@@ -0,0 +1,27 @@
+From 156977363d9ed39d80062044704932d8c11d1611 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 20:31:33 +0800
+Subject: [PATCH 06/16] MIPS: pci: lantiq: marks pcibios_init() as static
+
+Fix the following missing-prototypes build warning:
+
+arch/mips/pci/pci-lantiq.c:239:12: error: no previous prototype for 'pcibios_init' [-Werror=missing-prototypes]
+  239 | int __init pcibios_init(void)
+      |            ^~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/pci/pci-lantiq.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -234,7 +234,7 @@ static struct platform_driver ltq_pci_dr
+ 	},
+ };
+ 
+-int __init pcibios_init(void)
++static int __init pcibios_init(void)
+ {
+ 	int ret = platform_driver_register(&ltq_pci_driver);
+ 	if (ret)

target/linux/lantiq/patches-6.12/102-07-MIPS-lantiq-falcon-fix-misc-missing-prototypes-warni.patch

@@ -0,0 +1,39 @@
+From 6900665e987f7c76dff709d63be4df4171c02ab2 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:15:36 +0800
+Subject: [PATCH 07/16] MIPS: lantiq: falcon: fix misc missing-prototypes
+ warnings
+
+Fix the following build warnings:
+
+arch/mips/lantiq/falcon/prom.c:39:13: error: no previous prototype for 'ltq_soc_nmi_setup' [-Werror=missing-prototypes]
+   39 | void __init ltq_soc_nmi_setup(void)
+      |             ^~~~~~~~~~~~~~~~~
+arch/mips/lantiq/falcon/prom.c:46:13: error: no previous prototype for 'ltq_soc_ejtag_setup' [-Werror=missing-prototypes]
+   46 | void __init ltq_soc_ejtag_setup(void)
+      |             ^~~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/falcon/prom.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/lantiq/falcon/prom.c
++++ b/arch/mips/lantiq/falcon/prom.c
+@@ -36,14 +36,14 @@
+ #define BOOT_NVEC	(BOOT_REG_BASE | 0x04)
+ #define BOOT_EVEC	(BOOT_REG_BASE | 0x08)
+ 
+-void __init ltq_soc_nmi_setup(void)
++static void __init ltq_soc_nmi_setup(void)
+ {
+ 	extern void (*nmi_handler)(void);
+ 
+ 	ltq_w32((unsigned long)&nmi_handler, (void *)BOOT_NVEC);
+ }
+ 
+-void __init ltq_soc_ejtag_setup(void)
++static void __init ltq_soc_ejtag_setup(void)
+ {
+ 	extern void (*ejtag_debug_handler)(void);
+ 

target/linux/lantiq/patches-6.12/102-08-MIPS-lantiq-falcon-sysctrl-remove-unused-falcon_trig.patch

@@ -0,0 +1,31 @@
+From b145074ce653a895201bf8a2ba70719a107ad580 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:15:36 +0800
+Subject: [PATCH 08/16] MIPS: lantiq: falcon: sysctrl: remove unused
+ falcon_trigger_hrst()
+
+This is a defined but unused function. Fix warning:
+
+arch/mips/lantiq/falcon/sysctrl.c:75:6: error: no previous prototype for 'falcon_trigger_hrst' [-Werror=missing-prototypes]
+   75 | void falcon_trigger_hrst(int level)
+      |      ^~~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/falcon/sysctrl.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+--- a/arch/mips/lantiq/falcon/sysctrl.c
++++ b/arch/mips/lantiq/falcon/sysctrl.c
+@@ -72,11 +72,6 @@
+ static void __iomem *sysctl_membase[3], *status_membase;
+ void __iomem *ltq_sys1_membase, *ltq_ebu_membase;
+ 
+-void falcon_trigger_hrst(int level)
+-{
+-	sysctl_w32(SYSCTL_SYS1, level & 1, SYS1_HRSTOUTC);
+-}
+-
+ static inline void sysctl_wait(struct clk *clk,
+ 		unsigned int test, unsigned int reg)
+ {

target/linux/lantiq/patches-6.12/102-09-MIPS-lantiq-falcon-sysctrl-add-missing-header-prom.h.patch

@@ -0,0 +1,27 @@
+From cc7803436c2419009aaf702d96fc1d717ca52279 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:15:36 +0800
+Subject: [PATCH 09/16] MIPS: lantiq: falcon: sysctrl: add missing header
+ prom.h
+
+"prom.h" includes the prototype of ltq_soc_init(). Fix warning:
+
+arch/mips/lantiq/falcon/sysctrl.c:185:13: error: no previous prototype for 'ltq_soc_init' [-Werror=missing-prototypes]
+  185 | void __init ltq_soc_init(void)
+      |             ^~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/falcon/sysctrl.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/lantiq/falcon/sysctrl.c
++++ b/arch/mips/lantiq/falcon/sysctrl.c
+@@ -14,6 +14,7 @@
+ #include <lantiq_soc.h>
+ 
+ #include "../clk.h"
++#include "../prom.h"
+ 
+ /* infrastructure control register */
+ #define SYS1_INFRAC		0x00bc

target/linux/lantiq/patches-6.12/102-10-MIPS-lantiq-falcon-sysctrl-fix-request-memory-check-.patch

@@ -0,0 +1,64 @@
+From ccdf5d58c4f3330a83393641d4e4334994fc91af Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:53:58 +0800
+Subject: [PATCH 10/16] MIPS: lantiq: falcon: sysctrl: fix request memory check
+ logic
+
+request_mem_region() will return NULL instead of error code
+when the memory request fails. Therefore, we should check if
+the return value is non-zero instead of less than zero. In
+this way, this patch also fixes the build warnings:
+
+arch/mips/lantiq/falcon/sysctrl.c:214:50: error: ordered comparison of pointer with integer zero [-Werror=extra]
+  214 |                                 res_status.name) < 0) ||
+      |                                                  ^
+arch/mips/lantiq/falcon/sysctrl.c:216:47: error: ordered comparison of pointer with integer zero [-Werror=extra]
+  216 |                                 res_ebu.name) < 0) ||
+      |                                               ^
+arch/mips/lantiq/falcon/sysctrl.c:219:50: error: ordered comparison of pointer with integer zero [-Werror=extra]
+  219 |                                 res_sys[0].name) < 0) ||
+      |                                                  ^
+arch/mips/lantiq/falcon/sysctrl.c:222:50: error: ordered comparison of pointer with integer zero [-Werror=extra]
+  222 |                                 res_sys[1].name) < 0) ||
+      |                                                  ^
+arch/mips/lantiq/falcon/sysctrl.c:225:50: error: ordered comparison of pointer with integer zero [-Werror=extra]
+  225 |                                 res_sys[2].name) < 0))
+      |
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/falcon/sysctrl.c | 23 ++++++++++-------------
+ 1 file changed, 10 insertions(+), 13 deletions(-)
+
+--- a/arch/mips/lantiq/falcon/sysctrl.c
++++ b/arch/mips/lantiq/falcon/sysctrl.c
+@@ -210,19 +210,16 @@ void __init ltq_soc_init(void)
+ 	of_node_put(np_syseth);
+ 	of_node_put(np_sysgpe);
+ 
+-	if ((request_mem_region(res_status.start, resource_size(&res_status),
+-				res_status.name) < 0) ||
+-		(request_mem_region(res_ebu.start, resource_size(&res_ebu),
+-				res_ebu.name) < 0) ||
+-		(request_mem_region(res_sys[0].start,
+-				resource_size(&res_sys[0]),
+-				res_sys[0].name) < 0) ||
+-		(request_mem_region(res_sys[1].start,
+-				resource_size(&res_sys[1]),
+-				res_sys[1].name) < 0) ||
+-		(request_mem_region(res_sys[2].start,
+-				resource_size(&res_sys[2]),
+-				res_sys[2].name) < 0))
++	if ((!request_mem_region(res_status.start, resource_size(&res_status),
++				 res_status.name)) ||
++	    (!request_mem_region(res_ebu.start, resource_size(&res_ebu),
++				 res_ebu.name)) ||
++	    (!request_mem_region(res_sys[0].start, resource_size(&res_sys[0]),
++				 res_sys[0].name)) ||
++	    (!request_mem_region(res_sys[1].start, resource_size(&res_sys[1]),
++				 res_sys[1].name)) ||
++	    (!request_mem_region(res_sys[2].start, resource_size(&res_sys[2]),
++				 res_sys[2].name)))
+ 		pr_err("Failed to request core resources");
+ 
+ 	status_membase = ioremap(res_status.start,

target/linux/lantiq/patches-6.12/102-11-MIPS-lantiq-xway-gptu-mark-gptu_init-as-static.patch

@@ -0,0 +1,27 @@
+From 2caf57c67c6c3228b7a2ff1510e7671539ad31d3 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 22:29:34 +0800
+Subject: [PATCH 11/16] MIPS: lantiq: xway: gptu: mark gptu_init() as static
+
+Fix the following missing-prototypes warning:
+
+arch/mips/lantiq/xway/gptu.c:197:12: error: no previous prototype for 'gptu_init' [-Werror=missing-prototypes]
+  197 | int __init gptu_init(void)
+      |            ^~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/xway/gptu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/lantiq/xway/gptu.c
++++ b/arch/mips/lantiq/xway/gptu.c
+@@ -194,7 +194,7 @@ static struct platform_driver dma_driver
+ 	},
+ };
+ 
+-int __init gptu_init(void)
++static int __init gptu_init(void)
+ {
+ 	int ret = platform_driver_register(&dma_driver);
+ 

target/linux/lantiq/patches-6.12/102-12-MIPS-vpe-mt-mark-vpe_free-and-vpe_stop-as-static.patch

@@ -0,0 +1,52 @@
+From 6faade177216b41a8112e33c6e73377e78dd1f92 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 18:32:11 +0800
+Subject: [PATCH 12/16] MIPS: vpe-mt: mark vpe_free() and vpe_stop() as static
+
+These functions are only used in the current source file "vpe-mt.c".
+Do not export them and mark them as static to silence the missing
+prototypes warnings:
+
+arch/mips/kernel/vpe-mt.c:208:5: error: no previous prototype for 'vpe_stop' [-Werror=missing-prototypes]
+  208 | int vpe_stop(void *vpe)
+      |     ^~~~~~~~
+arch/mips/kernel/vpe-mt.c:229:5: error: no previous prototype for 'vpe_free' [-Werror=missing-prototypes]
+  229 | int vpe_free(void *vpe)
+      |     ^~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/kernel/vpe-mt.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -202,7 +202,7 @@ int vpe_start(void *vpe, unsigned long s
+ EXPORT_SYMBOL(vpe_start);
+ 
+ /* halt it for now */
+-int vpe_stop(void *vpe)
++static int vpe_stop(void *vpe)
+ {
+ 	struct vpe *v = vpe;
+ 	struct tc *t;
+@@ -220,10 +220,9 @@ int vpe_stop(void *vpe)
+ 
+ 	return 0;
+ }
+-EXPORT_SYMBOL(vpe_stop);
+ 
+ /* I've done with it thank you */
+-int vpe_free(void *vpe)
++static int vpe_free(void *vpe)
+ {
+ 	struct vpe *v = vpe;
+ 	struct tc *t;
+@@ -255,7 +254,6 @@ int vpe_free(void *vpe)
+ 
+ 	return 0;
+ }
+-EXPORT_SYMBOL(vpe_free);
+ 
+ static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
+ 			  const char *buf, size_t len)

target/linux/lantiq/patches-6.12/102-13-MIPS-vpe-mt-drop-unused-functions-vpe_alloc-and-vpe_.patch

@@ -0,0 +1,59 @@
+From e6fab4c05f655b834587bc06f0274f69cdc43171 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 18:32:11 +0800
+Subject: [PATCH 13/16] MIPS: vpe-mt: drop unused functions vpe_alloc() and
+ vpe_start()
+
+These two functions are defined but unused. Removing them to silence
+the missing prototypes warnings:
+
+arch/mips/kernel/vpe-mt.c:180:7: error: no previous prototype for 'vpe_alloc' [-Werror=missing-prototypes]
+  180 | void *vpe_alloc(void)
+      |       ^~~~~~~~~
+arch/mips/kernel/vpe-mt.c:198:5: error: no previous prototype for 'vpe_start' [-Werror=missing-prototypes]
+  198 | int vpe_start(void *vpe, unsigned long start)
+      |     ^~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/kernel/vpe-mt.c | 29 -----------------------------
+ 1 file changed, 29 deletions(-)
+
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -172,35 +172,6 @@ void cleanup_tc(struct tc *tc)
+ 	local_irq_restore(flags);
+ }
+ 
+-/* module wrapper entry points */
+-/* give me a vpe */
+-void *vpe_alloc(void)
+-{
+-	int i;
+-	struct vpe *v;
+-
+-	/* find a vpe */
+-	for (i = 1; i < MAX_VPES; i++) {
+-		v = get_vpe(i);
+-		if (v != NULL) {
+-			v->state = VPE_STATE_INUSE;
+-			return v;
+-		}
+-	}
+-	return NULL;
+-}
+-EXPORT_SYMBOL(vpe_alloc);
+-
+-/* start running from here */
+-int vpe_start(void *vpe, unsigned long start)
+-{
+-	struct vpe *v = vpe;
+-
+-	v->__start = start;
+-	return vpe_run(v);
+-}
+-EXPORT_SYMBOL(vpe_start);
+-
+ /* halt it for now */
+ static int vpe_stop(void *vpe)
+ {

target/linux/lantiq/patches-6.12/102-14-pinctrl-xway-mark-xway_pinconf_group_set-as-static.patch

@@ -0,0 +1,34 @@
+From 7d8878668dfe011f33b92a0f9aa3e0d46c1b77ca Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 20:36:56 +0800
+Subject: [PATCH 14/16] pinctrl: xway: mark xway_pinconf_group_set() as static
+
+Fix the following missing-prototypes build warning:
+
+drivers/pinctrl/pinctrl-xway.c:1231:5: error: no previous prototype for 'xway_pinconf_group_set' [-Werror=missing-prototypes]
+ 1231 | int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
+      |     ^~~~~~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/pinctrl/pinctrl-xway.c | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-xway.c
++++ b/drivers/pinctrl/pinctrl-xway.c
+@@ -1228,10 +1228,11 @@ static int xway_pinconf_set(struct pinct
+ 	return 0;
+ }
+ 
+-int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
+-			unsigned selector,
+-			unsigned long *configs,
+-			unsigned num_configs)
++static int
++xway_pinconf_group_set(struct pinctrl_dev *pctldev,
++		       unsigned selector,
++		       unsigned long *configs,
++		       unsigned num_configs)
+ {
+ 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
+ 	int i, ret = 0;

target/linux/lantiq/patches-6.12/102-15-pinctrl-falcon-mark-pinctrl_falcon_init-as-static.patch

@@ -0,0 +1,27 @@
+From 9dec40b4f01a2aa92311b077ef45ecaa335d45a2 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:16:49 +0800
+Subject: [PATCH 15/16] pinctrl: falcon: mark pinctrl_falcon_init() as static
+
+Fix the following missing-prototypes build warning:
+
+drivers/pinctrl/pinctrl-falcon.c:508:12: error: no previous prototype for 'pinctrl_falcon_init' [-Werror=missing-prototypes]
+  508 | int __init pinctrl_falcon_init(void)
+      |            ^~~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/pinctrl/pinctrl-falcon.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/pinctrl-falcon.c
++++ b/drivers/pinctrl/pinctrl-falcon.c
+@@ -505,7 +505,7 @@ static struct platform_driver pinctrl_fa
+ 	},
+ };
+ 
+-int __init pinctrl_falcon_init(void)
++static int __init pinctrl_falcon_init(void)
+ {
+ 	return platform_driver_register(&pinctrl_falcon_driver);
+ }

target/linux/lantiq/patches-6.12/102-16-spi-falcon-mark-falcon_sflash_xfer-as-static.patch

@@ -0,0 +1,30 @@
+From 28b20e002412bcadd4de74235faff275efb9e2cd Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:21:02 +0800
+Subject: [PATCH 16/16] spi: falcon: mark falcon_sflash_xfer() as static
+
+Fix the following missing-prototypes build warning:
+
+drivers/spi/spi-falcon.c:97:5: error: no previous prototype for 'falcon_sflash_xfer' [-Werror=missing-prototypes]
+   97 | int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
+      |     ^~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/spi/spi-falcon.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/spi/spi-falcon.c
++++ b/drivers/spi/spi-falcon.c
+@@ -94,8 +94,9 @@ struct falcon_sflash {
+ 	struct spi_controller *host;
+ };
+ 
+-int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
+-		unsigned long flags)
++static int
++falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
++		   unsigned long flags)
+ {
+ 	struct device *dev = &spi->dev;
+ 	struct falcon_sflash *priv = spi_controller_get_devdata(spi->controller);

target/linux/lantiq/patches-6.12/151-lantiq-ifxmips_pcie-use-of.patch

@@ -0,0 +1,486 @@
+From 1d1885f4a7abd7272f47b835b03d8662fb981d19 Mon Sep 17 00:00:00 2001
+From: Eddi De Pieri <eddi@depieri.net>
+Date: Tue, 14 Oct 2014 11:04:00 +0000
+Subject: [PATCH] MIPS: lantiq: ifxmips_pcie: use of
+
+Signed-off-by: Eddi De Pieri <eddi@depieri.net>
+---
+ arch/mips/pci/Makefile           |   2 +-
+ arch/mips/pci/ifxmips_pcie.c     | 151 +++++++++++++++++++++++++++----
+ arch/mips/pci/ifxmips_pcie_vr9.h | 105 ---------------------
+ 3 files changed, 133 insertions(+), 125 deletions(-)
+
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -41,7 +41,7 @@ obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o
+ obj-$(CONFIG_SOC_MT7620)	+= pci-mt7620.o
+ obj-$(CONFIG_SOC_RT288X)	+= pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
+-obj-$(CONFIG_PCIE_LANTIQ)	+= ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o
++obj-$(CONFIG_PCIE_LANTIQ)	+= ifxmips_pcie.o fixup-lantiq-pcie.o
+ obj-$(CONFIG_PCIE_LANTIQ_MSI)	+= pcie-lantiq-msi.o
+ obj-$(CONFIG_SOC_TX4927)	+= pci-tx4927.o
+ obj-$(CONFIG_SOC_TX4938)	+= pci-tx4938.o
+--- a/arch/mips/pci/ifxmips_pcie.c
++++ b/arch/mips/pci/ifxmips_pcie.c
+@@ -16,8 +16,16 @@
+ #include <asm/paccess.h>
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
++#include <linux/phy/phy.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ 
++#include <linux/of_gpio.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++
+ #include "ifxmips_pcie.h"
+ #include "ifxmips_pcie_reg.h"
+ 
+@@ -25,11 +33,6 @@
+ #define IFX_PCIE_ERROR_INT
+ #define IFX_PCIE_IO_32BIT
+ 
+-#define IFX_PCIE_IR                     (INT_NUM_IM4_IRL0 + 25)
+-#define IFX_PCIE_INTA                   (INT_NUM_IM4_IRL0 + 8)
+-#define IFX_PCIE_INTB                   (INT_NUM_IM4_IRL0 + 9)
+-#define IFX_PCIE_INTC                   (INT_NUM_IM4_IRL0 + 10)
+-#define IFX_PCIE_INTD                   (INT_NUM_IM4_IRL0 + 11)
+ #define MS(_v, _f)  (((_v) & (_f)) >> _f##_S)
+ #define SM(_v, _f)  (((_v) << _f##_S) & (_f))
+ #define IFX_REG_SET_BIT(_f, _r) \
+@@ -40,30 +43,30 @@
+ static DEFINE_SPINLOCK(ifx_pcie_lock);
+ 
+ u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
++static int pcie_reset_gpio;
++static struct phy *ltq_pcie_phy;
++static struct reset_control *ltq_pcie_reset;
++static struct regmap *ltq_rcu_regmap;
++static bool switch_pcie_endianess;
+ 
+ static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
+     {
+         .ir_irq = {
+-            .irq  = IFX_PCIE_IR,
+             .name = "ifx_pcie_rc0",
+         },
+ 
+         .legacy_irq = {
+             {
+                 .irq_bit = PCIE_IRN_INTA,
+-                .irq     = IFX_PCIE_INTA,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTB,
+-                .irq     = IFX_PCIE_INTB,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTC,
+-                .irq     = IFX_PCIE_INTC,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTD,
+-                .irq     = IFX_PCIE_INTD,
+             },
+         },
+     },
+@@ -82,6 +85,22 @@ void ifx_pcie_debug(const char *fmt, ...
+ 	printk("%s", buf);
+ }
+ 
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++	gpio_direction_output(pcie_reset_gpio, 1);
++	gpio_set_value(pcie_reset_gpio, 1);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++	gpio_set_value(pcie_reset_gpio, 0);
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++	mdelay(100);
++	gpio_direction_output(pcie_reset_gpio, 1);
++}
+ 
+ static inline int pcie_ltssm_enable(int pcie_port)
+ {
+@@ -857,7 +876,8 @@ pcie_rc_core_int_init(int pcie_port)
+ 	ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0,
+ 		pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]);
+ 	if (ret)
+-		printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR);
++		printk(KERN_ERR "%s request irq %d failed\n", __func__,
++		       pcie_irqs[pcie_port].ir_irq.irq);
+ 
+ 	return ret;
+ }
+@@ -988,10 +1008,26 @@ int  ifx_pcie_bios_plat_dev_init(struct
+ static int
+ pcie_rc_initialize(int pcie_port)
+ {
+-	int i;
++	int i, ret;
+ #define IFX_PCIE_PHY_LOOP_CNT  5
+ 
+-	pcie_rcu_endian_setup(pcie_port);
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M,
++			   IFX_RCU_AHB_BE_PCIE_M);
++
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
++			   IFX_RCU_AHB_BE_PCIE_S);
++       if (switch_pcie_endianess) {
++	        regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_S,
++			           IFX_RCU_AHB_BE_XBAR_S);
++       }
++#else
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
++			   0x0);
++#endif
++
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M,
++			   0x0);
+ 
+ 	pcie_ep_gpio_rst_init(pcie_port);
+ 
+@@ -1000,26 +1036,21 @@ pcie_rc_initialize(int pcie_port)
+ 	* reset PCIe PHY will solve this issue 
+ 	*/
+ 	for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
+-		/* Disable PCIe PHY Analog part for sanity check */
+-		pcie_phy_pmu_disable(pcie_port);
+-
+-		pcie_phy_rst_assert(pcie_port);
+-		pcie_phy_rst_deassert(pcie_port);
+-
+-		/* Make sure PHY PLL is stable */
+-		udelay(20);
+-
+-		/* PCIe Core reset enabled, low active, sw programmed */
+-		pcie_core_rst_assert(pcie_port);
++		ret = phy_init(ltq_pcie_phy);
++		if (ret)
++			continue;
+ 
+ 		/* Put PCIe EP in reset status */
+ 		pcie_device_rst_assert(pcie_port);
+ 
+-		/* PCI PHY & Core reset disabled, high active, sw programmed */
+-		pcie_core_rst_deassert(pcie_port);
++		udelay(1);
++		reset_control_deassert(ltq_pcie_reset);
+ 
+-		/* Already in a quiet state, program PLL, enable PHY, check ready bit */
+-		pcie_phy_clock_mode_setup(pcie_port);
++		ret = phy_power_on(ltq_pcie_phy);
++		if (ret) {
++			phy_exit(ltq_pcie_phy);
++			continue;
++		}
+ 
+ 		/* Enable PCIe PHY and Clock */
+ 		pcie_core_pmu_setup(pcie_port);
+@@ -1035,6 +1066,10 @@ pcie_rc_initialize(int pcie_port)
+ 		/* Once link is up, break out */
+ 		if (pcie_app_loigc_setup(pcie_port) == 0)
+ 			break;
++
++		phy_power_off(ltq_pcie_phy);
++		reset_control_assert(ltq_pcie_reset);
++		phy_exit(ltq_pcie_phy);
+ 	}
+ 	if (i >= IFX_PCIE_PHY_LOOP_CNT) {
+ 		printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
+@@ -1045,17 +1080,73 @@ pcie_rc_initialize(int pcie_port)
+ 	return 0;
+ }
+ 
+-static int __init ifx_pcie_bios_init(void)
++static int ifx_pcie_bios_probe(struct platform_device *pdev)
+ {
++    struct device_node *node = pdev->dev.of_node;
+     void __iomem *io_map_base;
+     int pcie_port;
+     int startup_port;
++    struct device_node *np;
++    struct pci_bus *bus;
++
++    /*
++     * In case a PCI device is physical present, the Lantiq PCI driver need
++     * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them
++     * will work.
++     *
++     * In case the lantiq PCI driver is enabled in the device tree, check if
++     * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already
++     * registered.
++     *
++     * It will fail if there is another PCI controller, this controller is
++     * registered before the Lantiq PCIe driver is probe and the lantiq PCI
++     */
++    np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway");
++
++    if (of_device_is_available(np)) {
++        bus = pci_find_next_bus(bus);
++
++        if (!bus)
++	     return -EPROBE_DEFER;
++    }
+ 
+     /* Enable AHB Master/ Slave */
+     pcie_ahb_pmu_setup();
+ 
+     startup_port = IFX_PCIE_PORT0;
+-    
++
++    ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie");
++    if (IS_ERR(ltq_pcie_phy))
++        return dev_err_probe(&pdev->dev, PTR_ERR(ltq_pcie_phy),
++                             "failed to get the PCIe PHY\n");
++
++    ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL);
++    if (IS_ERR(ltq_pcie_reset)) {
++        dev_err(&pdev->dev, "failed to get the PCIe reset line\n");
++        return PTR_ERR(ltq_pcie_reset);
++    }
++
++    if (of_property_read_bool(node, "lantiq,switch-pcie-endianess")) {
++        switch_pcie_endianess = true;
++        dev_info(&pdev->dev, "switch pcie endianess requested\n");
++    } else {
++        switch_pcie_endianess = false;
++    }
++
++    ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu");
++    if (IS_ERR(ltq_rcu_regmap))
++        return PTR_ERR(ltq_rcu_regmap);
++
++    pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
++    if (gpio_is_valid(pcie_reset_gpio)) {
++        int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset");
++        if (ret) {
++            dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio);
++            return ret;
++        }
++        gpio_direction_output(pcie_reset_gpio, 1);
++    }
++
+     for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
+ 	if (pcie_rc_initialize(pcie_port) == 0) {
+ 	    IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", 
+@@ -1066,7 +1157,19 @@ static int __init ifx_pcie_bios_init(voi
+                 IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__);
+                 return -ENOMEM;
+             }
++            pcie_irqs[pcie_port].ir_irq.irq = platform_get_irq(pdev, 0);
++            if (pcie_irqs[pcie_port].ir_irq.irq < 0)
++                return pcie_irqs[pcie_port].ir_irq.irq;
++
++            for (int i = 0; i <= 3; i++){
++                pcie_irqs[pcie_port].legacy_irq[i].irq = platform_get_irq(pdev, i + 1);
++
++                if (pcie_irqs[pcie_port].legacy_irq[i].irq < 0)
++                    return pcie_irqs[pcie_port].legacy_irq[i].irq;
++            }
++
+             ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
++            pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node);
+ 
+             register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
+             /* XXX, clear error status */
+@@ -1083,6 +1186,29 @@ static int __init ifx_pcie_bios_init(voi
+ 
+     return 0;
+ }
++
++static const struct of_device_id ifxmips_pcie_match[] = {
++        { .compatible = "lantiq,pcie-xrx200" },
++        {},
++};
++MODULE_DEVICE_TABLE(of, ifxmips_pcie_match);
++
++static struct platform_driver ltq_pci_driver = {
++        .probe = ifx_pcie_bios_probe,
++        .driver = {
++                .name = "pcie-xrx200",
++                .of_match_table = ifxmips_pcie_match,
++        },
++};
++
++static int __init ifx_pcie_bios_init(void)
++{
++        int ret = platform_driver_register(&ltq_pci_driver);
++        if (ret)
++                pr_info("pcie-xrx200: Error registering platform driver!");
++        return ret;
++}
++
+ arch_initcall(ifx_pcie_bios_init);
+ 
+ MODULE_LICENSE("GPL");
+--- a/arch/mips/pci/ifxmips_pcie_vr9.h
++++ b/arch/mips/pci/ifxmips_pcie_vr9.h
+@@ -22,8 +22,6 @@
+ #include <linux/gpio.h>
+ #include <lantiq_soc.h>
+ 
+-#define IFX_PCIE_GPIO_RESET  494
+-
+ #define IFX_REG_R32    ltq_r32
+ #define IFX_REG_W32    ltq_w32
+ #define CONFIG_IFX_PCIE_HW_SWAP
+@@ -54,21 +52,6 @@
+ #define OUT			((volatile u32*)(IFX_GPIO + 0x0070))
+ 
+ 
+-static inline void pcie_ep_gpio_rst_init(int pcie_port)
+-{
+-
+-	gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset");
+-	gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
+-	gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
+-
+-/*    ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/
+-}
+-
+ static inline void pcie_ahb_pmu_setup(void) 
+ {
+ 	/* Enable AHB bus master/slave */
+@@ -80,24 +63,6 @@ static inline void pcie_ahb_pmu_setup(vo
+     //AHBS_PMU_SETUP(IFX_PMU_ENABLE);
+ }
+ 
+-static inline void pcie_rcu_endian_setup(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
+-#ifdef CONFIG_IFX_PCIE_HW_SWAP
+-    reg |= IFX_RCU_AHB_BE_PCIE_M;
+-    reg |= IFX_RCU_AHB_BE_PCIE_S;
+-    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
+-#else 
+-    reg |= IFX_RCU_AHB_BE_PCIE_M;
+-    reg &= ~IFX_RCU_AHB_BE_PCIE_S;
+-    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
+-#endif /* CONFIG_IFX_PCIE_HW_SWAP */
+-    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
+-    IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
+-}
+-
+ static inline void pcie_phy_pmu_enable(int pcie_port)
+ {
+ 	struct clk *clk;
+@@ -116,17 +81,6 @@ static inline void pcie_phy_pmu_disable(
+ //    PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
+ }
+ 
+-static inline void pcie_pdi_big_endian(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* SRAM2PDI endianness control. */
+-    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
+-    /* Config AHB->PCIe and PDI endianness */
+-    reg |= IFX_RCU_AHB_BE_PCIE_PDI;
+-    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
+-}
+-
+ static inline void pcie_pdi_pmu_enable(int pcie_port)
+ {
+     /* Enable PDI to access PCIe PHY register */
+@@ -136,65 +90,6 @@ static inline void pcie_pdi_pmu_enable(i
+     //PDI_PMU_SETUP(IFX_PMU_ENABLE);
+ }
+ 
+-static inline void pcie_core_rst_assert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-
+-    /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly  */
+-    reg |= 0x00400000;
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_core_rst_deassert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* Make sure one micro-second delay */
+-    udelay(1);
+-
+-    /* Reset PCIe PHY & Core, bit 22 */
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg &= ~0x00400000;
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_phy_rst_assert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg |= 0x00001000; /* Bit 12 */
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_phy_rst_deassert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* Make sure one micro-second delay */
+-    udelay(1);
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg &= ~0x00001000; /* Bit 12 */
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_device_rst_assert(int pcie_port)
+-{
+-	gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
+-//    ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-}
+-
+-static inline void pcie_device_rst_deassert(int pcie_port)
+-{
+-    mdelay(100);
+-	gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
+-//    gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
+-    //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-}
+-
+ static inline void pcie_core_pmu_setup(int pcie_port)
+ {
+ 	struct clk *clk;
+--- a/arch/mips/pci/ifxmips_pcie.h
++++ b/arch/mips/pci/ifxmips_pcie.h
+@@ -96,13 +96,13 @@ struct ifx_pci_controller {
+ };
+ 
+ typedef struct ifx_pcie_ir_irq {
+-    const unsigned int irq;
++    unsigned int irq;
+     const char name[16];
+ }ifx_pcie_ir_irq_t;
+ 
+ typedef struct ifx_pcie_legacy_irq{
+     const u32 irq_bit;
+-    const int irq;
++    int irq;
+ }ifx_pcie_legacy_irq_t;
+ 
+ typedef struct ifx_pcie_irq {

target/linux/lantiq/patches-6.12/152-lantiq-VPE.patch

@@ -0,0 +1,187 @@
+From 4d48a3d1ef6f8d036bd926e3c1f70b56fcc679b2 Mon Sep 17 00:00:00 2001
+From: Stefan Koch <stefan.koch10@gmail.com>
+Date: Thu, 20 Oct 2016 21:32:00 +0200
+Subject: [PATCH] lantiq: vpe
+
+Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
+---
+ arch/mips/Kconfig                  |  6 ++++
+ arch/mips/include/asm/mipsmtregs.h |  5 ++++
+ arch/mips/include/asm/vpe.h        |  9 ++++++
+ arch/mips/kernel/vpe-mt.c          | 47 ++++++++++++++++++++++++++++++
+ arch/mips/kernel/vpe.c             | 35 ++++++++++++++++++++++
+ arch/mips/lantiq/prom.c            |  4 +++
+ 6 files changed, 106 insertions(+)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -2251,6 +2251,12 @@ config MIPS_VPE_LOADER
+ 	  Includes a loader for loading an elf relocatable object
+ 	  onto another VPE and running it.
+ 
++config IFX_VPE_EXT
++	bool "IFX APRP Extensions"
++	depends on MIPS_VPE_LOADER
++	help
++	  IFX included extensions in APRP
++
+ config MIPS_VPE_LOADER_MT
+ 	bool
+ 	default "y"
+--- a/arch/mips/include/asm/mipsmtregs.h
++++ b/arch/mips/include/asm/mipsmtregs.h
+@@ -31,6 +31,9 @@
+ #define read_c0_vpeconf1()		__read_32bit_c0_register($1, 3)
+ #define write_c0_vpeconf1(val)		__write_32bit_c0_register($1, 3, val)
+ 
++#define read_c0_vpeopt()		__read_32bit_c0_register($1, 7)
++#define write_c0_vpeopt(val)		__write_32bit_c0_register($1, 7, val)
++
+ #define read_c0_tcstatus()		__read_32bit_c0_register($2, 1)
+ #define write_c0_tcstatus(val)		__write_32bit_c0_register($2, 1, val)
+ 
+@@ -429,6 +432,8 @@ do {									\
+ #define write_vpe_c0_vpeconf0(val)	mttc0($1, 2, val)
+ #define read_vpe_c0_vpeconf1()		mftc0($1, 3)
+ #define write_vpe_c0_vpeconf1(val)	mttc0($1, 3, val)
++#define read_vpe_c0_vpeopt()		mftc0($1, 7)
++#define write_vpe_c0_vpeopt(val)	mttc0($1, 7, val)
+ #define read_vpe_c0_count()		mftc0($9, 0)
+ #define write_vpe_c0_count(val)		mttc0($9, 0, val)
+ #define read_vpe_c0_status()		mftc0($12, 0)
+--- a/arch/mips/include/asm/vpe.h
++++ b/arch/mips/include/asm/vpe.h
+@@ -119,4 +119,13 @@ void cleanup_tc(struct tc *tc);
+ 
+ int __init vpe_module_init(void);
+ void __exit vpe_module_exit(void);
++
++/* For the explanation of the APIs please refer the section "MT APRP Kernel
++ * Programming" in AR9 SW Architecture Specification
++ */
++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags);
++int32_t vpe1_sw_stop(uint32_t flags);
++uint32_t vpe1_get_load_addr(uint32_t flags);
++uint32_t vpe1_get_max_mem(uint32_t flags);
++
+ #endif /* _ASM_VPE_H */
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -383,6 +383,8 @@ int __init vpe_module_init(void)
+ 			}
+ 
+ 			v->ntcs = hw_tcs - aprp_cpu_index();
++			write_tc_c0_tcbind((read_tc_c0_tcbind() &
++						~TCBIND_CURVPE) | 1);
+ 
+ 			/* add the tc to the list of this vpe's tc's. */
+ 			list_add(&t->tc, &v->tc);
+@@ -486,3 +488,47 @@ void __exit vpe_module_exit(void)
+ 			release_vpe(v);
+ 	}
+ }
++
++#ifdef CONFIG_IFX_VPE_EXT
++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags)
++{
++	enum vpe_state state;
++	struct vpe *v = get_vpe(tclimit);
++	struct vpe_notifications *not;
++
++	if (tcmask || flags) {
++		pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n");
++		return -1;
++	}
++
++	state = xchg(&v->state, VPE_STATE_INUSE);
++	if (state != VPE_STATE_UNUSED) {
++		vpe_stop(v);
++
++		list_for_each_entry(not, &v->notify, list) {
++			not->stop(tclimit);
++		}
++	}
++
++	v->__start = (unsigned long)sw_start_addr;
++
++	if (!vpe_run(v)) {
++		pr_debug("VPE loader: VPE1 running successfully\n");
++		return 0;
++	}
++	return -1;
++}
++EXPORT_SYMBOL(vpe1_sw_start);
++
++int32_t vpe1_sw_stop(uint32_t flags)
++{
++	struct vpe *v = get_vpe(tclimit);
++
++	if (!vpe_free(v)) {
++		pr_debug("RP Stopped\n");
++		return 0;
++	} else
++		return -1;
++}
++EXPORT_SYMBOL(vpe1_sw_stop);
++#endif
+--- a/arch/mips/kernel/vpe.c
++++ b/arch/mips/kernel/vpe.c
+@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = {
+ 	.tc_list	= LIST_HEAD_INIT(vpecontrol.tc_list)
+ };
+ 
++#ifdef CONFIG_IFX_VPE_EXT
++unsigned int vpe1_load_addr;
++
++static int __init load_address(char *str)
++{
++	get_option(&str, &vpe1_load_addr);
++	return 1;
++}
++__setup("vpe1_load_addr=", load_address);
++
++static unsigned int vpe1_mem;
++static int __init vpe1mem(char *str)
++{
++	vpe1_mem = memparse(str, &str);
++	return 1;
++}
++__setup("vpe1_mem=", vpe1mem);
++
++uint32_t vpe1_get_load_addr(uint32_t flags)
++{
++	return vpe1_load_addr;
++}
++EXPORT_SYMBOL(vpe1_get_load_addr);
++
++uint32_t vpe1_get_max_mem(uint32_t flags)
++{
++	if (!vpe1_mem)
++		return P_SIZE;
++	else
++		return vpe1_mem;
++}
++EXPORT_SYMBOL(vpe1_get_max_mem);
++
++#endif
++
+ /* get the vpe associated with this minor */
+ struct vpe *get_vpe(int minor)
+ {
+--- a/arch/mips/lantiq/prom.c
++++ b/arch/mips/lantiq/prom.c
+@@ -36,10 +36,14 @@ extern const struct plat_smp_ops vsmp_sm
+ static struct plat_smp_ops lantiq_smp_ops;
+ #endif
+ 
++/* for Multithreading (APRP), vpe.c will use it */
++unsigned long cp0_memsize;
++
+ const char *get_system_type(void)
+ {
+ 	return soc_info.sys_type;
+ }
++EXPORT_SYMBOL(ltq_soc_type);
+ 
+ int ltq_soc_type(void)
+ {

target/linux/lantiq/patches-6.12/154-lantiq-pci-bar11mask-fix.patch

@@ -0,0 +1,32 @@
+From 3c92a781de062064e36b867c0ab22f9aba48f3d3 Mon Sep 17 00:00:00 2001
+From: Eddi De Pieri <eddi@depieri.net>
+Date: Tue, 8 Nov 2016 17:38:00 +0100
+Subject: [PATCH] lantiq: pci: bar11mask fix
+
+Signed-off-by: Eddi De Pieri <eddi@depieri.net>
+---
+ arch/mips/pci/pci-lantiq.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -59,6 +59,8 @@
+ #define ltq_pci_cfg_w32(x, y)	ltq_w32((x), ltq_pci_mapped_cfg + (y))
+ #define ltq_pci_cfg_r32(x)	ltq_r32(ltq_pci_mapped_cfg + (x))
+ 
++extern u32 max_low_pfn;
++
+ __iomem void *ltq_pci_mapped_cfg;
+ static __iomem void *ltq_pci_membase;
+ 
+@@ -84,8 +86,8 @@ static inline u32 ltq_calc_bar11mask(voi
+ 	u32 mem, bar11mask;
+ 
+ 	/* BAR11MASK value depends on available memory on system. */
+-	mem = get_num_physpages() * PAGE_SIZE;
+-	bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
++	mem = max_low_pfn << PAGE_SHIFT;
++	bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8;
+ 
+ 	return bar11mask;
+ }

target/linux/lantiq/patches-6.12/155-lantiq-VPE-nosmp.patch

@@ -0,0 +1,24 @@
+From 07ce9e9bc4dcd5ac4728e587901112eef95bbe7b Mon Sep 17 00:00:00 2001
+From: Stefan Koch <stefan.koch10@gmail.com>
+Date: Mon, 13 Mar 2017 23:42:00 +0100
+Subject: [PATCH] lantiq: vpe nosmp
+
+Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
+---
+ arch/mips/kernel/vpe-mt.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -130,7 +130,10 @@ int vpe_run(struct vpe *v)
+ 	 * kernels need to turn it on, even if that wasn't the pre-dvpe() state.
+ 	 */
+ #ifdef CONFIG_SMP
+-	evpe(vpeflags);
++	if (!setup_max_cpus) /* nosmp is set */
++		evpe(EVPE_ENABLE);
++	else
++		evpe(vpeflags);
+ #else
+ 	evpe(EVPE_ENABLE);
+ #endif

target/linux/lantiq/patches-6.12/160-owrt-lantiq-multiple-flash.patch

@@ -0,0 +1,224 @@
+From ebaae1cd68cd79c7eee67c9c5c0fa45809e84525 Mon Sep 17 00:00:00 2001
+From: Maikel Bloemendal <openwrt@maikelenyvonne.nl>
+Date: Fri, 14 Nov 2014 17:06:00 +0000
+Subject: [PATCH] owrt: lantiq: multiple flash
+
+Concatenate multiple flash chips for lantiq-flash.
+
+Signed-off-by: Maikel Bloemendal <openwrt@maikelenyvonne.nl>
+---
+ drivers/mtd/maps/lantiq-flash.c | 168 +++++++++++++++++++++-----------
+ 1 file changed, 109 insertions(+), 59 deletions(-)
+
+--- a/drivers/mtd/maps/lantiq-flash.c
++++ b/drivers/mtd/maps/lantiq-flash.c
+@@ -17,6 +17,7 @@
+ #include <linux/mtd/cfi.h>
+ #include <linux/platform_device.h>
+ #include <linux/mtd/physmap.h>
++#include <linux/mtd/concat.h>
+ #include <linux/of.h>
+ 
+ #include <lantiq_soc.h>
+@@ -36,13 +37,16 @@ enum {
+ 	LTQ_NOR_NORMAL
+ };
+ 
++#define MAX_RESOURCES		4
++
+ struct ltq_mtd {
+-	struct resource *res;
+-	struct mtd_info *mtd;
+-	struct map_info *map;
++	struct mtd_info *mtd[MAX_RESOURCES];
++	struct mtd_info	*cmtd;
++	struct map_info map[MAX_RESOURCES];
+ };
+ 
+ static const char ltq_map_name[] = "ltq_nor";
++static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL };
+ 
+ static map_word
+ ltq_read16(struct map_info *map, unsigned long adr)
+@@ -105,12 +109,41 @@ ltq_copy_to(struct map_info *map, unsign
+ 	spin_unlock_irqrestore(&ebu_lock, flags);
+ }
+ 
++static void ltq_mtd_remove(struct platform_device *pdev)
++{
++	struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);
++	int i;
++
++	if (ltq_mtd == NULL)
++		return;
++
++	if (ltq_mtd->cmtd) {
++		mtd_device_unregister(ltq_mtd->cmtd);
++		if (ltq_mtd->cmtd != ltq_mtd->mtd[0])
++			mtd_concat_destroy(ltq_mtd->cmtd);
++	}
++
++	for (i = 0; i < MAX_RESOURCES; i++) {
++		if (ltq_mtd->mtd[i] != NULL)
++			map_destroy(ltq_mtd->mtd[i]);
++	}
++
++	kfree(ltq_mtd);
++}
++
+ static int
+ ltq_mtd_probe(struct platform_device *pdev)
+ {
+ 	struct ltq_mtd *ltq_mtd;
+ 	struct cfi_private *cfi;
+-	int err;
++	int err = 0;
++	int i;
++	int devices_found = 0;
++
++	static const char *rom_probe_types[] = {
++		"cfi_probe", "jedec_probe", NULL
++	};
++	const char **type;
+ 
+ 	ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);
+ 	if (!ltq_mtd)
+@@ -118,68 +151,89 @@ ltq_mtd_probe(struct platform_device *pd
+ 
+ 	platform_set_drvdata(pdev, ltq_mtd);
+ 
+-	ltq_mtd->map->virt = devm_platform_get_and_ioremap_resource(pdev, 0, &ltq_mtd->res);
+-	if (IS_ERR(ltq_mtd->map->virt))
+-		return PTR_ERR(ltq_mtd->map->virt);
+-
+-	ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info),
+-				    GFP_KERNEL);
+-	if (!ltq_mtd->map)
+-		return -ENOMEM;
+-
+-	if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
+-		ltq_mtd->map->phys = NO_XIP;
+-	else
+-		ltq_mtd->map->phys = ltq_mtd->res->start;
+-	ltq_mtd->res->start;
+-	ltq_mtd->map->size = resource_size(ltq_mtd->res);
+-
+-	ltq_mtd->map->name = ltq_map_name;
+-	ltq_mtd->map->bankwidth = 2;
+-	ltq_mtd->map->read = ltq_read16;
+-	ltq_mtd->map->write = ltq_write16;
+-	ltq_mtd->map->copy_from = ltq_copy_from;
+-	ltq_mtd->map->copy_to = ltq_copy_to;
+-
+-	ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING;
+-	ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map);
+-	ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL;
+-
+-	if (!ltq_mtd->mtd) {
+-		dev_err(&pdev->dev, "probing failed\n");
+-		return -ENXIO;
++	for (i = 0; i < pdev->num_resources; i++) {
++		printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n",
++		       (unsigned long long)resource_size(&pdev->resource[i]),
++		       (unsigned long long)pdev->resource[i].start);
++	
++		if (!devm_request_mem_region(&pdev->dev,
++			pdev->resource[i].start,
++			resource_size(&pdev->resource[i]),
++			dev_name(&pdev->dev))) {
++			dev_err(&pdev->dev, "Could not reserve memory region\n");
++			return -ENOMEM;
++		}
++
++		ltq_mtd->map[i].name = ltq_map_name;
++		ltq_mtd->map[i].bankwidth = 2;
++		ltq_mtd->map[i].read = ltq_read16;
++		ltq_mtd->map[i].write = ltq_write16;
++		ltq_mtd->map[i].copy_from = ltq_copy_from;
++		ltq_mtd->map[i].copy_to = ltq_copy_to;
++
++		if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
++			ltq_mtd->map[i].phys = NO_XIP;
++		else
++			ltq_mtd->map[i].phys = pdev->resource[i].start;
++		ltq_mtd->map[i].size = resource_size(&pdev->resource[i]);
++		ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start,
++						 ltq_mtd->map[i].size);
++		if (IS_ERR(ltq_mtd->map[i].virt))
++			return PTR_ERR(ltq_mtd->map[i].virt);
++
++		if (ltq_mtd->map[i].virt == NULL) {
++			dev_err(&pdev->dev, "Failed to ioremap flash region\n");
++			err = PTR_ERR(ltq_mtd->map[i].virt);
++			goto err_out;
++		}
++
++		ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING;
++		for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++)
++			ltq_mtd->mtd[i] = do_map_probe(*type, &ltq_mtd->map[i]);
++		ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL;
++
++		if (!ltq_mtd->mtd[i]) {
++			dev_err(&pdev->dev, "probing failed\n");
++			return -ENXIO;
++		} else {
++			devices_found++;
++		}
++
++		ltq_mtd->mtd[i]->owner = THIS_MODULE;
++		ltq_mtd->mtd[i]->dev.parent = &pdev->dev;
++
++		cfi = ltq_mtd->map[i].fldrv_priv;
++		cfi->addr_unlock1 ^= 1;
++		cfi->addr_unlock2 ^= 1;
+ 	}
+ 
+-	ltq_mtd->mtd->dev.parent = &pdev->dev;
+-	mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node);
++	if (devices_found == 1) {
++		ltq_mtd->cmtd = ltq_mtd->mtd[0];
++	} else if (devices_found > 1) {
++		/*
++		 * We detected multiple devices. Concatenate them together.
++		 */
++		ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev));
++		if (ltq_mtd->cmtd == NULL)
++			err = -ENXIO;
++	}
+ 
+-	cfi = ltq_mtd->map->fldrv_priv;
+-	cfi->addr_unlock1 ^= 1;
+-	cfi->addr_unlock2 ^= 1;
++	ltq_mtd->cmtd->dev.parent = &pdev->dev;
++	mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node);
+ 
+-	err = mtd_device_register(ltq_mtd->mtd, NULL, 0);
++	err = mtd_device_register(ltq_mtd->cmtd, NULL, 0);
+ 	if (err) {
+ 		dev_err(&pdev->dev, "failed to add partitions\n");
+-		goto err_destroy;
++		goto err_out;
+ 	}
+ 
+ 	return 0;
+ 
+-err_destroy:
+-	map_destroy(ltq_mtd->mtd);
++err_out:
++	ltq_mtd_remove(pdev);
+ 	return err;
+ }
+ 
+-static void ltq_mtd_remove(struct platform_device *pdev)
+-{
+-	struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);
+-
+-	if (ltq_mtd && ltq_mtd->mtd) {
+-		mtd_device_unregister(ltq_mtd->mtd);
+-		map_destroy(ltq_mtd->mtd);
+-	}
+-}
+-
+ static const struct of_device_id ltq_mtd_match[] = {
+ 	{ .compatible = "lantiq,nor" },
+ 	{},

target/linux/lantiq/patches-6.12/200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch

@@ -0,0 +1,111 @@
+From 2b873c59fd313aee57864f96d64a228f2ea7c208 Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Mon, 13 May 2024 10:42:24 +0200
+Subject: [PATCH] MIPS: lantiq: xway: vmmc: use platform_get_irq to get irqs
+ from dts
+
+Let's fetch the irqs from the dts here and expose them to the voice
+driver like it is done for the cp1 base memory.
+
+ToDo:
+Maybe it is possible to drop this driver completely and merge this
+handling to the voice driver.
+
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ arch/mips/lantiq/xway/vmmc.c | 53 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+--- a/arch/mips/lantiq/xway/vmmc.c
++++ b/arch/mips/lantiq/xway/vmmc.c
+@@ -15,6 +15,10 @@
+ 
+ static unsigned int *cp1_base;
+ 
++static int ad0_irq;
++static int ad1_irq;
++static int vc_irq[4];
++
+ unsigned int *ltq_get_cp1_base(void)
+ {
+ 	if (!cp1_base)
+@@ -24,6 +28,33 @@ unsigned int *ltq_get_cp1_base(void)
+ }
+ EXPORT_SYMBOL(ltq_get_cp1_base);
+ 
++unsigned int ltq_get_mps_ad0_irq(void)
++{
++	if (!ad0_irq)
++		panic("no ad0 irq was set\n");
++
++	return ad0_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad0_irq);
++
++unsigned int ltq_get_mps_ad1_irq(void)
++{
++	if (!ad1_irq)
++		panic("no ad1 irq was set\n");
++
++	return ad1_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad1_irq);
++
++unsigned int ltq_get_mps_vc_irq(int idx)
++{
++	if (!vc_irq[idx])
++		panic("no vc%d irq was set\n", idx);
++
++	return vc_irq[idx];
++}
++EXPORT_SYMBOL(ltq_get_mps_vc_irq);
++
+ static int vmmc_probe(struct platform_device *pdev)
+ {
+ #define CP1_SIZE       (1 << 20)
+@@ -31,11 +62,33 @@ static int vmmc_probe(struct platform_de
+ 	int gpio_count;
+ 	dma_addr_t dma;
+ 	int error;
++	int i;
+ 
+ 	cp1_base =
+ 		(void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE,
+ 						    &dma, GFP_KERNEL));
+ 
++	ad0_irq = platform_get_irq(pdev, 4);
++	if (ad0_irq < 0) {
++		dev_err(&pdev->dev, "failed to get MPS AD0 irq: %d\n", ad0_irq);
++		return ad0_irq;
++	}
++
++	ad1_irq = platform_get_irq(pdev, 5);
++	if (ad1_irq < 0) {
++		dev_err(&pdev->dev, "failed to get MPS AD1 irq: %d\n", ad1_irq);
++		return ad1_irq;
++	}
++
++	for (i = 0; i < 4; i++) {
++	vc_irq[i] = platform_get_irq(pdev, i);
++		if (vc_irq[i] < 0) {
++			dev_err(&pdev->dev, "failed to get MPS VC%d irq: %d\n",
++				i, vc_irq[i]);
++			return vc_irq[i];
++		}
++	}
++
+ 	gpio_count = gpiod_count(&pdev->dev, NULL);
+ 	while (gpio_count > 0) {
+ 		gpio = devm_gpiod_get_index(&pdev->dev,
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -104,6 +104,9 @@ const u8* ltq_get_eth_mac(void);
+ 
+ /* VMMC */
+ extern unsigned int *ltq_get_cp1_base(void);
++extern unsigned int ltq_get_mps_ad0_irq(void);
++extern unsigned int ltq_get_mps_ad1_irq(void);
++extern unsigned int ltq_get_mps_vc_irq(int idx);
+ 
+ #endif /* CONFIG_SOC_TYPE_XWAY */
+ #endif /* _LTQ_XWAY_H__ */

target/linux/lantiq/patches-6.12/300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch

@@ -0,0 +1,21 @@
+From 5e93c85ac3e5626d1aa7e7f9c0a008b2a4224f04 Mon Sep 17 00:00:00 2001
+From: Matti Laakso <malaakso@elisanet.fi>
+Date: Sat, 14 Feb 2015 20:48:00 +0000
+Subject: [PATCH] MTD: cfi_cmdset_0001: disable buffered writes
+
+Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
+---
+ drivers/mtd/chips/cfi_cmdset_0001.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0001.c
++++ b/drivers/mtd/chips/cfi_cmdset_0001.c
+@@ -40,7 +40,7 @@
+ /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */
+ 
+ // debugging, turns off buffer write mode if set to 1
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+ 
+ /* Intel chips */
+ #define I82802AB	0x00ad

target/linux/lantiq/patches-6.12/301-xrx200-add-gphy-clk-src-device-tree-binding.patch

@@ -0,0 +1,40 @@
+From 5502ef9d40ab20b2ac683660d1565a7c4968bcc8 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <openwrt@kresin.me>
+Date: Mon, 2 May 2016 18:50:00 +0000
+Subject: [PATCH] xrx200: add gphy clk src device tree binding
+
+Signed-off-by: Mathias Kresin <openwrt@kresin.me>
+---
+ arch/mips/lantiq/xway/sysctrl.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/mips/lantiq/xway/sysctrl.c
++++ b/arch/mips/lantiq/xway/sysctrl.c
+@@ -439,6 +439,20 @@ static void clkdev_add_clkout(void)
+ 	}
+ }
+ 
++static void set_phy_clock_source(struct device_node *np_cgu)
++{
++	u32 phy_clk_src, ifcc;
++
++	if (!np_cgu)
++		return;
++
++	if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
++		return;
++
++	ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
++	ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
++}
++
+ /* bring up all register ranges that we need for basic system control */
+ void __init ltq_soc_init(void)
+ {
+@@ -608,4 +622,6 @@ void __init ltq_soc_init(void)
+ 		clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
+ 	}
+ 	usb_set_clock();
++
++	set_phy_clock_source(np_cgu);
+ }

target/linux/lantiq/patches-6.12/302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch

@@ -0,0 +1,62 @@
+From 118fe2c88b35482711adeee0d8758bddfe958701 Mon Sep 17 00:00:00 2001
+From: Aleksander Jan Bajkowski <olek2@wp.pl>
+Date: Sat, 6 May 2023 14:32:00 +0200
+Subject: [PATCH] mtd: cfi_cmdset_0001: Disable write buffer functions if
+ FORCE_WORD_WRITE is 1
+
+Some write buffer functions are not used when FORCE_WORD_WRITE is set to 1.
+So the compile warning messages are output if FORCE_WORD_WRITE is 1. To
+resolve this disable the write buffer functions if FORCE_WORD_WRITE is 1.
+
+This is similar fix to: 557c759036fc3976a5358cef23e65a263853b93f.
+
+Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
+---
+ drivers/mtd/chips/cfi_cmdset_0001.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0001.c
++++ b/drivers/mtd/chips/cfi_cmdset_0001.c
+@@ -62,8 +62,10 @@
+ 
+ static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#if !FORCE_WORD_WRITE
+ static int cfi_intelext_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+ static int cfi_intelext_writev(struct mtd_info *, const struct kvec *, unsigned long, loff_t, size_t *);
++#endif
+ static int cfi_intelext_erase_varsize(struct mtd_info *, struct erase_info *);
+ static void cfi_intelext_sync (struct mtd_info *);
+ static int cfi_intelext_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+@@ -305,6 +307,7 @@ static void fixup_use_point(struct mtd_i
+ 	}
+ }
+ 
++#if !FORCE_WORD_WRITE
+ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ {
+ 	struct map_info *map = mtd->priv;
+@@ -315,6 +318,7 @@ static void fixup_use_write_buffers(stru
+ 		mtd->_writev = cfi_intelext_writev;
+ 	}
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ /*
+  * Some chips power-up with all sectors locked by default.
+@@ -1720,6 +1724,7 @@ static int cfi_intelext_write_words (str
+ }
+ 
+ 
++#if !FORCE_WORD_WRITE
+ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+ 				    unsigned long adr, const struct kvec **pvec,
+ 				    unsigned long *pvec_seek, int len)
+@@ -1948,6 +1953,7 @@ static int cfi_intelext_write_buffers (s
+ 
+ 	return cfi_intelext_writev(mtd, &vec, 1, to, retlen);
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip,
+ 				      unsigned long adr, int len, void *thunk)

target/linux/lantiq/patches-6.12/400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch

@@ -0,0 +1,38 @@
+From 416f25a948d11ef15733f2e31658d31b5cc7bef6 Mon Sep 17 00:00:00 2001
+From: Thomas Nixon <tom@tomn.co.uk>
+Date: Sun, 26 Mar 2023 11:08:49 +0100
+Subject: [PATCH] mtd: rawnand: xway: don't yield while holding spinlock
+
+The nand driver normally while waiting for the device to become ready;
+this is normally fine, but xway_nand holds the ebu_lock spinlock, and
+this can cause lockups if other threads which use ebu_lock are
+interleaved. Fix this by waiting instead of polling.
+
+This mainly showed up as crashes in ath9k_pci_owl_loader (see
+https://github.com/openwrt/openwrt/issues/9829 ), but turning on
+spinlock debugging shows this happening in other places too.
+
+This doesn't seem to measurably impact boot time.
+
+Signed-off-by: Thomas Nixon <tom@tomn.co.uk>
+---
+ drivers/mtd/nand/raw/xway_nand.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/raw/xway_nand.c
++++ b/drivers/mtd/nand/raw/xway_nand.c
+@@ -175,7 +175,13 @@ static void xway_cmd_ctrl(struct nand_ch
+ 
+ static int xway_dev_ready(struct nand_chip *chip)
+ {
+-	return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
++	/*
++	 * wait until ready, as otherwise the driver will yield in nand_wait or
++	 * nand_wait_ready, which is a bad idea when we're holding ebu_lock
++	 */
++	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
++		cpu_relax();
++	return 1;
+ }
+ 
+ static unsigned char xway_read_byte(struct nand_chip *chip)

target/linux/lantiq/patches-6.12/701-NET-lantiq-etop-of-mido.patch

@@ -0,0 +1,47 @@
+From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
+From: Johann Neuhauser <johann@it-neuhauser.de>
+Date: Thu, 17 May 2018 19:12:35 +0200
+Subject: [PATCH] net: lantiq_etop: of mdio
+
+Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
+---
+ drivers/net/ethernet/lantiq_etop.c |  555 +++++++++++++++++++++++++-----------
+ 1 file changed, 389 insertions(+), 166 deletions(-)
+
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -31,6 +31,7 @@
+ #include <linux/of_net.h>
+ #include <linux/of_irq.h>
+ #include <linux/of_platform.h>
++#include <linux/of_mdio.h>
+ 
+ #include <asm/checksum.h>
+ 
+@@ -561,7 +562,8 @@ static int
+ ltq_etop_mdio_init(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int err;
++	struct device_node *mdio_np = NULL;
++	int err, ret;
+ 
+ 	priv->mii_bus = mdiobus_alloc();
+ 	if (!priv->mii_bus) {
+@@ -581,7 +583,15 @@ ltq_etop_mdio_init(struct net_device *de
+ 	priv->mii_bus->name = "ltq_mii";
+ 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+ 		 priv->pdev->name, priv->pdev->id);
+-	if (mdiobus_register(priv->mii_bus)) {
++
++	mdio_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
++
++	if (mdio_np)
++		ret = of_mdiobus_register(priv->mii_bus, mdio_np);
++	else
++		ret = mdiobus_register(priv->mii_bus);
++
++	if (ret) {
+ 		err = -ENXIO;
+ 		goto err_out_free_mdiobus;
+ 	}

target/linux/lantiq/patches-6.6/0008-MIPS-lantiq-backport-old-timer-code.patch

@@ -186,7 +186,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  obj-y += vmmc.o
 --- /dev/null
 +++ b/arch/mips/lantiq/xway/timer.c
-@@ -0,0 +1,888 @@
+@@ -0,0 +1,889 @@
 +#ifndef CONFIG_SOC_AMAZON_SE
 +
 +#include <linux/kernel.h>
@@ -200,6 +200,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#include <linux/unistd.h>
 +#include <linux/errno.h>
 +#include <linux/interrupt.h>
++#include <linux/platform_device.h>
 +#include <linux/sched.h>
 +#include <linux/sched/signal.h>
 +
@@ -346,7 +347,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +};
 +
 +
-+unsigned int ltq_get_fpi_bus_clock(int fpi) {
++static unsigned int ltq_get_fpi_bus_clock(int fpi) {
 +	struct clk *clk = clk_get_fpi();
 +	return clk_get_rate(clk);
 +}
@@ -1049,7 +1050,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	},
 +};
 +
-+int __init lq_gptu_init(void)
++static int __init lq_gptu_init(void)
 +{
 +	int ret = platform_driver_register(&gptu_driver);
 +
@@ -1058,7 +1059,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	return ret;
 +}
 +
-+void __exit lq_gptu_exit(void)
++static void __exit lq_gptu_exit(void)
 +{
 +	unsigned int i;
 +

target/linux/lantiq/patches-6.6/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch

@@ -70,7 +70,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +}
 +
 +static int ath5k_eep_load;
-+int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
++static int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
 +{
 +	struct device_node *np = pdev->dev.of_node, *mtd_np = NULL;
 +	int mac_offset;
@@ -174,7 +174,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +subsys_initcall(of_ath5k_eeprom_init);
 --- /dev/null
 +++ b/arch/mips/lantiq/xway/eth_mac.c
-@@ -0,0 +1,25 @@
+@@ -0,0 +1,26 @@
 +/*
 + *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
 + *
@@ -183,6 +183,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 + *  by the Free Software Foundation.
 + */
 +
++#include <lantiq_soc.h>
 +#include <linux/init.h>
 +#include <linux/if_ether.h>
 +

target/linux/lantiq/patches-6.6/0102-01-MIPS-lantiq-xway-mark-ltq_ar9_sys_hz-as-static.patch

@@ -0,0 +1,27 @@
+From 3004522ddba0a23941222d2044badd4436ce776f Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 18:08:35 +0800
+Subject: [PATCH 01/16] MIPS: lantiq: xway: mark ltq_ar9_sys_hz() as static
+
+Fix the following missing-prototypes warning:
+
+arch/mips/lantiq/xway/clk.c:77:15: error: no previous prototype for 'ltq_ar9_sys_hz' [-Werror=missing-prototypes]
+   77 | unsigned long ltq_ar9_sys_hz(void)
+      |               ^~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/xway/clk.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/lantiq/xway/clk.c
++++ b/arch/mips/lantiq/xway/clk.c
+@@ -74,7 +74,7 @@ unsigned long ltq_danube_pp32_hz(void)
+ 	return clk;
+ }
+ 
+-unsigned long ltq_ar9_sys_hz(void)
++static unsigned long ltq_ar9_sys_hz(void)
+ {
+ 	if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
+ 		return CLOCK_393M;

target/linux/lantiq/patches-6.6/0102-02-MIPS-lantiq-xway-mark-dma_init-as-static.patch

@@ -0,0 +1,27 @@
+From ada0c7fd1b2e6daaf64bf8649cc58afaceed1a3d Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 18:11:41 +0800
+Subject: [PATCH 02/16] MIPS: lantiq: xway: mark dma_init() as static
+
+Fix the following missing-prototypes build warning:
+
+arch/mips/lantiq/xway/dma.c:293:1: error: no previous prototype for 'dma_init' [-Werror=missing-prototypes]
+  293 | dma_init(void)
+      | ^~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/xway/dma.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/lantiq/xway/dma.c
++++ b/arch/mips/lantiq/xway/dma.c
+@@ -289,7 +289,7 @@ static struct platform_driver dma_driver
+ 	},
+ };
+ 
+-int __init
++static int __init
+ dma_init(void)
+ {
+ 	return platform_driver_register(&dma_driver);

target/linux/lantiq/patches-6.6/0102-03-MIPS-lantiq-xway-mark-dcdc_init-as-static.patch

@@ -0,0 +1,27 @@
+From d27f9ab0f53886152b717e44eeca0217519ad323 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 18:18:26 +0800
+Subject: [PATCH 03/16] MIPS: lantiq: xway: mark dcdc_init() as static
+
+Fix the following missing-prototypes build warning:
+
+arch/mips/lantiq/xway/dcdc.c:49:12: error: no previous prototype for 'dcdc_init' [-Werror=missing-prototypes]
+   49 | int __init dcdc_init(void)
+      |            ^~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/xway/dcdc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/lantiq/xway/dcdc.c
++++ b/arch/mips/lantiq/xway/dcdc.c
+@@ -46,7 +46,7 @@ static struct platform_driver dcdc_drive
+ 	},
+ };
+ 
+-int __init dcdc_init(void)
++static int __init dcdc_init(void)
+ {
+ 	int ret = platform_driver_register(&dcdc_driver);
+ 

target/linux/lantiq/patches-6.6/0102-04-MIPS-lantiq-irq-fix-misc-missing-prototypes-warnings.patch

@@ -0,0 +1,42 @@
+From 9729233d2ef318cdb6954c8b5cb032d7d0f03473 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 19:53:12 +0800
+Subject: [PATCH 04/16] MIPS: lantiq: irq: fix misc missing-prototypes warnings
+
+Fix the following build warnings:
+
+arch/mips/lantiq/irq.c:340:12: error: no previous prototype for 'icu_of_init' [-Werror=missing-prototypes]
+  340 | int __init icu_of_init(struct device_node *node, struct device_node *parent)
+      |            ^~~~~~~~~~~
+arch/mips/lantiq/irq.c:418:5: error: no previous prototype for 'get_c0_perfcount_int' [-Werror=missing-prototypes]
+  418 | int get_c0_perfcount_int(void)
+      |     ^~~~~~~~~~~~~~~~~~~~
+arch/mips/lantiq/irq.c:424:14: error: no previous prototype for 'get_c0_compare_int' [-Werror=missing-prototypes]
+  424 | unsigned int get_c0_compare_int(void)
+      |              ^~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/irq.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/lantiq/irq.c
++++ b/arch/mips/lantiq/irq.c
+@@ -17,6 +17,7 @@
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/irq_cpu.h>
++#include <asm/time.h>
+ 
+ #include <lantiq_soc.h>
+ #include <irq.h>
+@@ -337,7 +338,8 @@ static const struct irq_domain_ops irq_d
+ 	.map = icu_map,
+ };
+ 
+-int __init icu_of_init(struct device_node *node, struct device_node *parent)
++static int __init
++icu_of_init(struct device_node *node, struct device_node *parent)
+ {
+ 	struct device_node *eiu_node;
+ 	struct resource res;

target/linux/lantiq/patches-6.6/0102-05-MIPS-lantiq-xway-add-prototype-for-ltq_get_cp1_base.patch

@@ -0,0 +1,29 @@
+From 5759385fb2b1fafcb0073add3cf4dc7a918ac7f2 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 20:19:15 +0800
+Subject: [PATCH 05/16] MIPS: lantiq: xway: add prototype for
+ ltq_get_cp1_base()
+
+ltq_get_cp1_base() is an exported function, we must define
+its prototype on header file. Fix warning:
+
+arch/mips/lantiq/xway/vmmc.c:22:15: error: no previous prototype for 'ltq_get_cp1_base' [-Werror=missing-prototypes]
+   22 | unsigned int *ltq_get_cp1_base(void)
+      |               ^~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -102,5 +102,8 @@ extern void ltq_pmu_disable(unsigned int
+ /* allow the ethernet driver to load a flash mapped mac addr */
+ const u8* ltq_get_eth_mac(void);
+ 
++/* VMMC */
++extern unsigned int *ltq_get_cp1_base(void);
++
+ #endif /* CONFIG_SOC_TYPE_XWAY */
+ #endif /* _LTQ_XWAY_H__ */

target/linux/lantiq/patches-6.6/0102-06-MIPS-pci-lantiq-marks-pcibios_init-as-static.patch

@@ -0,0 +1,27 @@
+From 156977363d9ed39d80062044704932d8c11d1611 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 20:31:33 +0800
+Subject: [PATCH 06/16] MIPS: pci: lantiq: marks pcibios_init() as static
+
+Fix the following missing-prototypes build warning:
+
+arch/mips/pci/pci-lantiq.c:239:12: error: no previous prototype for 'pcibios_init' [-Werror=missing-prototypes]
+  239 | int __init pcibios_init(void)
+      |            ^~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/pci/pci-lantiq.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -234,7 +234,7 @@ static struct platform_driver ltq_pci_dr
+ 	},
+ };
+ 
+-int __init pcibios_init(void)
++static int __init pcibios_init(void)
+ {
+ 	int ret = platform_driver_register(&ltq_pci_driver);
+ 	if (ret)

target/linux/lantiq/patches-6.6/0102-07-MIPS-lantiq-falcon-fix-misc-missing-prototypes-warni.patch

@@ -0,0 +1,39 @@
+From 6900665e987f7c76dff709d63be4df4171c02ab2 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:15:36 +0800
+Subject: [PATCH 07/16] MIPS: lantiq: falcon: fix misc missing-prototypes
+ warnings
+
+Fix the following build warnings:
+
+arch/mips/lantiq/falcon/prom.c:39:13: error: no previous prototype for 'ltq_soc_nmi_setup' [-Werror=missing-prototypes]
+   39 | void __init ltq_soc_nmi_setup(void)
+      |             ^~~~~~~~~~~~~~~~~
+arch/mips/lantiq/falcon/prom.c:46:13: error: no previous prototype for 'ltq_soc_ejtag_setup' [-Werror=missing-prototypes]
+   46 | void __init ltq_soc_ejtag_setup(void)
+      |             ^~~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/falcon/prom.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/lantiq/falcon/prom.c
++++ b/arch/mips/lantiq/falcon/prom.c
+@@ -36,14 +36,14 @@
+ #define BOOT_NVEC	(BOOT_REG_BASE | 0x04)
+ #define BOOT_EVEC	(BOOT_REG_BASE | 0x08)
+ 
+-void __init ltq_soc_nmi_setup(void)
++static void __init ltq_soc_nmi_setup(void)
+ {
+ 	extern void (*nmi_handler)(void);
+ 
+ 	ltq_w32((unsigned long)&nmi_handler, (void *)BOOT_NVEC);
+ }
+ 
+-void __init ltq_soc_ejtag_setup(void)
++static void __init ltq_soc_ejtag_setup(void)
+ {
+ 	extern void (*ejtag_debug_handler)(void);
+ 

target/linux/lantiq/patches-6.6/0102-08-MIPS-lantiq-falcon-sysctrl-remove-unused-falcon_trig.patch

@@ -0,0 +1,31 @@
+From b145074ce653a895201bf8a2ba70719a107ad580 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:15:36 +0800
+Subject: [PATCH 08/16] MIPS: lantiq: falcon: sysctrl: remove unused
+ falcon_trigger_hrst()
+
+This is a defined but unused function. Fix warning:
+
+arch/mips/lantiq/falcon/sysctrl.c:75:6: error: no previous prototype for 'falcon_trigger_hrst' [-Werror=missing-prototypes]
+   75 | void falcon_trigger_hrst(int level)
+      |      ^~~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/falcon/sysctrl.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+--- a/arch/mips/lantiq/falcon/sysctrl.c
++++ b/arch/mips/lantiq/falcon/sysctrl.c
+@@ -72,11 +72,6 @@
+ static void __iomem *sysctl_membase[3], *status_membase;
+ void __iomem *ltq_sys1_membase, *ltq_ebu_membase;
+ 
+-void falcon_trigger_hrst(int level)
+-{
+-	sysctl_w32(SYSCTL_SYS1, level & 1, SYS1_HRSTOUTC);
+-}
+-
+ static inline void sysctl_wait(struct clk *clk,
+ 		unsigned int test, unsigned int reg)
+ {

target/linux/lantiq/patches-6.6/0102-09-MIPS-lantiq-falcon-sysctrl-add-missing-header-prom.h.patch

@@ -0,0 +1,27 @@
+From cc7803436c2419009aaf702d96fc1d717ca52279 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:15:36 +0800
+Subject: [PATCH 09/16] MIPS: lantiq: falcon: sysctrl: add missing header
+ prom.h
+
+"prom.h" includes the prototype of ltq_soc_init(). Fix warning:
+
+arch/mips/lantiq/falcon/sysctrl.c:185:13: error: no previous prototype for 'ltq_soc_init' [-Werror=missing-prototypes]
+  185 | void __init ltq_soc_init(void)
+      |             ^~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/falcon/sysctrl.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/lantiq/falcon/sysctrl.c
++++ b/arch/mips/lantiq/falcon/sysctrl.c
+@@ -14,6 +14,7 @@
+ #include <lantiq_soc.h>
+ 
+ #include "../clk.h"
++#include "../prom.h"
+ 
+ /* infrastructure control register */
+ #define SYS1_INFRAC		0x00bc

target/linux/lantiq/patches-6.6/0102-10-MIPS-lantiq-falcon-sysctrl-fix-request-memory-check-.patch

@@ -0,0 +1,64 @@
+From ccdf5d58c4f3330a83393641d4e4334994fc91af Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:53:58 +0800
+Subject: [PATCH 10/16] MIPS: lantiq: falcon: sysctrl: fix request memory check
+ logic
+
+request_mem_region() will return NULL instead of error code
+when the memory request fails. Therefore, we should check if
+the return value is non-zero instead of less than zero. In
+this way, this patch also fixes the build warnings:
+
+arch/mips/lantiq/falcon/sysctrl.c:214:50: error: ordered comparison of pointer with integer zero [-Werror=extra]
+  214 |                                 res_status.name) < 0) ||
+      |                                                  ^
+arch/mips/lantiq/falcon/sysctrl.c:216:47: error: ordered comparison of pointer with integer zero [-Werror=extra]
+  216 |                                 res_ebu.name) < 0) ||
+      |                                               ^
+arch/mips/lantiq/falcon/sysctrl.c:219:50: error: ordered comparison of pointer with integer zero [-Werror=extra]
+  219 |                                 res_sys[0].name) < 0) ||
+      |                                                  ^
+arch/mips/lantiq/falcon/sysctrl.c:222:50: error: ordered comparison of pointer with integer zero [-Werror=extra]
+  222 |                                 res_sys[1].name) < 0) ||
+      |                                                  ^
+arch/mips/lantiq/falcon/sysctrl.c:225:50: error: ordered comparison of pointer with integer zero [-Werror=extra]
+  225 |                                 res_sys[2].name) < 0))
+      |
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/falcon/sysctrl.c | 23 ++++++++++-------------
+ 1 file changed, 10 insertions(+), 13 deletions(-)
+
+--- a/arch/mips/lantiq/falcon/sysctrl.c
++++ b/arch/mips/lantiq/falcon/sysctrl.c
+@@ -210,19 +210,16 @@ void __init ltq_soc_init(void)
+ 	of_node_put(np_syseth);
+ 	of_node_put(np_sysgpe);
+ 
+-	if ((request_mem_region(res_status.start, resource_size(&res_status),
+-				res_status.name) < 0) ||
+-		(request_mem_region(res_ebu.start, resource_size(&res_ebu),
+-				res_ebu.name) < 0) ||
+-		(request_mem_region(res_sys[0].start,
+-				resource_size(&res_sys[0]),
+-				res_sys[0].name) < 0) ||
+-		(request_mem_region(res_sys[1].start,
+-				resource_size(&res_sys[1]),
+-				res_sys[1].name) < 0) ||
+-		(request_mem_region(res_sys[2].start,
+-				resource_size(&res_sys[2]),
+-				res_sys[2].name) < 0))
++	if ((!request_mem_region(res_status.start, resource_size(&res_status),
++				 res_status.name)) ||
++	    (!request_mem_region(res_ebu.start, resource_size(&res_ebu),
++				 res_ebu.name)) ||
++	    (!request_mem_region(res_sys[0].start, resource_size(&res_sys[0]),
++				 res_sys[0].name)) ||
++	    (!request_mem_region(res_sys[1].start, resource_size(&res_sys[1]),
++				 res_sys[1].name)) ||
++	    (!request_mem_region(res_sys[2].start, resource_size(&res_sys[2]),
++				 res_sys[2].name)))
+ 		pr_err("Failed to request core resources");
+ 
+ 	status_membase = ioremap(res_status.start,

target/linux/lantiq/patches-6.6/0102-11-MIPS-lantiq-xway-gptu-mark-gptu_init-as-static.patch

@@ -0,0 +1,27 @@
+From 2caf57c67c6c3228b7a2ff1510e7671539ad31d3 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 22:29:34 +0800
+Subject: [PATCH 11/16] MIPS: lantiq: xway: gptu: mark gptu_init() as static
+
+Fix the following missing-prototypes warning:
+
+arch/mips/lantiq/xway/gptu.c:197:12: error: no previous prototype for 'gptu_init' [-Werror=missing-prototypes]
+  197 | int __init gptu_init(void)
+      |            ^~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/lantiq/xway/gptu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/lantiq/xway/gptu.c
++++ b/arch/mips/lantiq/xway/gptu.c
+@@ -194,7 +194,7 @@ static struct platform_driver dma_driver
+ 	},
+ };
+ 
+-int __init gptu_init(void)
++static int __init gptu_init(void)
+ {
+ 	int ret = platform_driver_register(&dma_driver);
+ 

target/linux/lantiq/patches-6.6/0102-12-MIPS-vpe-mt-mark-vpe_free-and-vpe_stop-as-static.patch

@@ -0,0 +1,52 @@
+From 6faade177216b41a8112e33c6e73377e78dd1f92 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 18:32:11 +0800
+Subject: [PATCH 12/16] MIPS: vpe-mt: mark vpe_free() and vpe_stop() as static
+
+These functions are only used in the current source file "vpe-mt.c".
+Do not export them and mark them as static to silence the missing
+prototypes warnings:
+
+arch/mips/kernel/vpe-mt.c:208:5: error: no previous prototype for 'vpe_stop' [-Werror=missing-prototypes]
+  208 | int vpe_stop(void *vpe)
+      |     ^~~~~~~~
+arch/mips/kernel/vpe-mt.c:229:5: error: no previous prototype for 'vpe_free' [-Werror=missing-prototypes]
+  229 | int vpe_free(void *vpe)
+      |     ^~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/kernel/vpe-mt.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -202,7 +202,7 @@ int vpe_start(void *vpe, unsigned long s
+ EXPORT_SYMBOL(vpe_start);
+ 
+ /* halt it for now */
+-int vpe_stop(void *vpe)
++static int vpe_stop(void *vpe)
+ {
+ 	struct vpe *v = vpe;
+ 	struct tc *t;
+@@ -220,10 +220,9 @@ int vpe_stop(void *vpe)
+ 
+ 	return 0;
+ }
+-EXPORT_SYMBOL(vpe_stop);
+ 
+ /* I've done with it thank you */
+-int vpe_free(void *vpe)
++static int vpe_free(void *vpe)
+ {
+ 	struct vpe *v = vpe;
+ 	struct tc *t;
+@@ -255,7 +254,6 @@ int vpe_free(void *vpe)
+ 
+ 	return 0;
+ }
+-EXPORT_SYMBOL(vpe_free);
+ 
+ static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
+ 			  const char *buf, size_t len)

target/linux/lantiq/patches-6.6/0102-13-MIPS-vpe-mt-drop-unused-functions-vpe_alloc-and-vpe_.patch

@@ -0,0 +1,59 @@
+From e6fab4c05f655b834587bc06f0274f69cdc43171 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 18:32:11 +0800
+Subject: [PATCH 13/16] MIPS: vpe-mt: drop unused functions vpe_alloc() and
+ vpe_start()
+
+These two functions are defined but unused. Removing them to silence
+the missing prototypes warnings:
+
+arch/mips/kernel/vpe-mt.c:180:7: error: no previous prototype for 'vpe_alloc' [-Werror=missing-prototypes]
+  180 | void *vpe_alloc(void)
+      |       ^~~~~~~~~
+arch/mips/kernel/vpe-mt.c:198:5: error: no previous prototype for 'vpe_start' [-Werror=missing-prototypes]
+  198 | int vpe_start(void *vpe, unsigned long start)
+      |     ^~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/kernel/vpe-mt.c | 29 -----------------------------
+ 1 file changed, 29 deletions(-)
+
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -172,35 +172,6 @@ void cleanup_tc(struct tc *tc)
+ 	local_irq_restore(flags);
+ }
+ 
+-/* module wrapper entry points */
+-/* give me a vpe */
+-void *vpe_alloc(void)
+-{
+-	int i;
+-	struct vpe *v;
+-
+-	/* find a vpe */
+-	for (i = 1; i < MAX_VPES; i++) {
+-		v = get_vpe(i);
+-		if (v != NULL) {
+-			v->state = VPE_STATE_INUSE;
+-			return v;
+-		}
+-	}
+-	return NULL;
+-}
+-EXPORT_SYMBOL(vpe_alloc);
+-
+-/* start running from here */
+-int vpe_start(void *vpe, unsigned long start)
+-{
+-	struct vpe *v = vpe;
+-
+-	v->__start = start;
+-	return vpe_run(v);
+-}
+-EXPORT_SYMBOL(vpe_start);
+-
+ /* halt it for now */
+ static int vpe_stop(void *vpe)
+ {

target/linux/lantiq/patches-6.6/0102-14-pinctrl-xway-mark-xway_pinconf_group_set-as-static.patch

@@ -0,0 +1,34 @@
+From 7d8878668dfe011f33b92a0f9aa3e0d46c1b77ca Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 8 May 2025 20:36:56 +0800
+Subject: [PATCH 14/16] pinctrl: xway: mark xway_pinconf_group_set() as static
+
+Fix the following missing-prototypes build warning:
+
+drivers/pinctrl/pinctrl-xway.c:1231:5: error: no previous prototype for 'xway_pinconf_group_set' [-Werror=missing-prototypes]
+ 1231 | int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
+      |     ^~~~~~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/pinctrl/pinctrl-xway.c | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-xway.c
++++ b/drivers/pinctrl/pinctrl-xway.c
+@@ -1228,10 +1228,11 @@ static int xway_pinconf_set(struct pinct
+ 	return 0;
+ }
+ 
+-int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
+-			unsigned selector,
+-			unsigned long *configs,
+-			unsigned num_configs)
++static int
++xway_pinconf_group_set(struct pinctrl_dev *pctldev,
++		       unsigned selector,
++		       unsigned long *configs,
++		       unsigned num_configs)
+ {
+ 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
+ 	int i, ret = 0;

target/linux/lantiq/patches-6.6/0102-15-pinctrl-falcon-mark-pinctrl_falcon_init-as-static.patch

@@ -0,0 +1,27 @@
+From 9dec40b4f01a2aa92311b077ef45ecaa335d45a2 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:16:49 +0800
+Subject: [PATCH 15/16] pinctrl: falcon: mark pinctrl_falcon_init() as static
+
+Fix the following missing-prototypes build warning:
+
+drivers/pinctrl/pinctrl-falcon.c:508:12: error: no previous prototype for 'pinctrl_falcon_init' [-Werror=missing-prototypes]
+  508 | int __init pinctrl_falcon_init(void)
+      |            ^~~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/pinctrl/pinctrl-falcon.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/pinctrl-falcon.c
++++ b/drivers/pinctrl/pinctrl-falcon.c
+@@ -505,7 +505,7 @@ static struct platform_driver pinctrl_fa
+ 	},
+ };
+ 
+-int __init pinctrl_falcon_init(void)
++static int __init pinctrl_falcon_init(void)
+ {
+ 	return platform_driver_register(&pinctrl_falcon_driver);
+ }

target/linux/lantiq/patches-6.6/0102-16-spi-falcon-mark-falcon_sflash_xfer-as-static.patch

@@ -0,0 +1,30 @@
+From 28b20e002412bcadd4de74235faff275efb9e2cd Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Fri, 9 May 2025 20:21:02 +0800
+Subject: [PATCH 16/16] spi: falcon: mark falcon_sflash_xfer() as static
+
+Fix the following missing-prototypes build warning:
+
+drivers/spi/spi-falcon.c:97:5: error: no previous prototype for 'falcon_sflash_xfer' [-Werror=missing-prototypes]
+   97 | int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
+      |     ^~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/spi/spi-falcon.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/spi/spi-falcon.c
++++ b/drivers/spi/spi-falcon.c
+@@ -94,8 +94,9 @@ struct falcon_sflash {
+ 	struct spi_controller *host;
+ };
+ 
+-int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
+-		unsigned long flags)
++static int
++falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
++		   unsigned long flags)
+ {
+ 	struct device *dev = &spi->dev;
+ 	struct falcon_sflash *priv = spi_controller_get_devdata(spi->controller);

target/linux/lantiq/patches-6.6/0151-lantiq-ifxmips_pcie-use-of.patch

@@ -23,7 +23,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  obj-$(CONFIG_SOC_TX4938)	+= pci-tx4938.o
 --- a/arch/mips/pci/ifxmips_pcie.c
 +++ b/arch/mips/pci/ifxmips_pcie.c
-@@ -16,8 +16,15 @@
+@@ -16,8 +16,16 @@
  #include <asm/paccess.h>
  #include <linux/pci.h>
  #include <linux/pci_regs.h>
@@ -35,11 +35,12 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
 +#include <linux/of_gpio.h>
 +#include <linux/of_platform.h>
++#include <linux/platform_device.h>
 +
  #include "ifxmips_pcie.h"
  #include "ifxmips_pcie_reg.h"
  
-@@ -25,11 +32,6 @@
+@@ -25,11 +33,6 @@
  #define IFX_PCIE_ERROR_INT
  #define IFX_PCIE_IO_32BIT
  
@@ -51,7 +52,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  #define MS(_v, _f)  (((_v) & (_f)) >> _f##_S)
  #define SM(_v, _f)  (((_v) << _f##_S) & (_f))
  #define IFX_REG_SET_BIT(_f, _r) \
-@@ -40,30 +42,30 @@
+@@ -40,30 +43,30 @@
  static DEFINE_SPINLOCK(ifx_pcie_lock);
  
  u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
@@ -87,7 +88,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
              },
          },
      },
-@@ -82,6 +84,22 @@ void ifx_pcie_debug(const char *fmt, ...
+@@ -82,6 +85,22 @@ void ifx_pcie_debug(const char *fmt, ...
  	printk("%s", buf);
  }
  
@@ -110,7 +111,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
  static inline int pcie_ltssm_enable(int pcie_port)
  {
-@@ -857,7 +875,8 @@ pcie_rc_core_int_init(int pcie_port)
+@@ -857,7 +876,8 @@ pcie_rc_core_int_init(int pcie_port)
  	ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0,
  		pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]);
  	if (ret)
@@ -120,7 +121,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
  	return ret;
  }
-@@ -988,10 +1007,26 @@ int  ifx_pcie_bios_plat_dev_init(struct
+@@ -988,10 +1008,26 @@ int  ifx_pcie_bios_plat_dev_init(struct
  static int
  pcie_rc_initialize(int pcie_port)
  {
@@ -149,7 +150,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
  	pcie_ep_gpio_rst_init(pcie_port);
  
-@@ -1000,26 +1035,21 @@ pcie_rc_initialize(int pcie_port)
+@@ -1000,26 +1036,21 @@ pcie_rc_initialize(int pcie_port)
  	* reset PCIe PHY will solve this issue 
  	*/
  	for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
@@ -186,7 +187,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
  		/* Enable PCIe PHY and Clock */
  		pcie_core_pmu_setup(pcie_port);
-@@ -1035,6 +1065,10 @@ pcie_rc_initialize(int pcie_port)
+@@ -1035,6 +1066,10 @@ pcie_rc_initialize(int pcie_port)
  		/* Once link is up, break out */
  		if (pcie_app_loigc_setup(pcie_port) == 0)
  			break;
@@ -197,7 +198,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  	}
  	if (i >= IFX_PCIE_PHY_LOOP_CNT) {
  		printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
-@@ -1045,17 +1079,73 @@ pcie_rc_initialize(int pcie_port)
+@@ -1045,17 +1080,73 @@ pcie_rc_initialize(int pcie_port)
  	return 0;
  }
  
@@ -273,7 +274,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
      for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
  	if (pcie_rc_initialize(pcie_port) == 0) {
  	    IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", 
-@@ -1066,7 +1156,19 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1066,7 +1157,19 @@ static int __init ifx_pcie_bios_init(voi
                  IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__);
                  return -ENOMEM;
              }
@@ -293,7 +294,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
              register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
              /* XXX, clear error status */
-@@ -1083,6 +1185,29 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1083,6 +1186,29 @@ static int __init ifx_pcie_bios_init(voi
  
      return 0;
  }
@@ -312,7 +313,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
 +        },
 +};
 +
-+int __init ifx_pcie_bios_init(void)
++static int __init ifx_pcie_bios_init(void)
 +{
 +        int ret = platform_driver_register(&ltq_pci_driver);
 +        if (ret)

target/linux/lantiq/patches-6.6/0152-lantiq-VPE.patch

@@ -67,7 +67,7 @@ Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
  #endif /* _ASM_VPE_H */
 --- a/arch/mips/kernel/vpe-mt.c
 +++ b/arch/mips/kernel/vpe-mt.c
-@@ -414,6 +414,8 @@ int __init vpe_module_init(void)
+@@ -383,6 +383,8 @@ int __init vpe_module_init(void)
  			}
  
  			v->ntcs = hw_tcs - aprp_cpu_index();
@@ -76,7 +76,7 @@ Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
  
  			/* add the tc to the list of this vpe's tc's. */
  			list_add(&t->tc, &v->tc);
-@@ -517,3 +519,47 @@ void __exit vpe_module_exit(void)
+@@ -486,3 +488,47 @@ void __exit vpe_module_exit(void)
  			release_vpe(v);
  	}
  }

target/linux/lantiq/patches-6.6/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch

@@ -97,3 +97,15 @@ Signed-off-by: Martin Schiller <ms@dev.tdt.de>
  	gpio_count = gpiod_count(&pdev->dev, NULL);
  	while (gpio_count > 0) {
  		gpio = devm_gpiod_get_index(&pdev->dev,
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -104,6 +104,9 @@ const u8* ltq_get_eth_mac(void);
+ 
+ /* VMMC */
+ extern unsigned int *ltq_get_cp1_base(void);
++extern unsigned int ltq_get_mps_ad0_irq(void);
++extern unsigned int ltq_get_mps_ad1_irq(void);
++extern unsigned int ltq_get_mps_vc_irq(int idx);
+ 
+ #endif /* CONFIG_SOC_TYPE_XWAY */
+ #endif /* _LTQ_XWAY_H__ */

target/linux/lantiq/xrx200/config-6.12

@@ -0,0 +1,92 @@
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GRO_CELLS=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_IFX_VPE_EXT=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INTEL_XWAY_PHY=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_XRX200=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MIPS_MT=y
+# CONFIG_MIPS_MT_FPAFF is not set
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MIPS_VPE_APSP_API=y
+CONFIG_MIPS_VPE_APSP_API_MT=y
+CONFIG_MIPS_VPE_LOADER=y
+CONFIG_MIPS_VPE_LOADER_MT=y
+CONFIG_MIPS_VPE_LOADER_TOM=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_NAND_XWAY=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=2
+CONFIG_PADATA=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_LANTIQ=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_PHYLINK=y
+CONFIG_PHY_LANTIQ_VRX200_PCIE=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_SENSORS_LTQ_CPUTEMP=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y

target/linux/lantiq/xrx200/config-6.6

@@ -52,7 +52,6 @@ CONFIG_NET_FLOW_LIMIT=y
 CONFIG_NLS=y
 CONFIG_NR_CPUS=2
 CONFIG_PADATA=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
 CONFIG_PCI=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCIE_LANTIQ=y

target/linux/lantiq/xrx200_legacy/config-6.12

@@ -0,0 +1,77 @@
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GRO_CELLS=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_IFX_VPE_EXT=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INTEL_XWAY_PHY=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_XRX200=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MIPS_MT=y
+# CONFIG_MIPS_MT_FPAFF is not set
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MIPS_VPE_APSP_API=y
+CONFIG_MIPS_VPE_APSP_API_MT=y
+CONFIG_MIPS_VPE_LOADER=y
+CONFIG_MIPS_VPE_LOADER_MT=y
+CONFIG_MIPS_VPE_LOADER_TOM=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=2
+CONFIG_PADATA=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_LANTIQ=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_PHYLINK=y
+CONFIG_PHY_LANTIQ_VRX200_PCIE=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_SENSORS_LTQ_CPUTEMP=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y

target/linux/lantiq/xrx200_legacy/config-6.6

@@ -39,7 +39,6 @@ CONFIG_NET_FLOW_LIMIT=y
 CONFIG_NLS=y
 CONFIG_NR_CPUS=2
 CONFIG_PADATA=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
 CONFIG_PCI=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCIE_LANTIQ=y

target/linux/lantiq/xway/config-6.12

@@ -0,0 +1,83 @@
+CONFIG_ADM6996_PHY=y
+CONFIG_AR8216_PHY=y
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_HW_RANDOM=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MIPS_MT=y
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_XWAY=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_FLOW_LIMIT=y
+# CONFIG_NET_SWITCHDEV is not set
+CONFIG_NLS=y
+CONFIG_NR_CPUS=2
+CONFIG_PADATA=y
+CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_PSB6970_PHY=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTL8306_PHY=y
+CONFIG_RTL8366RB_PHY=y
+CONFIG_RTL8366_SMI=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_SMT=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SWCONFIG=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y

target/linux/lantiq/xway_legacy/config-6.12

@@ -0,0 +1,31 @@
+CONFIG_ADM6996_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_GENERIC_ALLOCATOR=y
+# CONFIG_GPIO_CDEV is not set
+# CONFIG_GPIO_SYSFS is not set
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_NET_SWITCHDEV is not set
+CONFIG_NLS=y
+CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RTL8306_PHY=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SWCONFIG=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y

target/linux/mediatek/Makefile

@@ -8,8 +8,7 @@ BOARDNAME:=MediaTek ARM
 SUBTARGETS:=filogic mt7622 mt7623 mt7629
 FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb
 
-KERNEL_PATCHVER:=6.6
-KERNEL_TESTING_PATCHVER:=6.12
+KERNEL_PATCHVER:=6.12
 
 include $(INCLUDE_DIR)/target.mk
 DEFAULT_PACKAGES += \

target/linux/mediatek/dts/mt7981b-gatonetworks-gdsp-gps.dtso

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "gatonetworks,gdsp", "mediatek,mt7981";
+
+	fragment@0 {
+		target = <&uart1>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};

target/linux/mediatek/dts/mt7981b-gatonetworks-gdsp-sd-boot.dtso

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "gatonetworks,gdsp", "mediatek,mt7981";
+
+	fragment@1 {
+		target = <&mmc0>;
+		__overlay__ {
+			card@0 {
+				compatible = "mmc-card";
+				reg = <0>;
+
+				partitions {
+					compatible = "gpt-partitions";
+
+					sdmmc_fit: block-partition-fit {
+						partname = "FIT";
+					};
+				};
+			};
+		};
+	};
+};
+
+&{/chosen} {
+	rootdisk = <&sdmmc_fit>;
+};

target/linux/mediatek/dts/mt7981b-gatonetworks-gdsp-sd.dtso

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "gatonetworks,gdsp", "mediatek,mt7981";
+
+	fragment@0 {
+		target = <&mmc0>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};

target/linux/mediatek/dts/mt7981b-gatonetworks-gdsp.dts

@@ -127,6 +127,23 @@
 	status = "okay";
 };
 
+&mmc0 {
+	status = "disabled";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_pins_default>;
+	pinctrl-1 = <&mmc0_pins_uhs>;
+	bus-width = <4>;
+	max-frequency = <50000000>;
+	cap-sd-highspeed;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	no-mmc;
+	no-sdio;
+};
+
 &eth {
 	status = "okay";
 
@@ -334,6 +351,56 @@
 		};
 	};
 
+	mmc0_pins_default: mmc0-pins-default {
+		mux {
+			function = "flash";
+			groups = "emmc_45";
+		};
+		conf-cmd-dat {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
+				"SPI0_CS",  "SPI0_HOLD", "SPI0_WP",
+				"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
+			input-enable;
+			drive-strength = <MTK_DRIVE_4mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+		conf-clk {
+			pins = "SPI1_CS";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+		conf-rst {
+			pins = "PWM0";
+			drive-strength = <MTK_DRIVE_4mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+	};
+
+	mmc0_pins_uhs: mmc0-pins-uhs {
+		mux {
+			function = "flash";
+			groups = "emmc_45";
+		};
+		conf-cmd-dat {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
+				"SPI0_CS",  "SPI0_HOLD", "SPI0_WP",
+				"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
+			input-enable;
+			drive-strength = <MTK_DRIVE_4mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+		conf-clk {
+			pins = "SPI1_CS";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+		conf-rst {
+			pins = "PWM0";
+			drive-strength = <MTK_DRIVE_4mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+	};
+
 	uart2_pins: uart2-pins {
 		mux {
 			function = "uart";
@@ -368,7 +435,7 @@
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
+	status = "disabled";
 };
 
 &uart2 {

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso

@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-		};
-	};
-
-	fragment@1 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <600>;
-			reset-post-delay-us = <20000>;
-
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso

@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&sw_p5>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <600>;
-			reset-post-delay-us = <20000>;
-
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso

@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&chosen>;
-		rootdisk-spim-nand = <&ubi_rootdisk>;
-	};
-
-	fragment@1 {
-		target = <&spi0>;
-		__overlay__ {
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			spi_nand: spi_nand@1 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "spi-nand";
-				reg = <1>;
-				spi-max-frequency = <10000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					factory: partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0200000>;
-					};
-
-					partition@380000 {
-						label = "FIP";
-						reg = <0x380000 0x0200000>;
-					};
-
-					partition@580000 {
-						label = "ubi";
-						reg = <0x580000 0x4000000>;
-						compatible = "linux,ubi";
-
-						volumes {
-							ubi_rootdisk: ubi-volume-fit {
-								volname = "fit";
-							};
-						};
-					};
-				};
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&wifi>;
-		__overlay__ {
-			mediatek,mtd-eeprom = <&factory 0x0>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts

@@ -1,189 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7981b.dtsi"
-
-/ {
-	model = "MediaTek MT7981 RFB";
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen: chosen {
-		stdout-path = "serial0:115200n8";
-		bootargs-append = " root=/dev/fit0 rootwait";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x20000000>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
-		};
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "gmii";
-		phy-handle = <&int_gbe_phy>;
-	};
-};
-
-&mdio_bus {
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		interrupt-parent = <&pio>;
-		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
-		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&pio {
-	spi0_flash_pins: spi0-pins {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-		conf-pu {
-			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
-			drive-strength = <MTK_DRIVE_8mA>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
-		};
-		conf-pd {
-			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
-			drive-strength = <MTK_DRIVE_8mA>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
-		};
-	};
-
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_flash_pins>;
-	cs-gpios = <0>, <0>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "disabled";
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan1";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan2";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan3";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan4";
-		};
-
-		sw_p5: port@5 {
-			reg = <5>;
-			label = "lan5";
-			status = "disabled";
-		};
-
-		port@6 {
-			reg = <6>;
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&xhci {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981b.dtsi

@@ -1,822 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (c) 2020 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <dt-bindings/reset/mt7986-resets.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mux/mux.h>
-
-/ {
-	compatible = "mediatek,mt7981";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			compatible = "arm,cortex-a53";
-			reg = <0x0>;
-			device_type = "cpu";
-			enable-method = "psci";
-		};
-
-		cpu@1 {
-			compatible = "arm,cortex-a53";
-			reg = <0x1>;
-			device_type = "cpu";
-			enable-method = "psci";
-		};
-	};
-
-	ice: ice_debug {
-		compatible = "mediatek,mt7981-ice_debug", "mediatek,mt2701-ice_debug";
-		clocks = <&infracfg CLK_INFRA_DBG_CK>;
-		clock-names = "ice_dbg";
-	};
-
-	clk40m: oscillator-40m {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		clock-output-names = "clkxtal";
-		#clock-cells = <0>;
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		/* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
-		cooling-levels = <0 63 95 127 159 191 223 255>;
-		#cooling-cells = <2>;
-		status = "disabled";
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reserved-memory {
-		ranges;
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		/* 64 KiB reserved for ramoops/pstore */
-		ramoops@42ff0000 {
-			compatible = "ramoops";
-			reg = <0 0x42ff0000 0 0x10000>;
-			record-size = <0x1000>;
-		};
-
-		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x30000>;
-			no-map;
-		};
-
-		wmcpu_emi: wmcpu-reserved@47c80000 {
-			reg = <0 0x47c80000 0 0x100000>;
-			no-map;
-		};
-
-		wo_emi0: wo-emi@47d80000 {
-			reg = <0 0x47d80000 0 0x40000>;
-			no-map;
-		};
-
-		wo_data: wo-data@47dc0000 {
-			reg = <0 0x47dc0000 0 0x240000>;
-			no-map;
-		};
-	};
-
-	soc {
-		compatible = "simple-bus";
-		ranges;
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		gic: interrupt-controller@c000000 {
-			compatible = "arm,gic-v3";
-			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-			      <0 0x0c080000 0 0x200000>; /* GICR */
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-		};
-
-		consys: consys@10000000 {
-			compatible = "mediatek,mt7981-consys";
-			reg = <0 0x10000000 0 0x8600000>;
-			memory-region = <&wmcpu_emi>;
-		};
-
-		infracfg: clock-controller@10001000 {
-			compatible = "mediatek,mt7981-infracfg", "syscon";
-			reg = <0 0x10001000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		wed_pcie: wed_pcie@10003000 {
-			compatible = "mediatek,wed_pcie";
-			reg = <0 0x10003000 0 0x10>;
-		};
-
-		topckgen: clock-controller@1001b000 {
-			compatible = "mediatek,mt7981-topckgen", "syscon";
-			reg = <0 0x1001b000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		watchdog: watchdog@1001c000 {
-			compatible = "mediatek,mt7986-wdt",
-				     "mediatek,mt6589-wdt";
-			reg = <0 0x1001c000 0 0x1000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			#reset-cells = <1>;
-			status = "disabled";
-		};
-
-		apmixedsys: clock-controller@1001e000 {
-			compatible = "mediatek,mt7981-apmixedsys", "syscon";
-			reg = <0 0x1001e000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7981-pwm";
-			reg = <0 0x10048000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_PWM_STA>,
-				 <&infracfg CLK_INFRA_PWM_HCK>,
-				 <&infracfg CLK_INFRA_PWM1_CK>,
-				 <&infracfg CLK_INFRA_PWM2_CK>,
-				 <&infracfg CLK_INFRA_PWM3_CK>;
-			clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
-			#pwm-cells = <2>;
-		};
-
-		sgmiisys0: syscon@10060000 {
-			compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
-			reg = <0 0x10060000 0 0x1000>;
-			mediatek,pnswap;
-			#clock-cells = <1>;
-		};
-
-		sgmiisys1: syscon@10070000 {
-			compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
-			reg = <0 0x10070000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		crypto: crypto@10320000 {
-			compatible = "inside-secure,safexcel-eip97";
-			reg = <0 0x10320000 0 0x40000>;
-			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "ring0", "ring1", "ring2", "ring3";
-			clocks = <&topckgen CLK_TOP_EIP97B>;
-			clock-names = "top_eip97_ck";
-			assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
-		};
-
-		uart0: serial@11002000 {
-			compatible = "mediatek,mt6577-uart";
-			reg = <0 0x11002000 0 0x400>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
-				 <&infracfg CLK_INFRA_UART0_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_UART0_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			pinctrl-0 = <&uart0_pins>;
-			pinctrl-names = "default";
-			status = "disabled";
-		};
-
-		uart1: serial@11003000 {
-			compatible = "mediatek,mt6577-uart";
-			reg = <0 0x11003000 0 0x400>;
-			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
-				 <&infracfg CLK_INFRA_UART1_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_UART1_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			status = "disabled";
-		};
-
-		uart2: serial@11004000 {
-			compatible = "mediatek,mt6577-uart";
-			reg = <0 0x11004000 0 0x400>;
-			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
-				 <&infracfg CLK_INFRA_UART2_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_UART2_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			status = "disabled";
-		};
-
-		snand: snfi@11005000 {
-			compatible = "mediatek,mt7986-snand";
-			reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
-			reg-names = "nfi", "ecc";
-			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
-				 <&infracfg CLK_INFRA_NFI1_CK>,
-				 <&infracfg CLK_INFRA_NFI_HCK_CK>;
-			clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
-			assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
-					  <&topckgen CLK_TOP_NFI1X_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
-						 <&topckgen CLK_TOP_CB_M_D8>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		i2c0: i2c@11007000 {
-			compatible = "mediatek,mt7981-i2c";
-			reg = <0 0x11007000 0 0x1000>,
-			      <0 0x10217080 0 0x80>;
-			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-				 <&infracfg CLK_INFRA_AP_DMA_CK>,
-				 <&infracfg CLK_INFRA_I2C_MCK_CK>,
-				 <&infracfg CLK_INFRA_I2C_PCK_CK>;
-			clock-names = "main", "dma", "arb", "pmic";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi2: spi@11009000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			reg = <0 0x11009000 0 0x100>;
-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_CB_M_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_SPI2_CK>,
-				 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi0: spi@1100a000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			reg = <0 0x1100a000 0 0x100>;
-			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_CB_M_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_SPI0_CK>,
-				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi1: spi@1100b000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			reg = <0 0x1100b000 0 0x100>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_CB_M_D2>,
-				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
-				 <&infracfg CLK_INFRA_SPI1_CK>,
-				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		thermal: thermal@1100c800 {
-			compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
-			reg = <0 0x1100c800 0 0x800>;
-			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_THERM_CK>,
-				 <&infracfg CLK_INFRA_ADC_26M_CK>;
-			clock-names = "therm", "auxadc";
-			nvmem-cells = <&thermal_calibration>;
-			nvmem-cell-names = "calibration-data";
-			#thermal-sensor-cells = <1>;
-			mediatek,auxadc = <&auxadc>;
-			mediatek,apmixedsys = <&apmixedsys>;
-		};
-
-		auxadc: adc@1100d000 {
-			compatible = "mediatek,mt7981-auxadc",
-				     "mediatek,mt7986-auxadc",
-				     "mediatek,mt7622-auxadc";
-			reg = <0 0x1100d000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
-				 <&infracfg CLK_INFRA_ADC_FRC_CK>;
-			clock-names = "main", "32k";
-			#io-channel-cells = <1>;
-		};
-
-		xhci: usb@11200000 {
-			compatible = "mediatek,mt7986-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x2e00>,
-			      <0 0x11203e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-				 <&infracfg CLK_INFRA_IUSB_CK>,
-				 <&infracfg CLK_INFRA_IUSB_133_CK>,
-				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
-				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-			clock-names = "sys_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck",
-				      "xhci_ck";
-			phys = <&u2port0 PHY_TYPE_USB2>,
-			       <&u3port0 PHY_TYPE_USB3>;
-			vusb33-supply = <&reg_3p3v>;
-			status = "disabled";
-		};
-
-		afe: audio-controller@11210000 {
-			compatible = "mediatek,mt79xx-audio";
-			reg = <0 0x11210000 0 0x9000>;
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
-				 <&infracfg CLK_INFRA_AUD_26M_CK>,
-				 <&infracfg CLK_INFRA_AUD_L_CK>,
-				 <&infracfg CLK_INFRA_AUD_AUD_CK>,
-				 <&infracfg CLK_INFRA_AUD_EG2_CK>,
-				 <&topckgen CLK_TOP_AUD_SEL>;
-			clock-names = "aud_bus_ck",
-				      "aud_26m_ck",
-				      "aud_l_ck",
-				      "aud_aud_ck",
-				      "aud_eg2_ck",
-				      "aud_sel";
-			assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
-					  <&topckgen CLK_TOP_A1SYS_SEL>,
-					  <&topckgen CLK_TOP_AUD_L_SEL>,
-					  <&topckgen CLK_TOP_A_TUNER_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
-						 <&topckgen CLK_TOP_APLL2_D4>,
-						 <&topckgen CLK_TOP_CB_APLL2_196M>,
-						 <&topckgen CLK_TOP_APLL2_D4>;
-			status = "disabled";
-		};
-
-		mmc0: mmc@11230000 {
-			compatible = "mediatek,mt7986-mmc", "mediatek,mt7981-mmc";
-			reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
-			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_MSDC_CK>,
-				 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-				 <&infracfg CLK_INFRA_MSDC_66M_CK>,
-				 <&infracfg CLK_INFRA_MSDC_133M_CK>;
-			assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
-					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
-						 <&topckgen CLK_TOP_CB_NET2_D2>;
-			clock-names = "source", "hclk", "axi_cg", "ahb_cg";
-			status = "disabled";
-		};
-
-		pcie: pcie@11280000 {
-			compatible = "mediatek,mt7981-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11280000 0 0x4000>;
-			reg-names = "pcie-mac";
-			ranges = <0x82000000 0 0x20000000
-				  0x0 0x20000000 0 0x10000000>;
-			device_type = "pci";
-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
-				 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-				 <&infracfg CLK_INFRA_IPCIER_CK>,
-				 <&infracfg CLK_INFRA_IPCIEB_CK>;
-			phys = <&u3port0 PHY_TYPE_PCIE>;
-			phy-names = "pcie-phy";
-			interrupt-map-mask = <0 0 0 7>;
-			interrupt-map = <0 0 0 1 &pcie_intc 0>,
-					<0 0 0 2 &pcie_intc 1>,
-					<0 0 0 3 &pcie_intc 2>,
-					<0 0 0 4 &pcie_intc 3>;
-			#interrupt-cells = <1>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc: interrupt-controller {
-				interrupt-controller;
-				#interrupt-cells = <1>;
-				#address-cells = <0>;
-			};
-		};
-
-		pio: pinctrl@11d00000 {
-			compatible = "mediatek,mt7981-pinctrl";
-			reg = <0 0x11d00000 0 0x1000>,
-			      <0 0x11c00000 0 0x1000>,
-			      <0 0x11c10000 0 0x1000>,
-			      <0 0x11d20000 0 0x1000>,
-			      <0 0x11e00000 0 0x1000>,
-			      <0 0x11e20000 0 0x1000>,
-			      <0 0x11f00000 0 0x1000>,
-			      <0 0x11f10000 0 0x1000>,
-			      <0 0x1000b000 0 0x1000>;
-			reg-names = "gpio", "iocfg_rt", "iocfg_rm",
-				    "iocfg_rb", "iocfg_lb", "iocfg_bl",
-				    "iocfg_tm", "iocfg_tl", "eint";
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pio 0 0 56>;
-			interrupt-controller;
-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&gic>;
-			#interrupt-cells = <2>;
-
-			mdio_pins: mdc-mdio-pins {
-				mux {
-					function = "eth";
-					groups = "smi_mdc_mdio";
-				};
-			};
-
-			uart0_pins: uart0-pins {
-				mux {
-					function = "uart";
-					groups = "uart0";
-				};
-			};
-
-			wifi_dbdc_pins: wifi-dbdc-pins {
-				mux {
-					function = "eth";
-					groups = "wf0_mode1";
-				};
-
-				conf {
-					pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
-					       "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
-					       "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
-					       "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
-					       "WF_CBA_RESETB", "WF_DIG_RESETB";
-					drive-strength = <4>;
-				};
-			};
-
-			gbe_led0_pins: gbe-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe_led0";
-				};
-			};
-
-			gbe_led1_pins: gbe-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe_led1";
-				};
-			};
-		};
-
-		topmisc: topmisc@11d10000 {
-			compatible = "mediatek,mt7981-topmisc", "syscon";
-			reg = <0 0x11d10000 0 0x10000>;
-			#clock-cells = <1>;
-		};
-
-		usb_phy: usb-phy@11e10000 {
-			compatible = "mediatek,mt7981",
-				     "mediatek,generic-tphy-v2";
-			ranges = <0 0 0x11e10000 0x1700>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			status = "disabled";
-
-			u2port0: usb-phy@0 {
-				reg = <0x0 0x700>;
-				clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			u3port0: usb-phy@700 {
-				reg = <0x700 0x900>;
-				clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-				mediatek,syscon-type = <&topmisc 0x218 0>;
-				status = "okay";
-			};
-		};
-
-		efuse: efuse@11f20000 {
-			compatible = "mediatek,mt7981-efuse",
-				     "mediatek,efuse";
-			reg = <0 0x11f20000 0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			status = "okay";
-
-			thermal_calibration: thermal-calib@274 {
-				reg = <0x274 0xc>;
-			};
-
-			phy_calibration: phy-calib@8dc {
-				reg = <0x8dc 0x10>;
-			};
-
-			comb_rx_imp_p0: usb3-rx-imp@8c8 {
-				reg = <0x8c8 1>;
-				bits = <0 5>;
-			};
-
-			comb_tx_imp_p0: usb3-tx-imp@8c8 {
-				reg = <0x8c8 2>;
-				bits = <5 5>;
-			};
-
-			comb_intr_p0: usb3-intr@8c9 {
-				reg = <0x8c9 1>;
-				bits = <2 6>;
-			};
-		};
-
-		ethsys: clock-controller@15000000 {
-			compatible = "mediatek,mt7981-ethsys",
-				     "syscon";
-			reg = <0 0x15000000 0 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-		};
-
-		wed: wed@15010000 {
-			compatible = "mediatek,mt7981-wed",
-				     "mediatek,mt7986-wed",
-				     "syscon";
-			reg = <0 0x15010000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wo_emi0>, <&wo_data>;
-			memory-region-names = "wo-emi", "wo-data";
-			mediatek,wo-ccif = <&wo_ccif0>;
-			mediatek,wo-ilm = <&wo_ilm0>;
-			mediatek,wo-dlm = <&wo_dlm0>;
-			mediatek,wo-cpuboot = <&wo_cpuboot>;
-		};
-
-		eth: ethernet@15100000 {
-			compatible = "mediatek,mt7981-eth";
-			reg = <0 0x15100000 0 0x80000>;
-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-					<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-					<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-					<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ethsys CLK_ETH_FE_EN>,
-				<&ethsys CLK_ETH_GP2_EN>,
-				<&ethsys CLK_ETH_GP1_EN>,
-				<&ethsys CLK_ETH_WOCPU0_EN>,
-				<&sgmiisys0 CLK_SGM0_TX_EN>,
-				<&sgmiisys0 CLK_SGM0_RX_EN>,
-				<&sgmiisys0 CLK_SGM0_CK0_EN>,
-				<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
-				<&sgmiisys1 CLK_SGM1_TX_EN>,
-				<&sgmiisys1 CLK_SGM1_RX_EN>,
-				<&sgmiisys1 CLK_SGM1_CK1_EN>,
-				<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
-				<&topckgen CLK_TOP_SGM_REG>,
-				<&topckgen CLK_TOP_NETSYS_SEL>,
-				<&topckgen CLK_TOP_NETSYS_500M_SEL>;
-			clock-names = "fe", "gp2", "gp1", "wocpu0",
-						"sgmii_tx250m", "sgmii_rx250m",
-						"sgmii_cdr_ref", "sgmii_cdr_fb",
-						"sgmii2_tx250m", "sgmii2_rx250m",
-						"sgmii2_cdr_ref", "sgmii2_cdr_fb",
-						"sgmii_ck", "netsys0", "netsys1";
-			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-					  <&topckgen CLK_TOP_SGM_325M_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
-						 <&topckgen CLK_TOP_CB_SGM_325M>;
-			mediatek,ethsys = <&ethsys>;
-			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-			mediatek,infracfg = <&topmisc>;
-			mediatek,wed = <&wed>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-
-			mdio_bus: mdio-bus {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				int_gbe_phy: ethernet-phy@0 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <0>;
-					phy-mode = "gmii";
-					phy-is-integrated;
-					nvmem-cells = <&phy_calibration>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						int_gbe_phy_led0: int-gbe-phy-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						int_gbe_phy_led1: int-gbe-phy-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-			};
-		};
-
-		wdma: wdma@15104800 {
-			compatible = "mediatek,wed-wdma";
-			reg = <0 0x15104800 0 0x400>,
-			      <0 0x15104c00 0 0x400>;
-		};
-
-		wo_cpuboot: syscon@15194000 {
-			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
-			reg = <0 0x15194000 0 0x1000>;
-		};
-
-		ap2woccif: ap2woccif@151a5000 {
-			compatible = "mediatek,ap2woccif";
-			reg = <0 0x151a5000 0 0x1000>,
-			      <0 0x151ad000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		wo_ccif0: syscon@151a5000 {
-			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-			reg = <0 0x151a5000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		wo_ilm0: syscon@151e0000 {
-			compatible = "mediatek,mt7986-wo-ilm", "syscon";
-			reg = <0 0x151e0000 0 0x8000>;
-		};
-
-		wo_dlm0: syscon@151e8000 {
-			compatible = "mediatek,mt7986-wo-dlm", "syscon";
-			reg = <0 0x151e8000 0 0x2000>;
-		};
-
-		wifi: wifi@18000000 {
-			compatible = "mediatek,mt7981-wmac";
-			reg = <0 0x18000000 0 0x1000000>,
-			      <0 0x10003000 0 0x1000>,
-			      <0 0x11d10000 0 0x1000>;
-			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
-			reset-names = "consys";
-			pinctrl-0 = <&wifi_dbdc_pins>;
-			pinctrl-names = "dbdc";
-			clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
-				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
-			clock-names = "mcu", "ap2conn";
-			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wmcpu_emi>;
-			status = "disabled";
-		};
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&thermal 0>;
-
-			trips {
-				cpu_trip_active_highest: active-highest {
-					temperature = <70000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <60000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <50000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <45000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_lowest: active-lowest {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-
-			cooling-maps {
-				cpu-active-highest {
-					/* active: set fan to cooling level 7 */
-					cooling-device = <&fan 7 7>;
-					trip = <&cpu_trip_active_highest>;
-				};
-
-				cpu-active-high {
-					/* active: set fan to cooling level 5 */
-					cooling-device = <&fan 5 5>;
-					trip = <&cpu_trip_active_high>;
-				};
-
-				cpu-active-med {
-					/* active: set fan to cooling level 3 */
-					cooling-device = <&fan 3 3>;
-					trip = <&cpu_trip_active_med>;
-				};
-
-				cpu-active-low {
-					/* active: set fan to cooling level 2 */
-					cooling-device = <&fan 2 2>;
-					trip = <&cpu_trip_active_low>;
-				};
-
-				cpu-active-lowest {
-					/* active: set fan to cooling level 1 */
-					cooling-device = <&fan 1 1>;
-					trip = <&cpu_trip_active_lowest>;
-				};
-			};
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		clock-frequency = <13000000>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-
-	};
-
-	trng {
-		compatible = "mediatek,mt7981-rng";
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts

@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
-	compatible = "mediatek,mt7986a-rfb-snand";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi_nand: spi_nand@1 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <10000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			partition@0 {
-				label = "BL2";
-				reg = <0x00000 0x0100000>;
-				read-only;
-			};
-			partition@100000 {
-				label = "u-boot-env";
-				reg = <0x0100000 0x0080000>;
-			};
-			factory: partition@180000 {
-				label = "Factory";
-				reg = <0x180000 0x0200000>;
-			};
-			partition@380000 {
-				label = "FIP";
-				reg = <0x380000 0x0200000>;
-			};
-			partition@580000 {
-				label = "ubi";
-				reg = <0x580000 0x4000000>;
-			};
-		};
-	};
-};
-
-&wifi {
-	mediatek,mtd-eeprom = <&factory 0>;
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts

@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
-	compatible = "mediatek,mt7986a-rfb-snor";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi_nor: spi_nor@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <52000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@00000 {
-				label = "BL2";
-				reg = <0x00000 0x0040000>;
-			};
-			partition@40000 {
-				label = "u-boot-env";
-				reg = <0x40000 0x0010000>;
-			};
-			factory: partition@50000 {
-				label = "Factory";
-				reg = <0x50000 0x00B0000>;
-			};
-			partition@100000 {
-				label = "FIP";
-				reg = <0x100000 0x0080000>;
-			};
-			partition@180000 {
-				label = "firmware";
-				reg = <0x180000 0xE00000>;
-			};
-		};
-	};
-};
-
-&wifi {
-	mediatek,mtd-eeprom = <&factory 0>;
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi

@@ -1,389 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7986a.dtsi"
-
-/ {
-	model = "MediaTek MT7986a RFB";
-	compatible = "mediatek,mt7986a-rfb";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>;
-};
-
-&mdio {
-	phy5: phy@5 {
-		compatible = "ethernet-phy-id67c9.de0a";
-		reg = <5>;
-
-		reset-gpios = <&pio 6 1>;
-		reset-deassert-us = <20000>;
-	};
-
-	phy6: phy@6 {
-		compatible = "ethernet-phy-id67c9.de0a";
-		reg = <6>;
-	};
-
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		reset-gpios = <&pio 5 0>;
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&mmc0 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&mmc0_pins_default>;
-	pinctrl-1 = <&mmc0_pins_uhs>;
-	bus-width = <8>;
-	max-frequency = <200000000>;
-	cap-mmc-highspeed;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-	hs400-ds-delay = <0x14014>;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-	non-removable;
-	no-sd;
-	no-sdio;
-	status = "okay";
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_pins>;
-	status = "okay";
-};
-
-&pcie_phy {
-	status = "okay";
-};
-
-&pio {
-	mmc0_pins_default: mmc0-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-	};
-
-	mmc0_pins_uhs: mmc0-uhs-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-	};
-
-	pcie_pins: pcie-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
-		};
-	};
-
-	spic_pins_g2: spic-pins-29-to-32 {
-		mux {
-			function = "spi";
-			groups = "spi1_2";
-		};
-	};
-
-	spi_flash_pins: spi-flash-pins-33-to-38 {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-		conf-pu {
-			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
-			drive-strength = <8>;
-			mediatek,pull-up-adv = <0>;	/* bias-disable */
-		};
-		conf-pd {
-			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
-			drive-strength = <8>;
-			mediatek,pull-down-adv = <0>;	/* bias-disable */
-		};
-	};
-
-	uart1_pins: uart1-pins {
-		mux {
-			function = "uart";
-			groups = "uart1";
-		};
-	};
-
-	uart2_pins: uart2-pins {
-		mux {
-			function = "uart";
-			groups = "uart2";
-		};
-	};
-
-	wf_2g_5g_pins: wf_2g_5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf_dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_flash_pins>;
-	cs-gpios = <0>, <0>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "disabled";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic_pins_g2>;
-	status = "okay";
-
-	proslic_spi: proslic_spi@0 {
-		compatible = "silabs,proslic_spi";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-		spi-cpha = <1>;
-		spi-cpol = <1>;
-		channel_count = <1>;
-		debug_level = <4>;       /* 1 = TRC, 2 = DBG, 4 = ERR */
-		reset_gpio = <&pio 7 0>;
-		ig,enable-spi = <1>;     /* 1: Enable, 0: Disable */
-	};
-};
-
-&gmac1 {
-	phy-mode = "2500base-x";
-	phy-connection-type = "2500base-x";
-	phy-handle = <&phy6>;
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan1";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan2";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan3";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan4";
-		};
-
-		port@4 {
-			reg = <4>;
-			label = "wan";
-		};
-
-		port@5 {
-			reg = <5>;
-			label = "lan6";
-
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-		};
-
-		port@6 {
-			reg = <6>;
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&ssusb {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso

@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
-	fragment@0 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_emmc_51>;
-			pinctrl-1 = <&mmc0_pins_emmc_51>;
-			bus-width = <8>;
-			max-frequency = <200000000>;
-			cap-mmc-highspeed;
-			mmc-hs200-1_8v;
-			mmc-hs400-1_8v;
-			hs400-ds-delay = <0x12814>;
-			vqmmc-supply = <&reg_1p8v>;
-			vmmc-supply = <&reg_3p3v>;
-			non-removable;
-			no-sd;
-			no-sdio;
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			card@0 {
-				compatible = "mmc-card";
-				reg = <0>;
-
-				block {
-					compatible = "block-device";
-					partitions {
-						block-partition-env {
-							partname = "ubootenv";
-
-							nvmem-layout {
-								compatible = "u-boot,env";
-							};
-						};
-						emmc_rootfs: block-partition-production {
-							partname = "production";
-						};
-					};
-				};
-			};
-		};
-	};
-
-	fragment@2 {
-		target-path = "/chosen";
-		__overlay__ {
-			rootdisk-emmc = <&emmc_rootfs>;
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts

@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include "mt7988a-bananapi-bpi-r4.dtsi"
-
-/ {
-	model = "Bananapi BPI-R4 2.5GE PoE";
-	compatible = "bananapi,bpi-r4-poe",
-		     "mediatek,mt7988a";
-};
-
-&gmac1 {
-	phy-mode = "internal";
-	phy-connection-type = "internal";
-	phy = <&int_2p5g_phy>;
-	status = "okay";
-	openwrt,netdev-name = "lan4";
-};
-
-&int_2p5g_phy {
-	pinctrl-names = "i2p5gbe-led";
-	pinctrl-0 = <&i2p5gbe_led0_pins>;
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso

@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&pcf8563>;
-		__overlay__ {
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso

@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
-	fragment@1 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_sdcard>;
-			pinctrl-1 = <&mmc0_pins_sdcard>;
-			cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
-			bus-width = <4>;
-			max-frequency = <52000000>;
-			cap-sd-highspeed;
-			vmmc-supply = <&reg_3p3v>;
-			vqmmc-supply = <&reg_3p3v>;
-			no-mmc;
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			card@0 {
-				compatible = "mmc-card";
-				reg = <0>;
-
-				block {
-					compatible = "block-device";
-					partitions {
-						block-partition-env {
-							partname = "ubootenv";
-
-							nvmem-layout {
-								compatible = "u-boot,env";
-							};
-						};
-						sd_rootfs: block-partition-production {
-							partname = "production";
-						};
-					};
-				};
-			};
-		};
-	};
-
-	fragment@2 {
-		target-path = "/chosen";
-		__overlay__ {
-			rootdisk-sd = <&sd_rootfs>;
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso

@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
-	fragment@0 {
-		target-path = "/";
-		__overlay__ {
-			wifi_12v: regulator-wifi-12v {
-				compatible = "regulator-fixed";
-				regulator-name = "wifi";
-				regulator-min-microvolt = <12000000>;
-				regulator-max-microvolt = <12000000>;
-				gpios = <&pio 4 GPIO_ACTIVE_HIGH>;
-				enable-active-high;
-				regulator-always-on;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&i2c_wifi>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			// 5G WIFI MAC Address EEPROM
-			wifi_eeprom@51 {
-				compatible = "atmel,24c02";
-				reg = <0x51>;
-				address-bits = <8>;
-				page-size = <8>;
-				size = <256>;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_5g: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-				};
-			};
-
-			// 6G WIFI MAC Address EEPROM
-			wifi_eeprom@52 {
-				compatible = "atmel,24c02";
-				reg = <0x52>;
-				address-bits = <8>;
-				page-size = <8>;
-				size = <256>;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_6g: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-				};
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&pcie0>;
-		__overlay__ {
-			#address-cells = <3>;
-			#size-cells = <2>;
-
-			pcie@0,0 {
-				#address-cells = <3>;
-				#size-cells = <2>;
-				reg = <0x0000 0 0 0 0>;
-
-				wifi@0,0 {
-					compatible = "mediatek,mt76";
-					reg = <0x0000 0 0 0 0>;
-					nvmem-cell-names = "mac-address";
-					nvmem-cells = <&macaddr_5g>;
-				};
-			};
-		};
-	};
-
-	fragment@3 {
-		target = <&pcie1>;
-		__overlay__ {
-			#address-cells = <3>;
-			#size-cells = <2>;
-
-			pcie@0,0 {
-				#address-cells = <3>;
-				#size-cells = <2>;
-				reg = <0x0000 0 0 0 0>;
-
-				wifi@0,0 {
-					compatible = "mediatek,mt76";
-					reg = <0x0000 0 0 0 0>;
-					nvmem-cell-names = "mac-address";
-					nvmem-cells = <&macaddr_6g>;
-				};
-			};
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts

@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include "mt7988a-bananapi-bpi-r4.dtsi"
-
-/ {
-	model = "Bananapi BPI-R4";
-	compatible = "bananapi,bpi-r4",
-		     "mediatek,mt7988a";
-
-	/* SFP2 cage (LAN) */
-	sfp2: sfp2 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp2>;
-		los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
-		rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
-		maximum-power-milliwatt = <3000>;
-	};
-};
-
-&gmac1 {
-	sfp = <&sfp2>;
-	managed = "in-band-status";
-	phy-mode = "usxgmii";
-	status = "okay";
-	openwrt,netdev-name = "sfp-lan";
-};
-
-&pca9545 {
-	i2c_sfp2: i2c@2 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <2>;
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi

@@ -1,596 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7988a.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-
-/ {
-	model = "Bananapi BPI-R4";
-	compatible = "bananapi,bpi-r4",
-		     "mediatek,mt7988a";
-
-	aliases {
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-		led-boot = &led_green;
-		led-failsafe = &led_green;
-		led-running = &led_green;
-		led-upgrade = &led_green;
-		serial0 = &serial0;
-	};
-
-	chosen {
-		stdout-path = &serial0;
-		bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait";
-		rootdisk-spim-nand = <&ubi_rootfs>;
-	};
-
-	memory {
-		reg = <0x00 0x40000000 0x00 0x10000000>;
-	};
-
-	/* SFP1 cage (WAN) */
-	sfp1: sfp1 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp1>;
-		los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
-		rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
-		maximum-power-milliwatt = <3000>;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "WPS";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-
-		led_green: led-green {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		led_blue: led-blue {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		/* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
-		cooling-levels = <0 80 128 255>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm0_pins>;
-		pwms = <&pwm 0 50000>;
-		#cooling-cells = <2>;
-		#thermal-sensor-cells = <1>;
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&eth {
-	status = "okay";
-};
-
-&gmac0 {
-	status = "okay";
-};
-
-&gmac2 {
-	sfp = <&sfp1>;
-	managed = "in-band-status";
-	phy-mode = "usxgmii";
-	status = "okay";
-	openwrt,netdev-name = "sfp-wan";
-};
-
-&switch {
-	status = "okay";
-};
-
-&gsw_phy0 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe0_led0_pins>;
-};
-
-&gsw_port0 {
-	label = "wan";
-};
-
-&gsw_phy0_led0 {
-	status = "okay";
-	function = LED_FUNCTION_WAN;
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy1 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe1_led0_pins>;
-};
-
-&gsw_port1 {
-	label = "lan1";
-};
-
-&gsw_phy1_led0 {
-	status = "okay";
-	function = LED_FUNCTION_LAN;
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy2 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe2_led0_pins>;
-};
-
-&gsw_port2 {
-	label = "lan2";
-};
-
-&gsw_phy2_led0 {
-	status = "okay";
-	function = LED_FUNCTION_LAN;
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy3 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe3_led0_pins>;
-};
-
-&gsw_port3 {
-	label = "lan3";
-};
-
-&gsw_phy3_led0 {
-	status = "okay";
-	function = LED_FUNCTION_LAN;
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&cpu0 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu1 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu2 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu3 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cci {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-	status = "okay";
-
-	rt5190a_64: rt5190a@64 {
-		compatible = "richtek,rt5190a";
-		reg = <0x64>;
-		vin2-supply = <&rt5190_buck1>;
-		vin3-supply = <&rt5190_buck1>;
-		vin4-supply = <&rt5190_buck1>;
-
-		regulators {
-			rt5190_buck1: buck1 {
-				regulator-name = "rt5190a-buck1";
-				regulator-min-microvolt = <5090000>;
-				regulator-max-microvolt = <5090000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			buck2 {
-				regulator-name = "vcore";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			rt5190_buck3: buck3 {
-				regulator-name = "vproc";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-			};
-			buck4 {
-				regulator-name = "rt5190a-buck4";
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			ldo {
-				regulator-name = "rt5190a-ldo";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_1_pins>;
-	status = "okay";
-
-	pca9545: i2c-switch@70 {
-		reg = <0x70>;
-		compatible = "nxp,pca9545";
-		reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		i2c_rtc: i2c@0 { //eeprom,rtc,ngff
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0>;
-
-			eeprom@50 {
-				compatible = "atmel,24c02";
-				reg = <0x50>;
-				address-bits = <8>;
-				page-size = <8>;
-				size = <256>;
-			};
-
-			eeprom@57 {
-				compatible = "atmel,24c02";
-				reg = <0x57>;
-				address-bits = <8>;
-				page-size = <8>;
-				size = <256>;
-			};
-
-			pcf8563: rtc@51 {
-				compatible = "nxp,pcf8563";
-				reg = <0x51>;
-				status = "disabled";
-			};
-		};
-
-		i2c_sfp1: i2c@1 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <1>;
-		};
-
-		i2c_wifi: i2c@3 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <3>;
-		};
-	};
-};
-
-/* mPCIe SIM2 */
-&pcie0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie0_pins>;
-	status = "okay";
-};
-
-/* mPCIe SIM3 */
-&pcie1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie1_pins>;
-	status = "okay";
-};
-
-/* M.2 key-B SIM1 */
-&pcie2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie2_pins>;
-	status = "okay";
-};
-
-/* M.2 key-M SSD */
-&pcie3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie3_pins>;
-	status = "okay";
-};
-
-&pio {
-	mdio0_pins: mdio0-pins {
-		mux {
-			function = "eth";
-			groups = "mdc_mdio0";
-		};
-
-		conf {
-			groups = "mdc_mdio0";
-			drive-strength = <MTK_DRIVE_8mA>;
-		};
-	};
-
-	i2c0_pins: i2c0-pins-g0 {
-		mux {
-			function = "i2c";
-			groups = "i2c0_1";
-		};
-	};
-
-	i2c2_1_pins: i2c2-pins-g1 {
-		mux {
-			function = "i2c";
-			groups = "i2c2_1";
-		};
-	};
-
-	gbe0_led0_pins: gbe0-led0-pins {
-		mux {
-			function = "led";
-			groups = "gbe0_led0";
-		};
-	};
-
-	gbe1_led0_pins: gbe1-led0-pins {
-		mux {
-			function = "led";
-			groups = "gbe1_led0";
-		};
-	};
-
-	gbe2_led0_pins: gbe2-led0-pins {
-		mux {
-			function = "led";
-			groups = "gbe2_led0";
-		};
-	};
-
-	gbe3_led0_pins: gbe3-led0-pins {
-		mux {
-			function = "led";
-			groups = "gbe3_led0";
-		};
-	};
-
-	i2p5gbe_led0_pins: 2p5gbe-led0-pins {
-		mux {
-			function = "led";
-			groups = "2p5gbe_led0";
-		};
-	};
-
-	mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
-		mux {
-			function = "flash";
-			groups = "emmc_51";
-		};
-	};
-
-	mmc0_pins_sdcard: mmc0-pins-sdcard {
-		mux {
-			function = "flash";
-			groups = "sdcard";
-		};
-	};
-
-	pwm0_pins: pwm0-pins {
-		mux {
-			groups = "pwm0";
-			function = "pwm";
-		};
-	};
-
-	uart0_pins: uart0-pins {
-		mux {
-			function = "uart";
-			groups =  "uart0";
-		};
-	};
-
-	uart1_2_lite_pins: uart1-2-lite-pins {
-		mux {
-			function = "uart";
-			groups =  "uart1_2_lite";
-		};
-	};
-
-	uart2_3_pins: uart2-3-pins {
-		mux {
-			function = "uart";
-			groups =  "uart2_3";
-		};
-	};
-
-	spi0_flash_pins: spi0-flash-pins {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-	};
-};
-
-&pwm {
-	status = "okay";
-};
-
-&cpu_thermal {
-	trips {
-		cpu_trip_hot: hot {
-			temperature = <120000>;
-			hysteresis = <2000>;
-			type = "hot";
-		};
-
-		cpu_trip_active_high: active-high {
-			temperature = <115000>;
-			hysteresis = <2000>;
-			type = "active";
-		};
-
-		cpu_trip_active_med: active-med {
-			temperature = <85000>;
-			hysteresis = <2000>;
-			type = "active";
-		};
-
-		cpu_trip_active_low: active-low {
-			temperature = <40000>;
-			hysteresis = <2000>;
-			type = "active";
-		};
-	};
-
-	cooling-maps {
-		cpu-active-high {
-		/* active: set fan to cooling level 2 */
-			cooling-device = <&fan 3 3>;
-			trip = <&cpu_trip_active_high>;
-		};
-
-		cpu-active-low {
-		/* active: set fan to cooling level 1 */
-			cooling-device = <&fan 2 2>;
-			trip = <&cpu_trip_active_med>;
-		};
-
-		cpu-passive {
-		/* passive: set fan to cooling level 0 */
-			cooling-device = <&fan 1 1>;
-			trip = <&cpu_trip_active_low>;
-		};
-	};
-};
-
-&ssusb1 {
-	status = "okay";
-};
-
-&tphy {
-	status = "okay";
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_flash_pins>;
-	status = "okay";
-
-	spi_nand: spi_nand@0 {
-		compatible = "spi-nand";
-		reg = <0>;
-		spi-max-frequency = <52000000>;
-		spi-tx-buswidth = <4>;
-		spi-rx-buswidth = <4>;
-	};
-};
-
-&spi_nand {
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		partition@0 {
-			label = "bl2";
-			reg = <0x0 0x200000>;
-			read-only;
-		};
-
-		partition@200000 {
-			label = "ubi";
-			reg = <0x200000 0x7e00000>;
-			compatible = "linux,ubi";
-
-			volumes {
-				ubi-volume-ubootenv {
-					volname = "ubootenv";
-					nvmem-layout {
-						compatible = "u-boot,env-redundant-bool";
-					};
-				};
-
-				ubi-volume-ubootenv2 {
-					volname = "ubootenv2";
-					nvmem-layout {
-						compatible = "u-boot,env-redundant-bool";
-					};
-				};
-
-				ubi_rootfs: ubi-volume-fit {
-					volname = "fit";
-				};
-			};
-		};
-	};
-};
-
-&serial0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-	status = "okay";
-};
-
-&serial1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_2_lite_pins>;
-};
-
-&serial2 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_3_pins>;
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&xsphy {
-	status = "okay";
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso

@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mmc0>;
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_emmc_51>;
-			pinctrl-1 = <&mmc0_pins_emmc_51>;
-			bus-width = <8>;
-			max-frequency = <200000000>;
-			cap-mmc-highspeed;
-			mmc-hs200-1_8v;
-			mmc-hs400-1_8v;
-			hs400-ds-delay = <0x12814>;
-			vqmmc-supply = <&reg_1p8v>;
-			vmmc-supply = <&reg_3p3v>;
-			non-removable;
-			no-sd;
-			no-sdio;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso

@@ -1,42 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Aquantia AQR113C */
-			phy0: ethernet-phy@0 {
-				reg = <0>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
-				reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
-				reset-assert-us = <100000>;
-				reset-deassert-us = <221000>;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "usxgmii";
-			phy-connection-type = "usxgmii";
-			phy = <&phy0>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "internal";
-			phy-connection-type = "internal";
-			phy = <&int_2p5g_phy>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target = <&int_2p5g_phy>;
-		__overlay__ {
-			pinctrl-names = "i2p5gbe-led";
-			pinctrl-0 = <&i2p5gbe_led0_pins>;
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso

@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Maxlinear GPY211C */
-			phy13: ethernet-phy@13 {
-				reg = <13>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-connection-type = "2500base-x";
-			phy = <&phy13>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso

@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&i2c2>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c2_0_pins>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target-path = "/";
-		__overlay__ {
-			sfp_esp1: sfp@1 {
-				compatible = "sff,sfp";
-				i2c-bus = <&i2c2>;
-				mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
-				los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
-				tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
-				maximum-power-milliwatt = <3000>;
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "10gbase-r";
-			managed = "in-band-status";
-			sfp = <&sfp_esp1>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso

@@ -1,42 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Aquantia AQR113C */
-			phy8: ethernet-phy@8 {
-				reg = <8>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
-				reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
-				reset-assert-us = <100000>;
-				reset-deassert-us = <221000>;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "usxgmii";
-			phy-connection-type = "usxgmii";
-			phy = <&phy8>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso

@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Maxlinear GPY211C */
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-connection-type = "2500base-x";
-			phy = <&phy5>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso

@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&i2c1>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c1_sfp_pins>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target-path = "/";
-		__overlay__ {
-			sfp_esp0: sfp@0 {
-				compatible = "sff,sfp";
-				i2c-bus = <&i2c1>;
-				mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
-				los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
-				tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
-				maximum-power-milliwatt = <3000>;
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "10gbase-r";
-			managed = "in-band-status";
-			sfp = <&sfp_esp0>;
-			status = "okay";
-		};
-	};
-};

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso

@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@1 {
-		target-path = <&mmc0>;
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_sdcard>;
-			pinctrl-1 = <&mmc0_pins_sdcard>;
-			cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
-			bus-width = <4>;
-			max-frequency = <52000000>;
-			cap-sd-highspeed;
-			vmmc-supply = <&reg_3p3v>;
-			vqmmc-supply = <&reg_3p3v>;
-			no-mmc;
-			status = "okay";
-		};
-	};
-};