Change devices with RTL8231 GPIO expander definition that can easily be
translated to the new RTL8231 binding and carry over any gpio-hogs. This
will let them use the new RTL8231 MFD driver, without any functional
changes.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit b7af54d5c1)
Zyxel GS1900-8 v2 devices have been produced more recently than v1
devices. As there are v1 boards with RTL8380M rev. C SoCs, it can likely
safely be assumed that all v2 devices will also have a recent SoC
revision, supporting the hardware auxiliary MDIO controller.
Make the GS1900-8 v1 use an emulated auxiliary MDIO bus, for backward
compatibility with devices containing an RTL8380M rev. A.
Since the devicetrees are otherwise identical, GS1900-8 v1 devices with
an RTL8380M rev. B or C will also be able to use the (more efficient) v2
image. This includes any currently functioning device with OpenWrt, so
include the old compatible as a supported device for the GS1900-8 v2.
Link: https://github.com/openwrt/openwrt/issues/9534
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 7322d3266d)
The mdio-gpio driver is required to support early revision of RTL8380M
slicon (rev A) where the auxilairy MDIO controller does not function
correctly. Add this driver to the rtl838x kernel so devices with old
SoCs are also able to function correctly.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit efffcfa436)
In order to be able to define the external GPIO controller on an
emulated MDIO bus, move the controller definition outside of the main
GS1900 include for RTL838x-based devices.
Additionally, a new DTSI is provided defining the RTL8231 on the
emulated MDIO bus.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit a6a77896f4)
Some RTL8380M-based devices have been around for a long time and use an
early A revision of the RTL8380M SoC. This revision has an issue with
the auxiliary MDIO controller, causing it to malfunction. This may lead
to device reboots when the controller is used.
Provide a bit-banged MDIO bus, which muxes the auxiliary MDIO pins to
their GPIO function. Although this will result in lower performance,
there should otherwise be no functional differences.
Link: https://github.com/openwrt/openwrt/issues/9534
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit d4bf16a9e1)
As the bootloader is reconfiguring the RTL8231 on these devices anyway,
no pin state can be maintained over warm reboots. This results in for
example the PoE disable pin always being asserted by the bootloader.
Define the GPIO line linked to the RTL8231's reset so the MDIO subsystem
will also reset the expander on boot and ensure the line in the correct
state.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit b2d17dbb68)
Switch the Zyxel GS1900-48 over to the new MDIO-based driver for the
RTL8231 GPIO expander.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 45aafe67f3)
Enable the RTL8231 MFD core driver, as well as the pinctrl/gpio driver
to allow RTL839x devices to use it.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit fd5797b7ce)
Enable the driver for the Realtek Otto auxiliary MDIO driver so RTL839x
devices can use it. The related node is added to the base devicetree for
rtl839x-based devices, so they can enabled and use it when required.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit cddcc69ddf)
For RTL839x, the driver was producing frequent timeouts on bus accesses.
Increasing the timeout to the one from a recent Realtek SDK resolves
these timeouts. To minimize overhead on different SoCs, each controller
can specify their own timeout.
This also add support for the register format as used on RTL93xx.
Support is added for the RTL930x "ext gpio" controller.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 52ffef6471)
regmap_read_poll_timeout() relies on usleep_range() to time the polling
loop. With the current, rather large, scheduling interval, a short
usleep_range() may take a lot longer than expected, causing performance
issues.
Switch the driver over to using regmap_read_poll_timeout_atomic(), which
uses udelay() to time the polling loop.
For comparision, the 'ethtool -m <dev>' command is about 10 times faster
with the atomic variant.
Using 'perf -r10 ethtool -m lan25':
- Driver using regmap_read_poll_timeout():
2.0117 +- 0.0118 seconds time elapsed ( +- 0.58% )
- Driver using regmap_read_poll_timeout_atomic():
0.1674 +- 0.0250 seconds time elapsed ( +- 14.95% )
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 693c1ea81a)
Apply the equivalent of commit f64541db02 ("realtek: HPE 1920 8G PoE+
180W move fans to hwmon") to the 24-ports variants of the HPE 1920 PoE+
switches, with model numbers JG925A and JG926A.
Copy from the original commit message:
Move to using hwmon and gpio-fan. This is by adding gpio_fan_array to
DTS and kmod-hwmon-gpiofan to DEVICE_PACKAGES.
In combination with the new rtl8231 gpio driver the default fan
behaviour will be maximum fan speed.
Bump compat value to 1.1 due to existing config in /etc/config/system
via gpio_switch. Also notify in device compat that fan is now going to
be at bootloader setting (maximum in this case) by default unless turned
down.
As the init script 03_gpio_switches does not perform any action after
removing these devices from it, the file can be dropped.
Link: https://github.com/openwrt/openwrt/pull/17598
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 0a7c8ed9d9)
Update the base DTS file for the 16 and 24 port HPE 1920 devices
(JG923A, JG924A, JG925A, JG926A), causing the new RTL8231 MFD driver to
be loaded at start-up.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 96850585e5)
The GPIO numbering has changed and is not stable. As a result fan
control via gpio_switch is broken, resulting in errors:
"export_store: invalid GPIO 456"
Move to using hwmon and gpio-fan. This is by adding gpio_fan_array to
DTS and kmod-hwmon-gpiofan to DEVICE_PACKAGES.
In combination with the new rtl8231 gpio driver the default fan
behaviour will be maximum fan speed.
Bump compat value to 1.1 due to existing config in /etc/config/system
via gpio_switch. Also notify in device compat that fan is now going to
be at bootloader setting (maximum in this case) by default unless turned
down.
Signed-off-by: Evan Jobling <evan@jobling.au>
Link: https://github.com/openwrt/openwrt/pull/17605
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit f64541db02)
Update the base DTS file for the 8 port HPE 1920 devices (JG920A,
JG921A, JG922A), causing the new RTL8231 MFD driver to be loaded at
start-up.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit e5d1a501cb)
Update the devicetree files to switch the GS1900 devices over to the new
pinctrl and GPIO driver. Enable the drivers to ensure the nodes can be
used.
This may fix issues caused by bad RMW behaviour on the GPIO data lines,
or glitches due to setting the pin direction before the pin level.
Although the driver supports retaining GPIO state after a warm boot,
some bootloaders appear to apply a default configuration on boot, which
may cause an interrupt in PoE-PSE support.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 5141e2d861)
Add pending patches to add RTL8231 support as a MDIO-bus attached
multi-functional device. This includes subdrivers for the pincontrol and
GPIO features, as well as the LED matrix support.
Leave the drivers disabled until required by a device.
Cherry picked from commit 6ef6014887, but
dropped already picked patch for gpio-regmap request/free, and rebased
configs
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add a disabled node for the auxiliary MDIO bus, used to manage the
RTL8231 expanders. A simple-mfd parent node is added, at the same
(implied) address as the switch@1b000000 node, as the switch drivers
should anyway transistion to MFD subdivices at some point.
Additionally, two pinctrl-single node are added to allow the MDX pins to
be muxed correctly, in case the bootloader leaves these unconfigured.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 92ae8cb16c)
Add a driver that exposes the auxiliary busses, used for the RTL8231
expanders, as a proper MDIO controller. The device must be instantiated
under an MFD device, so the driver should also be compatible with SoC
managed by an external CPU via SPI.
Leave the driver disabled in builds until required.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit ae833c01b3)
Apply "u-boot-dont-touch-spi-nand" to ASUS RT-AX59U, ASUS TUF-AX4200 as
well as ASUS TUF-AX6000 routers to prevent U-Boot from wiping MTD
child nodes from DT.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 4387de9445)
ASUS makes use of U-Boot's fdt_fixup_mtdparts() function which applies
the partitions defined in U-Boot's mtdparts and mtdids environment
variables to the devicetree passed over to Linux.
The undesired side-effect is that in this way also all additional
properties and child nodes get wiped, preventing NVMEM cells to be
defined for MTD partitions or UBI volumes.
To work-around this issue, add an additional compatible string
'u-boot-dont-touch-spi-nand' which can be used instead of 'spi-nand' in
case the replacement of the MTD partitions by U-Boot should be skipped
alltogether.
In practise this is mostly relevant for SPI-NAND which anyway comes only
with two partitions nowadays: 'Bootloader' and 'UBI_DEV'. Hence this
work-around is applicable for SPI-NAND only. Similar work-arounds for
other MTD devices can be created as well should they actually be needed.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit c48afca32c)
Add kernel command line replacement hack to qualcommax. Now we can
find and replace arguments in the kernel command line by setting
bootargs-find-1, bootargs-replace-1, bootargs-exact-match-1
and bootargs-find-2, bootargs-replace-2, bootargs-exact-match-2
under the chosen node in the device tree.
This hack replaces the first occurence of bootargs-find-X with
bootargs-replace-X. When bootargs-exact-match-X is set to "y",
then the replacement happens only if the kernel command line is
identical to bootargs-find-X.
Signed-off-by: Qiyuan Zhang <zhang.github@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/16070
(cherry picked from commit 337f6f76ca5361f45e76facd52396936b9fc25c0)
Signed-off-by: Rafal Boni <rafal.boni@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17889
Signed-off-by: Robert Marko <robimarko@gmail.com>
Currently for Linksys MX4200v2 all u-boot ethXaddr variables share the same MAC address
and there is no need to check them one by one.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16070
(cherry picked from commit 80c867815636cbf32e85b431c5d06c531e4a371e)
Signed-off-by: Rafal Boni <rafal.boni@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17889
Signed-off-by: Robert Marko <robimarko@gmail.com>
Create a generic Linksys MX4x00 dts file and extract the specific configuration
for MX4200v1/v2 to a new file.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16070
(cherry picked from commit ff85f883ea94f562af618fb26ba8b5e85e572d64)
Signed-off-by: Rafal Boni <rafal.boni@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17889
Signed-off-by: Robert Marko <robimarko@gmail.com>
The default value for the "root" parameter is "/dev/ubiblock0_0"
and there is no need to append it to bootargs.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16070
(cherry picked from commit fee2d93b276f3c44dad83849f9959638ce495de7)
Signed-off-by: Rafal Boni <rafal.boni@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17889
Signed-off-by: Robert Marko <robimarko@gmail.com>
This reverts commit f628467dfd.
The initial fix was correct. However, a recently introduced bug in
base-files can cause some unexpected byte overwriting in eeprom.
Since it has been fixed, let's accept this patch again.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Link: https://github.com/openwrt/openwrt/pull/17892
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 43bc5e6e12)
When support for Routerboard 911G was introduced, Routerboad 912UAG
device tree was used as a base, and the common part. This led to use of
40MHz as the reference clock frequency for both [1], while RB911G uses 25MHz
crystal on the board, causing heavy system clock drift.
Split the definition, and set the reference clock frequency for RB911G
back to 25MHz.
[1] a716ac5564 ("ath79: fix reference clock for RouterBoard 912UAG")
Fixes: bcc44b1212 ("ath79: support for MikroTik RouterBOARD 911G-(2,5)HPnD")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17944
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 40fc6bd5cc)
The GW82xx-2x has two network ports. By convention, the first
port (eth0) should be the WAN port and the second port (eth1)
should be the LAN port.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Link: https://github.com/openwrt/openwrt/pull/17717
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17762
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit d2eaaa90d5)
The act of attempting link at gen1 then trying to link at higher speeds
causes a hang with the specific PCIe switch used on the Gateworks Venice
boards. Work around this by linking at the highest speed first as is
common with all other PCI controller drivers.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Link: https://github.com/openwrt/openwrt/pull/17717
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17762
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 23a18a57cf)
This commit fixes nmbm configuration mismatch error on Xiaomi AX3000t
with Winbond W25N01KVZEIR spi-nand:
'''
[ 0.786783] NMBM configuration mismatch
'''
Root cause:
1. U-Boot W25N01KV spi-nand driver ia compiled with 64B OOB size for the
chip and store this size in the nmbm signature;
2. Linux W25N01KV driver use 96B OOB.
The change doesn't affect AX3000t variants with other spi-nand chips
(ESMT, Foresee) because their Linux drivers use 64B OOB.
Fixes: openwrt#16972
Tested-by: Aleksandr Danilov <sc16me@gmail.com>
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17549
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 3299d19c01)
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17898
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit adds new "mediatek,bmt-mtd-overridden-oobsize" property. The
property helps avoid "NMBM configuration mismatch" error if mtd "OOB size"
is not equal to the "spare size" which is stored in the nmbm signature.
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17549
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit e585ae70d4)
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17898
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
b11bff90f2ad r8169: add support for RTL8125BP rev.b
b3593df26ab1 r8169: add support for RTL8125D rev.b
b299ea006928 r8169: adjust version numbering for RTL8126
bb18265c3aba r8169: remove support for chip version 11
2e20bf8cc057 r8169: remove unused flag RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE
e340bff27e63 r8169: copy vendor driver 2.5G/5G EEE advertisement constraints
The EEE advertisement patch has been reworked for linux v6.6 because
phy_set_eee_broken() is only present on linux >= v6.13 and eee_broken_modes
declaration has been converted to a bitmap, so linkmode_set_bit() can't be
used either.
e340bff27eed623fb8e3721aa69e70
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry picked from commit 084618f8db)
This reverts commit 3295f6f1c2.
It looks like the eeprom gets broken after this change.
I think this change was not tested on a real device before it was
merged.
The MAC addresses will be broken again after this revert.
Fixes: #17818
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit f628467dfd)
Fix broken WAN on Linksys EAX and Asrock G10 by incrementing the WAN
interface MAC address + 1. This caused conflicting entry in the FDB
table and caused the WAN port to malfunction with the DSA conversion.
Fixes: #17157Fixes: #15585Fixes: #16604
Link: https://github.com/openwrt/openwrt/pull/17839
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
(cherry picked from commit eba2fbf638)
Two commits which made their way into Linux stable broke the SATA
support on the BPi-R64.
Fix this by reverting a node rename which broke DT-overlay application
and import a (still pending) patch re-adding the 'syscon' compatible to
the pciesys clock-controller which also contains phy-mode bits
referenced by the ahci_mtk driver expecting to access them using
syscon_regmap_lookup_by_phandle().
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 69890e16b3)
On some but not all devices using the RTL8221B 2.5GBit/s PHY the SerDes
setup sequence may hang under some circumstances (eg. <2500M link
partner present during boot).
RTL8221B-VB-CG 2.5Gbps PHY (C45) mdio-bus:01: rtl822xb_config_init failed: -110
Work-around the issue by performing a hardware reset and subsequent
retry of the SerDes setup, which seems to always succeed.
Doing this requires moving ALDPS setup to config_init (which is anyway
the better place for that) as it otherwise doesn't survive the reset.
Also disable listening on MDIO address 0 which may be used by other PHYs
despite being spec'ed as "broadcast address", as bus activity on address
0 may otherwise confuse the RealTek PHY for good reasons.
Tested-by: Luis Mita <luis@luismita.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit c87a767801)
Link: https://github.com/openwrt/openwrt/pull/17790
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The mt76x8 SDXC pin register definition is incompatible with the
mtmips generic pinctrl driver structure. This hack allows us to
mux the SDXC IO to different pin groups in device tree.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Link: https://github.com/openwrt/openwrt/pull/17446
(cherry picked from commit 05ec3b50a8)
Link: https://github.com/openwrt/openwrt/pull/17754
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The definition for the netgear_wndr4700 had two different
DEVICE_COMPAT_VERSION definitions.
In commit 5815884c3a ("apm821xx: migrate to DSA"), an additional
DEVICE_COMPAT_VERSION := 3.0 attribute was added to the device
definition. The old one with version 2.0 stayed and was defined later
overwriting the new one.
Replace the old version 2.0 with the new version 3.0
Fixes: 5815884c3a ("apm821xx: migrate to DSA")
Link: https://forum.openwrt.org/t/openwrt-24-10-0-rc6-sixth-release-candidate/222466/43
Link: https://github.com/openwrt/openwrt/pull/17741
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit dab52c00d7)
The STM32MP135F-DK board uses the LAN8742 PHY.
Enable CONFIG_SMSC_PHY to have full PHY support.
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://github.com/openwrt/openwrt/pull/17745
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit d981f28f76)
Since commit f1c9afd801 ("ramips: mt7621-dts: mux phy0/4 to gmac1") the
USW-Flex lan1 port has been attached directly to the CPU. This improves
routing performance but hinders switching.
This is a generally accepted trade-off in that commit but for USW-Flex it
is a questionable choice. This switch is designed to deliver PoE to remote
places and using it as a router is unlikely. Meanwhile, the lan1 port is
also PoE-in and will often be the uplink, carrying most of the traffic.
Reverting f1c9afd801 for USW-Flex restores full 1 Gbps switching
performance on all ports.
Signed-off-by: Anders Melchiorsen <amelchio@nogoto.net>
Link: https://github.com/openwrt/openwrt/pull/17703
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 62872f8bfd)
