forked from mirror/openwrt
realtek: rtl930x: move serdes functions over to mdio bus
The migration of the RTL930x mdio/serdes access functions over to the mdio bus is a little more complicated than for RTL83xx. There are several places where the serdes is accessed directly. So do it in two steps. With this first step: - use the rtmdio prefix for the serdes reader/writer functions - move the functions over to the bus (inside the ethernet driver) - Adapt all callers. This is not only a copy/paste but the serdes access will be hardened too. For this: - put a mutex around the read/write functions because we have only indirect register access through a mdio style bus. - Verify input values to avoid data mess. Tested-by: Bjørn Mork <bjorn@mork.no> Tested-by: Jan Hoffmann <jan@3e8.eu> Tested-by: Jonas Jelonek <jelonek.jonas@gmail.com> Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/19662 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Markus Stockhausen
Robert Marko
parent
6719bf5672
commit
e0ba4cf086
4 changed files with 116 additions and 96 deletions
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@ -29,10 +29,8 @@ extern int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, voi
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extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
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extern int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
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extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
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extern int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
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extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
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extern int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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@ -76,8 +74,10 @@ extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
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#define RTMDIO_ABS BIT(2)
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#define RTMDIO_PKG BIT(3)
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#define RTMDIO_838X_BASE (0xe780)
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#define RTMDIO_839X_BASE (0xa000)
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#define RTMDIO_838X_BASE (0xe780)
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#define RTMDIO_839X_BASE (0xa000)
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#define RTMDIO_930X_SDS_INDACS_CMD (0x03B0)
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#define RTMDIO_930X_SDS_INDACS_DATA (0x03B4)
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struct p_hdr {
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uint8_t *buf;
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@ -1632,6 +1632,7 @@ static int rtl838x_set_link_ksettings(struct net_device *ndev,
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*/
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DEFINE_MUTEX(rtmdio_lock);
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DEFINE_MUTEX(rtmdio_lock_sds);
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struct rtmdio_bus_priv {
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u16 id;
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@ -2211,6 +2212,70 @@ errout:
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return err;
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}
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/*
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* The RTL930x family has 12 SerDes of three types. They are accessed through two IO registers at
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* 0xbb0003b0 which simulate commands to an internal MDIO bus:
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*
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* - SerDes 0-1 exist on the RTL9301 and 9302B and are QSGMII capable
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* - SerDes 2-9 are USXGMII capabable with either quad or single configuration
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* - SerDes 10-11 are 10GBase-R capable
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*/
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int rtmdio_930x_read_sds_phy(int sds, int page, int regnum)
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{
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int i, ret = -EIO;
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u32 cmd;
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if (sds < 0 || sds > 11 || page < 0 || page > 63 || regnum < 0 || regnum > 31)
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return -EIO;
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mutex_lock(&rtmdio_lock_sds);
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cmd = sds << 2 | page << 7 | regnum << 13 | 1;
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sw_w32(cmd, RTMDIO_930X_SDS_INDACS_CMD);
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for (i = 0; i < 100; i++) {
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if (!(sw_r32(RTMDIO_930X_SDS_INDACS_CMD) & 0x1))
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break;
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mdelay(1);
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}
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if (i < 100)
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ret = sw_r32(RTMDIO_930X_SDS_INDACS_DATA) & 0xffff;
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mutex_unlock(&rtmdio_lock_sds);
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return ret;
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}
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int rtmdio_930x_write_sds_phy(int sds, int page, int regnum, u16 val)
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{
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int i, ret = -EIO;
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u32 cmd;
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if (sds < 0 || sds > 11 || page < 0 || page > 63 || regnum < 0 || regnum > 31)
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return -EIO;
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mutex_lock(&rtmdio_lock_sds);
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cmd = sds << 2 | page << 7 | regnum << 13 | 0x3;
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sw_w32(val, RTMDIO_930X_SDS_INDACS_DATA);
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sw_w32(cmd, RTMDIO_930X_SDS_INDACS_CMD);
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for (i = 0; i < 100; i++) {
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if (!(sw_r32(RTMDIO_930X_SDS_INDACS_CMD) & 0x1))
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break;
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mdelay(1);
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}
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mutex_unlock(&rtmdio_lock_sds);
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if (i < 100)
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ret = 0;
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return ret;
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}
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/* These are the core functions of our new Realtek SoC MDIO bus. */
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static int rtmdio_read_c45(struct mii_bus *bus, int addr, int devnum, int regnum)
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@ -2324,8 +2389,8 @@ static int rtmdio_93xx_read(struct mii_bus *bus, int addr, int regnum)
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priv->raw[addr] = (priv->page[addr] == priv->rawpage);
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if (priv->phy_is_internal[addr]) {
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if (priv->family_id == RTL9300_FAMILY_ID)
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return rtl930x_read_sds_phy(priv->sds_id[addr],
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priv->page[addr], regnum);
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return rtmdio_930x_read_sds_phy(priv->sds_id[addr],
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priv->page[addr], regnum);
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else
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return rtl931x_read_sds_phy(priv->sds_id[addr],
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priv->page[addr], regnum);
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@ -2416,8 +2481,8 @@ static int rtmdio_93xx_write(struct mii_bus *bus, int addr, int regnum, u16 val)
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priv->raw[addr] = (page == priv->rawpage);
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if (priv->phy_is_internal[addr]) {
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if (priv->family_id == RTL9300_FAMILY_ID)
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return rtl930x_write_sds_phy(priv->sds_id[addr],
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page, regnum, val);
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return rtmdio_930x_write_sds_phy(priv->sds_id[addr],
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page, regnum, val);
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else
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return rtl931x_write_sds_phy(priv->sds_id[addr],
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page, regnum, val);
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@ -456,4 +456,7 @@ int phy_port_write_paged(struct phy_device *phydev, int port, int page, u32 regn
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int rtmdio_838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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int rtmdio_838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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int rtmdio_930x_read_sds_phy(int sds, int page, int regnum);
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int rtmdio_930x_write_sds_phy(int sds, int page, int regnum, u16 val);
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#endif /* _RTL838X_ETH_H */
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@ -25,6 +25,9 @@ extern int phy_package_write_paged(struct phy_device *phydev, int page, u32 regn
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extern int phy_package_port_read_paged(struct phy_device *phydev, int port, int page, u32 regnum);
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extern int phy_package_read_paged(struct phy_device *phydev, int page, u32 regnum);
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extern int rtmdio_930x_read_sds_phy(int sds, int page, int regnum);
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extern int rtmdio_930x_write_sds_phy(int sds, int page, int regnum, u16 val);
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#define PHY_PAGE_2 2
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#define PHY_PAGE_4 4
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@ -292,53 +295,6 @@ static u32 rtl9300_sds_mode_get(int sds_num)
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return v & RTL930X_SDS_MASK;
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}
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/* On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
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* register which simulates commands to an internal MDIO bus.
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*/
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int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
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{
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int i;
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u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
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sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
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for (i = 0; i < 100; i++) {
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if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
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break;
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mdelay(1);
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}
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if (i >= 100)
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return -EIO;
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return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
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}
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int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
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{
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int i;
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u32 cmd;
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sw_w32(v, RTL930X_SDS_INDACS_DATA);
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cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
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sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
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for (i = 0; i < 100; i++) {
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if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
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break;
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mdelay(1);
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}
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if (i >= 100) {
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pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
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return -EIO;
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}
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return 0;
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}
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int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
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{
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int i;
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@ -1461,18 +1417,18 @@ static void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int sta
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if (l < 32) {
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u32 mask = BIT(l) - 1;
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data = rtl930x_read_sds_phy(sds, page, reg);
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data = rtmdio_930x_read_sds_phy(sds, page, reg);
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data &= ~(mask << start_bit);
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data |= (v & mask) << start_bit;
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}
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rtl930x_write_sds_phy(sds, page, reg, data);
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rtmdio_930x_write_sds_phy(sds, page, reg, data);
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}
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static u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
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{
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int l = end_bit - start_bit + 1;
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u32 v = rtl930x_read_sds_phy(sds, page, reg);
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u32 v = rtmdio_930x_read_sds_phy(sds, page, reg);
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if (l >= 32)
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return v;
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@ -1626,7 +1582,7 @@ static int rtsds_930x_wait_clock_ready(int sds)
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for (i = 0; i < 20; i++) {
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usleep_range(10000, 15000);
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rtl930x_write_sds_phy(base_sds, 0x1f, 0x02, 53);
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rtmdio_930x_write_sds_phy(base_sds, 0x1f, 0x02, 53);
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ready = rtl9300_sds_field_r(base_sds, 0x1f, 0x14, bit, bit);
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ready_cnt = ready ? ready_cnt + 1 : 0;
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@ -1876,8 +1832,8 @@ static void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_norm
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{
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u32 v10, v1;
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v10 = rtl930x_read_sds_phy(sds, 6, 2); /* 10GBit, page 6, reg 2 */
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v1 = rtl930x_read_sds_phy(sds, 0, 0); /* 1GBit, page 0, reg 0 */
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v10 = rtmdio_930x_read_sds_phy(sds, 6, 2); /* 10GBit, page 6, reg 2 */
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v1 = rtmdio_930x_read_sds_phy(sds, 0, 0); /* 1GBit, page 0, reg 0 */
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pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
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v10 &= ~(BIT(13) | BIT(14));
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@ -1889,11 +1845,11 @@ static void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_norm
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v10 |= tx_normal ? 0 : BIT(14);
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v1 |= tx_normal ? 0 : BIT(8);
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rtl930x_write_sds_phy(sds, 6, 2, v10);
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rtl930x_write_sds_phy(sds, 0, 0, v1);
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rtmdio_930x_write_sds_phy(sds, 6, 2, v10);
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rtmdio_930x_write_sds_phy(sds, 0, 0, v1);
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v10 = rtl930x_read_sds_phy(sds, 6, 2);
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v1 = rtl930x_read_sds_phy(sds, 0, 0);
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v10 = rtmdio_930x_read_sds_phy(sds, 6, 2);
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v1 = rtmdio_930x_read_sds_phy(sds, 0, 0);
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pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
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}
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@ -1967,9 +1923,9 @@ void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
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bool dcvs_manual;
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if (!(sds_num % 2))
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rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
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rtmdio_930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
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else
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rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
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rtmdio_930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
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/* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
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rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
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@ -2107,9 +2063,9 @@ static u32 rtl9300_sds_rxcal_leq_read(int sds_num)
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bool leq_manual;
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if (!(sds_num % 2))
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rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
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rtmdio_930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
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else
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rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
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rtmdio_930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
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/* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
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rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
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@ -2148,9 +2104,9 @@ static void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
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/* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; */ /* Lane0 */
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/* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; */ /* Lane1 */
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if (!(sds_num % 2))
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rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
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rtmdio_930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
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else
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rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
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rtmdio_930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
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/* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
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rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
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@ -2230,9 +2186,9 @@ static void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
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bool tap_manual;
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if (!(sds_num % 2))
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rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
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rtmdio_930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
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else
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rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
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rtmdio_930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
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/* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
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rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
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@ -2304,7 +2260,7 @@ static void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
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int vth_min = 0x0;
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pr_info("start_1.1.1 initial value for sds %d\n", sds);
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rtl930x_write_sds_phy(sds, 6, 0, 0);
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rtmdio_930x_write_sds_phy(sds, 6, 0, 0);
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/* FGCAL */
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rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x00);
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@ -2422,9 +2378,9 @@ static void rtl9300_do_rx_calibration_2_3(int sds_num)
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while(1) {
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if (!(sds_num % 2))
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rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
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rtmdio_930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
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else
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rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
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rtmdio_930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
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/* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
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rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
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@ -2668,8 +2624,8 @@ static int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
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case PHY_INTERFACE_MODE_10GBASER:
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/* Read twice to clear */
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rtl930x_read_sds_phy(sds_num, 5, 1);
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rtl930x_read_sds_phy(sds_num, 5, 1);
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rtmdio_930x_read_sds_phy(sds_num, 5, 1);
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rtmdio_930x_read_sds_phy(sds_num, 5, 1);
|
||||
break;
|
||||
|
||||
case PHY_INTERFACE_MODE_1000BASEX:
|
||||
|
|
@ -2698,7 +2654,7 @@ static u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
|
|||
case PHY_INTERFACE_MODE_1000BASEX:
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
case PHY_INTERFACE_MODE_10GBASER:
|
||||
v = rtl930x_read_sds_phy(sds_num, 5, 1);
|
||||
v = rtmdio_930x_read_sds_phy(sds_num, 5, 1);
|
||||
return v & 0xff;
|
||||
|
||||
default:
|
||||
|
|
@ -2748,24 +2704,24 @@ static void rtl9300_phy_enable_10g_1g(int sds_num)
|
|||
u32 v;
|
||||
|
||||
/* Enable 1GBit PHY */
|
||||
v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR);
|
||||
v = rtmdio_930x_read_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR);
|
||||
pr_info("%s 1gbit phy: %08x\n", __func__, v);
|
||||
v &= ~BMCR_PDOWN;
|
||||
rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR, v);
|
||||
rtmdio_930x_write_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR, v);
|
||||
pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
|
||||
|
||||
/* Enable 10GBit PHY */
|
||||
v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR);
|
||||
v = rtmdio_930x_read_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR);
|
||||
pr_info("%s 10gbit phy: %08x\n", __func__, v);
|
||||
v &= ~BMCR_PDOWN;
|
||||
rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR, v);
|
||||
rtmdio_930x_write_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR, v);
|
||||
pr_info("%s 10gbit phy after: %08x\n", __func__, v);
|
||||
|
||||
/* dal_longan_construct_mac_default_10gmedia_fiber */
|
||||
v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
|
||||
v = rtmdio_930x_read_sds_phy(sds_num, 0x1f, 11);
|
||||
pr_info("%s set medium: %08x\n", __func__, v);
|
||||
v |= BIT(1);
|
||||
rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
|
||||
rtmdio_930x_write_sds_phy(sds_num, 0x1f, 11, v);
|
||||
pr_info("%s set medium after: %08x\n", __func__, v);
|
||||
}
|
||||
|
||||
|
|
@ -2947,15 +2903,15 @@ static void rtl9300_serdes_patch(int sds_num)
|
|||
{
|
||||
if (sds_num % 2) {
|
||||
for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
|
||||
rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
|
||||
rtl9300_a_sds_10gr_lane1[i].reg,
|
||||
rtl9300_a_sds_10gr_lane1[i].data);
|
||||
rtmdio_930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
|
||||
rtl9300_a_sds_10gr_lane1[i].reg,
|
||||
rtl9300_a_sds_10gr_lane1[i].data);
|
||||
}
|
||||
} else {
|
||||
for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
|
||||
rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
|
||||
rtl9300_a_sds_10gr_lane0[i].reg,
|
||||
rtl9300_a_sds_10gr_lane0[i].data);
|
||||
rtmdio_930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
|
||||
rtl9300_a_sds_10gr_lane0[i].reg,
|
||||
rtl9300_a_sds_10gr_lane0[i].data);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -2975,7 +2931,7 @@ int rtl9300_sds_cmu_band_get(int sds)
|
|||
|
||||
en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
|
||||
if(!en) { /* Auto mode */
|
||||
rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
|
||||
rtmdio_930x_write_sds_phy(sds, 0x1f, 0x02, 31);
|
||||
|
||||
cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -57,8 +57,6 @@ struct __attribute__ ((__packed__)) fw_header {
|
|||
#define RTL839X_SDS12_13_XSG0 (0xB800)
|
||||
|
||||
/* Registers of the internal Serdes of the 9300 */
|
||||
#define RTL930X_SDS_INDACS_CMD (0x03B0)
|
||||
#define RTL930X_SDS_INDACS_DATA (0x03B4)
|
||||
#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
|
||||
|
||||
/* Registers of the internal SerDes of the 9310 */
|
||||
|
|
@ -69,8 +67,6 @@ struct __attribute__ ((__packed__)) fw_header {
|
|||
#define RTL931X_MAC_SERDES_MODE_CTRL(sds) (0x136C + (((sds) << 2)))
|
||||
|
||||
int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode);
|
||||
int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
|
||||
int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
|
||||
|
||||
int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg);
|
||||
int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue