forked from mirror/openwrt
uboot-lantiq: fix C-style comments in AWK scripts
Modern gawk rejects C-style /* ... */ comments in AWK code, treating
them as regex patterns where '*' has nothing to quantify. Replace all
such comments with AWK-style '#' comments in lantiq_bdi_conf.awk and
lantiq_ram_init_uart.awk.
Also replace the pattern 'if (x) /* comment */ else action' which used
a C comment as a null statement with the equivalent 'if (!x) action'.
Fixes build error:
awk: error: ? * + or {interval} not preceded by valid subpattern
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Link: https://github.com/openwrt/openwrt/pull/22458
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
parent
62ca0a987f
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1 changed files with 13 additions and 15 deletions
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@ -251,7 +251,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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+}
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+
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+/^#define/ {
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+ /* DC03 contains MC enable bit and must not be set here */
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+ # DC03 contains MC enable bit and must not be set here
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+ if (tolower($2) != "mc_dc03_value")
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+ printf("WM32 0x%x %s\n", reg_base, tolower($3))
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+
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@ -357,7 +357,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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+}
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--- /dev/null
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+++ b/tools/lantiq_ram_init_uart.awk
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@@ -0,0 +1,117 @@
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@@ -0,0 +1,115 @@
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+#!/usr/bin/awk -f
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+#
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+# Copyright (C) 2011-2012 Luka Perkov <luka@openwrt.org>
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@ -383,45 +383,45 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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+
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+function mc_danube_prologue()
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+{
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+ /* Clear access error log registers */
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+ # Clear access error log registers
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+ print "0xbf800010", "0x0"
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+ print "0xbf800020", "0x0"
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+
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+ /* Enable DDR and SRAM module in memory controller */
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+ # Enable DDR and SRAM module in memory controller
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+ print "0xbf800060", "0x5"
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+
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+ /* Clear start bit of DDR memory controller */
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+ # Clear start bit of DDR memory controller
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+ print "0xbf801030", "0x0"
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+}
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+
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+function mc_ar9_prologue()
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+{
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+ /* Clear access error log registers */
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+ # Clear access error log registers
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+ print "0xbf800010", "0x0"
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+ print "0xbf800020", "0x0"
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+
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+ /* Enable FPI, DDR and SRAM module in memory controller */
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+ # Enable FPI, DDR and SRAM module in memory controller
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+ print "0xbf800060", "0xD"
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+
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+ /* Clear start bit of DDR memory controller */
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+ # Clear start bit of DDR memory controller
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+ print "0xbf801030", "0x0"
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+}
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+
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+function mc_ddr1_epilogue()
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+{
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+ /* Set start bit of DDR memory controller */
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+ # Set start bit of DDR memory controller
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+ print "0xbf801030", "0x100"
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+}
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+
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+function mc_ddr2_prologue()
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+{
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+ /* Put memory controller in inactive mode */
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+ # Put memory controller in inactive mode
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+ print "0xbf401070", "0x0"
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+}
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+
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+function mc_ddr2_epilogue(mc_ccr07_value)
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+{
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+ /* Put memory controller in active mode */
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+ # Put memory controller in active mode
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+ mc_ccr07_value = or(mc_ccr07_value, 0x100)
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+ printf("0xbf401070 0x%x\n", mc_ccr07_value)
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+}
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@ -452,12 +452,10 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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+}
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+
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+/^#define/ {
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+ /* CCR07 contains MC enable bit and must not be set here */
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+ # CCR07 contains MC enable bit and must not be set here
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+ if (tolower($2) == "mc_ccr07_value")
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+ mc_ccr07_value = strtonum($3)
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+ if (tolower($2) == "mc_dc03_value")
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+ /* CCR07 contains MC enable bit and must not be set here */
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+ else
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+ if (tolower($2) != "mc_dc03_value")
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+ printf("0x%x %s\n", reg_base, tolower($3))
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+
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+ reg_base += 0x10
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