forked from mirror/openwrt
realtek: mdio: drop driver lock
The Realtek mdio driver does not need to track a separate lock. Rely on the default kernel mdio bus lock instead. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/21529 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Markus Stockhausen
Hauke Mehrtens
parent
5c0e415a4b
commit
48b4160329
1 changed files with 9 additions and 94 deletions
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@ -166,7 +166,6 @@
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* reimplemented. For now it should be sufficient.
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*/
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DEFINE_MUTEX(rtmdio_lock);
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struct rtmdio_bus_priv {
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const struct rtmdio_config *cfg;
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@ -229,16 +228,12 @@ static int rtmdio_838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
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u32 park_page = 0x1f;
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int err;
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mutex_lock(&rtmdio_lock);
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sw_w32_mask(0xffff0000, port << 16, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2);
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sw_w32(reg << 20 | page << 3 | park_page << 15, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1);
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err = rtmdio_838x_run_cmd(RTMDIO_838X_CMD_READ_C22);
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if (!err)
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*val = sw_r32(RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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@ -246,18 +241,12 @@ static int rtmdio_838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
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static int rtmdio_838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
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{
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u32 park_page = 0x1f;
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int err;
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mutex_lock(&rtmdio_lock);
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sw_w32(BIT(port), RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0);
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sw_w32_mask(0xffff0000, val << 16, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2);
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sw_w32(reg << 20 | page << 3 | park_page << 15, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1);
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err = rtmdio_838x_run_cmd(RTMDIO_838X_CMD_WRITE_C22);
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mutex_unlock(&rtmdio_lock);
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return err;
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return rtmdio_838x_run_cmd(RTMDIO_838X_CMD_WRITE_C22);
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}
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/* Read an mmd register of a PHY */
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@ -265,8 +254,6 @@ static int rtmdio_838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
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{
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int err;
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mutex_lock(&rtmdio_lock);
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sw_w32(1 << port, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0);
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sw_w32_mask(0xffff0000, port << 16, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2);
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sw_w32(addr << 16 | reg, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3);
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@ -274,27 +261,18 @@ static int rtmdio_838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
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if (!err)
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*val = sw_r32(RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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/* Write to an mmd register of a PHY */
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static int rtmdio_838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
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{
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int err;
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mutex_lock(&rtmdio_lock);
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sw_w32(1 << port, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0);
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sw_w32_mask(0xffff0000, val << 16, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2);
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sw_w32_mask(0x1f << 16, addr << 16, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3);
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sw_w32_mask(0xffff, reg, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3);
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err = rtmdio_838x_run_cmd(RTMDIO_838X_CMD_WRITE_C45);
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mutex_unlock(&rtmdio_lock);
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return err;
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return rtmdio_838x_run_cmd(RTMDIO_838X_CMD_WRITE_C45);
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}
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/* RTL839x specific MDIO functions */
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@ -310,8 +288,6 @@ static int rtmdio_839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
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int err;
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u32 v;
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mutex_lock(&rtmdio_lock);
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sw_w32_mask(0xffff0000, port << 16, RTMDIO_839X_PHYREG_DATA_CTRL);
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v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
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sw_w32(v, RTMDIO_839X_PHYREG_ACCESS_CTRL);
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@ -320,29 +296,21 @@ static int rtmdio_839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
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if (!err)
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*val = sw_r32(RTMDIO_839X_PHYREG_DATA_CTRL) & 0xffff;
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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static int rtmdio_839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
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{
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int err;
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u32 v;
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mutex_lock(&rtmdio_lock);
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sw_w32(BIT_ULL(port), RTMDIO_839X_PHYREG_PORT_CTRL);
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sw_w32(BIT_ULL(port) >> 32, RTMDIO_839X_PHYREG_PORT_CTRL + 4);
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sw_w32_mask(0xffff0000, val << 16, RTMDIO_839X_PHYREG_DATA_CTRL);
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v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
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sw_w32(v, RTMDIO_839X_PHYREG_ACCESS_CTRL);
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sw_w32(0x1ff, RTMDIO_839X_PHYREG_CTRL);
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err = rtmdio_839x_run_cmd(RTMDIO_839X_CMD_WRITE_C22);
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mutex_unlock(&rtmdio_lock);
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return err;
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return rtmdio_839x_run_cmd(RTMDIO_839X_CMD_WRITE_C22);
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}
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/* Read an mmd register of the PHY */
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@ -350,35 +318,24 @@ static int rtmdio_839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
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{
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int err;
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mutex_lock(&rtmdio_lock);
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sw_w32_mask(0xffff << 16, port << 16, RTMDIO_839X_PHYREG_DATA_CTRL);
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sw_w32(devnum << 16 | (regnum & 0xffff), RTMDIO_839X_PHYREG_MMD_CTRL);
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err = rtmdio_839x_run_cmd(RTMDIO_839X_CMD_READ_C45);
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if (!err)
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*val = sw_r32(RTMDIO_839X_PHYREG_DATA_CTRL) & 0xffff;
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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/* Write to an mmd register of the PHY */
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static int rtmdio_839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
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{
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int err;
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mutex_lock(&rtmdio_lock);
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sw_w32(BIT_ULL(port), RTMDIO_839X_PHYREG_PORT_CTRL);
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sw_w32(BIT_ULL(port) >> 32, RTMDIO_839X_PHYREG_PORT_CTRL + 4);
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sw_w32_mask(0xffff << 16, val << 16, RTMDIO_839X_PHYREG_DATA_CTRL);
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sw_w32(devnum << 16 | (regnum & 0xffff), RTMDIO_839X_PHYREG_MMD_CTRL);
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err = rtmdio_839x_run_cmd(RTMDIO_839X_CMD_WRITE_C45);
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mutex_unlock(&rtmdio_lock);
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return err;
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return rtmdio_839x_run_cmd(RTMDIO_839X_CMD_WRITE_C45);
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}
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/* RTL930x specific MDIO functions */
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@ -391,20 +348,14 @@ static int rtmdio_930x_run_cmd(int cmd)
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static int rtmdio_930x_write_phy(u32 port, u32 page, u32 reg, u32 val)
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{
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int err;
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u32 v;
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mutex_lock(&rtmdio_lock);
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sw_w32(BIT(port), RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0);
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sw_w32_mask(0xffff << 16, val << 16, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2);
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v = reg << 20 | page << 3 | 0x1f << 15 | BIT(2);
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sw_w32(v, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1);
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err = rtmdio_930x_run_cmd(RTMDIO_930X_CMD_WRITE_C22);
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mutex_unlock(&rtmdio_lock);
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return err;
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return rtmdio_930x_run_cmd(RTMDIO_930X_CMD_WRITE_C22);
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}
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static int rtmdio_930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
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@ -412,8 +363,6 @@ static int rtmdio_930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
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int err;
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u32 v;
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mutex_lock(&rtmdio_lock);
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sw_w32_mask(0xffff << 16, port << 16, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2);
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v = reg << 20 | page << 3 | 0x1f << 15;
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sw_w32(v, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1);
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@ -421,26 +370,17 @@ static int rtmdio_930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
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if (!err)
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*val = (sw_r32(RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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/* Write to an mmd register of the PHY */
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static int rtmdio_930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
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{
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int err;
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mutex_lock(&rtmdio_lock);
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sw_w32(BIT(port), RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0);
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sw_w32_mask(0xffff << 16, val << 16, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2);
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sw_w32(devnum << 16 | (regnum & 0xffff), RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3);
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err = rtmdio_930x_run_cmd(RTMDIO_930X_CMD_WRITE_C45);
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mutex_unlock(&rtmdio_lock);
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return err;
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return rtmdio_930x_run_cmd(RTMDIO_930X_CMD_WRITE_C45);
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}
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/* Read an mmd register of the PHY */
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@ -448,16 +388,12 @@ static int rtmdio_930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
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{
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int err ;
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mutex_lock(&rtmdio_lock);
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sw_w32_mask(0xffff << 16, port << 16, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2);
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sw_w32(devnum << 16 | (regnum & 0xffff), RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3);
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err = rtmdio_930x_run_cmd(RTMDIO_930X_CMD_READ_C45);
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if (!err)
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*val = (sw_r32(RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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@ -471,36 +407,26 @@ static int rtmdio_931x_run_cmd(int cmd)
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static int rtmdio_931x_write_phy(u32 port, u32 page, u32 reg, u32 val)
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{
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int err;
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mutex_lock(&rtmdio_lock);
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sw_w32(0, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2);
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sw_w32(0, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 + 4);
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sw_w32_mask(0, BIT(port % 32), RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 + (port / 32) * 4);
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sw_w32_mask(0xffff, val, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3);
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sw_w32(reg << 6 | page << 11, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0);
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sw_w32(0x1ff, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_1);
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err = rtmdio_931x_run_cmd(RTMDIO_931X_CMD_WRITE_C22);
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mutex_unlock(&rtmdio_lock);
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return err;
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return rtmdio_931x_run_cmd(RTMDIO_931X_CMD_WRITE_C22);
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}
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static int rtmdio_931x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
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{
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int err;
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mutex_lock(&rtmdio_lock);
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sw_w32(port << 5, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL);
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sw_w32(reg << 6 | page << 11, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0);
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err = rtmdio_931x_run_cmd(RTMDIO_931X_CMD_READ_C22);
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if (!err)
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*val = sw_r32(RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3) >> 16;
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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@ -509,37 +435,26 @@ static int rtmdio_931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
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{
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int err;
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mutex_lock(&rtmdio_lock);
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sw_w32(port << 5, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL);
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sw_w32(devnum << 16 | regnum, RTMDIO_931X_SMI_INDRT_ACCESS_MMD_CTRL);
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err = rtmdio_931x_run_cmd(RTMDIO_931X_CMD_READ_C45);
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if (!err)
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*val = sw_r32(RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3) >> 16;
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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/* Write to an mmd register of the PHY */
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static int rtmdio_931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
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{
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u64 mask;
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int err;
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u64 mask = BIT_ULL(port);
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mutex_lock(&rtmdio_lock);
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mask = BIT_ULL(port);
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sw_w32((u32)mask, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2);
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sw_w32((u32)(mask >> 32), RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 + 4);
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sw_w32_mask(0xffff, val, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3);
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sw_w32(devnum << 16 | regnum, RTMDIO_931X_SMI_INDRT_ACCESS_MMD_CTRL);
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err = rtmdio_931x_run_cmd(RTMDIO_931X_CMD_WRITE_C45);
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mutex_unlock(&rtmdio_lock);
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return err;
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return rtmdio_931x_run_cmd(RTMDIO_931X_CMD_WRITE_C45);
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}
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/* These are the core functions of our new Realtek SoC MDIO bus. */
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