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rockchip: backport dts updates for rk3576

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Backport core dts updates for rk3576.

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20041
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Tianling Shen 2025-09-13 19:49:35 +08:00 • committed by Hauke Mehrtens
parent 0a6ed6db26
commit 3a35a2cff1
27 changed files with 9845 additions and 0 deletions
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7486
target/linux/rockchip/patches-6.12/050-01-v6.13-arm64-dts-rockchip-Add-rk3576-SoC-base-DT.patch Normal file
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61
target/linux/rockchip/patches-6.12/050-02-v6.14-arm64-dts-rockchip-Add-rk3576-naneng-combphy-nodes.patch Normal file
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From ddbf63b25866a4a58222d763f9f2d29c309e00e8 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Tue, 7 Jan 2025 15:49:05 +0800
Subject: [PATCH] arm64: dts: rockchip: Add rk3576 naneng combphy nodes
rk3576 has two naneng combo phys:
- combophy0 is used for one of pcie and sata;
- combophy1 is used for one of pcie, sata and usb3;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Link: https://lore.kernel.org/r/20250107074911.550057-2-kever.yang@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++
1 file changed, 36 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1587,6 +1587,42 @@
status = "disabled";
};
+ combphy0_ps: phy@2b050000 {
+ compatible = "rockchip,rk3576-naneng-combphy";
+ reg = <0x0 0x2b050000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PCIE0_PHY>,
+ <&cru PCLK_PCIE2_COMBOPHY0>,
+ <&cru PCLK_PCIE0>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PCIE0_PIPE_PHY>,
+ <&cru SRST_P_PCIE2_COMBOPHY0>;
+ reset-names = "phy", "apb";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
+ status = "disabled";
+ };
+
+ combphy1_psu: phy@2b060000 {
+ compatible = "rockchip,rk3576-naneng-combphy";
+ reg = <0x0 0x2b060000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PCIE1_PHY>,
+ <&cru PCLK_PCIE2_COMBOPHY1>,
+ <&cru PCLK_PCIE1>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PCIE1_PIPE_PHY>,
+ <&cru SRST_P_PCIE2_COMBOPHY1>;
+ reset-names = "phy", "apb";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
+ status = "disabled";
+ };
+
sram: sram@3ff88000 {
compatible = "mmio-sram";
reg = <0x0 0x3ff88000 0x0 0x78000>;

171
target/linux/rockchip/patches-6.12/050-03-v6.14-arm64-dts-rockchip-add-usb-related-nodes-for-rk3576.patch Normal file
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From 23ec57a32da448cb3415d6abad3457b14c69af25 Mon Sep 17 00:00:00 2001
From: Frank Wang <frank.wang@rock-chips.com>
Date: Tue, 7 Jan 2025 15:49:08 +0800
Subject: [PATCH] arm64: dts: rockchip: add usb related nodes for rk3576
This adds USB and USB-PHY related nodes for RK3576 SoC.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Link: https://lore.kernel.org/r/20250107074911.550057-5-kever.yang@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 133 +++++++++++++++++++++++
1 file changed, 133 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -445,6 +445,58 @@
#size-cells = <2>;
ranges;
+ usb_drd0_dwc3: usb@23000000 {
+ compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
+ reg = <0x0 0x23000000 0x0 0x400000>;
+ clocks = <&cru CLK_REF_USB3OTG0>,
+ <&cru CLK_SUSPEND_USB3OTG0>,
+ <&cru ACLK_USB3OTG0>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3576_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG0>;
+ dr_mode = "otg";
+ phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,parkmode-disable-hs-quirk;
+ snps,parkmode-disable-ss-quirk;
+ status = "disabled";
+ };
+
+ usb_drd1_dwc3: usb@23400000 {
+ compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
+ reg = <0x0 0x23400000 0x0 0x400000>;
+ clocks = <&cru CLK_REF_USB3OTG1>,
+ <&cru CLK_SUSPEND_USB3OTG1>,
+ <&cru ACLK_USB3OTG1>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3576_PD_PHP>;
+ resets = <&cru SRST_A_USB3OTG1>;
+ dr_mode = "otg";
+ phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,dis_rxdet_inp3_quirk;
+ snps,parkmode-disable-hs-quirk;
+ snps,parkmode-disable-ss-quirk;
+ dma-coherent;
+ status = "disabled";
+ };
+
sys_grf: syscon@2600a000 {
compatible = "rockchip,rk3576-sys-grf", "syscon";
reg = <0x0 0x2600a000 0x0 0x2000>;
@@ -515,6 +567,65 @@
reg = <0x0 0x2602c000 0x0 0x2000>;
};
+ usb2phy_grf: syscon@2602e000 {
+ compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0x2602e000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy0: usb2-phy@0 {
+ compatible = "rockchip,rk3576-usb2phy";
+ reg = <0x0 0x10>;
+ resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>;
+ reset-names = "phy", "apb";
+ clocks = <&cru CLK_PHY_REF_SRC>,
+ <&cru ACLK_MMU2>,
+ <&cru ACLK_SLV_MMU2>;
+ clock-names = "phyclk", "aclk", "aclk_slv";
+ clock-output-names = "usb480m_phy0";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id", "linestate";
+ status = "disabled";
+ };
+ };
+
+ u2phy1: usb2-phy@2000 {
+ compatible = "rockchip,rk3576-usb2phy";
+ reg = <0x2000 0x10>;
+ resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>;
+ reset-names = "phy", "apb";
+ clocks = <&cru CLK_PHY_REF_SRC>,
+ <&cru ACLK_MMU1>,
+ <&cru ACLK_SLV_MMU1>;
+ clock-names = "phyclk", "aclk", "aclk_slv";
+ clock-output-names = "usb480m_phy1";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id", "linestate";
+ status = "disabled";
+ };
+ };
+ };
+
+ vo1_grf: syscon@26036000 {
+ compatible = "rockchip,rk3576-vo1-grf", "syscon";
+ reg = <0x0 0x26036000 0x0 0x100>;
+ clocks = <&cru PCLK_VO1_ROOT>;
+ };
+
sdgmac_grf: syscon@26038000 {
compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
reg = <0x0 0x26038000 0x0 0x1000>;
@@ -1623,6 +1734,28 @@
status = "disabled";
};
+ usbdp_phy: phy@2b010000 {
+ compatible = "rockchip,rk3576-usbdp-phy";
+ reg = <0x0 0x2b010000 0x0 0x10000>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_PHY_REF_SRC >,
+ <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>,
+ <&cru PCLK_USBDPPHY>,
+ <&u2phy0>;
+ clock-names = "refclk", "immortal", "pclk", "utmi";
+ resets = <&cru SRST_USBDP_COMBO_PHY_INIT>,
+ <&cru SRST_USBDP_COMBO_PHY_CMN>,
+ <&cru SRST_USBDP_COMBO_PHY_LANE>,
+ <&cru SRST_USBDP_COMBO_PHY_PCS>,
+ <&cru SRST_P_USBDPPHY>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy_grf>;
+ rockchip,vo-grf = <&vo1_grf>;
+ status = "disabled";
+ };
+
sram: sram@3ff88000 {
compatible = "mmio-sram";
reg = <0x0 0x3ff88000 0x0 0x78000>;

63
target/linux/rockchip/patches-6.12/050-04-v6.15-arm64-dts-rockchip-add-rk3576-otp-node.patch Normal file
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@ -0,0 +1,63 @@
From 8715d2eeb062f6859c252bb6c87b363230b66e9f Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Mon, 10 Feb 2025 23:45:10 +0100
Subject: [PATCH] arm64: dts: rockchip: add rk3576 otp node
This adds the otp node to the rk3576 soc devicetree including the
individual fields we know about.
Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250210224510.1194963-7-heiko@sntech.de
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 39 ++++++++++++++++++++++++
1 file changed, 39 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1260,6 +1260,45 @@
status = "disabled";
};
+ otp: otp@2a580000 {
+ compatible = "rockchip,rk3576-otp";
+ reg = <0x0 0x2a580000 0x0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+ <&cru CLK_OTP_PHY_G>;
+ clock-names = "otp", "apb_pclk", "phy";
+ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>;
+ reset-names = "otp", "apb";
+
+ /* Data cells */
+ cpu_code: cpu-code@2 {
+ reg = <0x02 0x2>;
+ };
+ otp_cpu_version: cpu-version@5 {
+ reg = <0x05 0x1>;
+ bits = <3 3>;
+ };
+ otp_id: id@a {
+ reg = <0x0a 0x10>;
+ };
+ cpub_leakage: cpub-leakage@1e {
+ reg = <0x1e 0x1>;
+ };
+ cpul_leakage: cpul-leakage@1f {
+ reg = <0x1f 0x1>;
+ };
+ npu_leakage: npu-leakage@20 {
+ reg = <0x20 0x1>;
+ };
+ gpu_leakage: gpu-leakage@21 {
+ reg = <0x21 0x1>;
+ };
+ log_leakage: log-leakage@22 {
+ reg = <0x22 0x1>;
+ };
+ };
+
gic: interrupt-controller@2a701000 {
compatible = "arm,gic-400";
reg = <0x0 0x2a701000 0 0x10000>,

48
target/linux/rockchip/patches-6.12/050-05-v6.15-scsi-arm64-dts-rockchip-Add-UFS-support-for-RK3576-SoC.patch Normal file
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@ -0,0 +1,48 @@
From c75e5e010fef2a62e6f2fe00ee8584e7b3ec82a6 Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Wed, 5 Feb 2025 14:15:56 +0800
Subject: [PATCH] scsi: arm64: dts: rockchip: Add UFS support for RK3576 SoC
Add ufshc node to rk3576.dtsi, so the board using UFS could enable it.
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://lore.kernel.org/r/1738736156-119203-8-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1221,6 +1221,30 @@
};
};
+ ufshc: ufshc@2a2d0000 {
+ compatible = "rockchip,rk3576-ufshc";
+ reg = <0x0 0x2a2d0000 0x0 0x10000>,
+ <0x0 0x2b040000 0x0 0x10000>,
+ <0x0 0x2601f000 0x0 0x1000>,
+ <0x0 0x2603c000 0x0 0x1000>,
+ <0x0 0x2a2e0000 0x0 0x10000>;
+ reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
+ clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>,
+ <&cru CLK_REF_UFS_CLKOUT>;
+ clock-names = "core", "pclk", "pclk_mphy", "ref_out";
+ assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
+ assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3576_PD_USB>;
+ pinctrl-0 = <&ufs_refclk>;
+ pinctrl-names = "default";
+ resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>,
+ <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>;
+ reset-names = "biu", "sys", "ufs", "grf";
+ reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+ };
+
sdmmc: mmc@2a310000 {
compatible = "rockchip,rk3576-dw-mshc";
reg = <0x0 0x2a310000 0x0 0x4000>;

98
target/linux/rockchip/patches-6.12/050-06-v6.15-arm64-dts-rockchip-Add-vop-for-rk3576.patch Normal file
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@ -0,0 +1,98 @@
From d74b842cab0860e41a45df0dac41e4e56202c766 Mon Sep 17 00:00:00 2001
From: Andy Yan <andy.yan@rock-chips.com>
Date: Tue, 31 Dec 2024 17:57:18 +0800
Subject: [PATCH] arm64: dts: rockchip: Add vop for rk3576
Add VOP and VOP_MMU found on rk3576.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20241231095728.253943-2-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 68 ++++++++++++++++++++++++
1 file changed, 68 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -393,6 +393,11 @@
};
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
+
firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
@@ -937,6 +942,69 @@
status = "disabled";
};
+ vop: vop@27d00000 {
+ compatible = "rockchip,rk3576-vop";
+ reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
+ reg-names = "vop", "gamma-lut";
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys",
+ "vp0",
+ "vp1",
+ "vp2";
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VP0>,
+ <&cru DCLK_VP1>,
+ <&cru DCLK_VP2>;
+ clock-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2";
+ iommus = <&vop_mmu>;
+ power-domains = <&power RK3576_PD_VOP>;
+ rockchip,grf = <&sys_grf>;
+ rockchip,pmu = <&pmu>;
+ status = "disabled";
+
+ vop_out: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vp0: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ vp1: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ vp2: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ };
+ };
+
+ vop_mmu: iommu@27d07e00 {
+ compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>;
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3576_PD_VOP>;
+ status = "disabled";
+ };
+
qos_hdcp1: qos@27f02000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f02000 0x0 0x20>;

95
target/linux/rockchip/patches-6.12/050-07-v6.15-arm64-dts-rockchip-Add-hdmi-for-rk3576.patch Normal file
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@ -0,0 +1,95 @@
From ad0ea230ab2a3535b186f7fb863b4bca7050e06f Mon Sep 17 00:00:00 2001
From: Andy Yan <andy.yan@rock-chips.com>
Date: Tue, 31 Dec 2024 17:57:19 +0800
Subject: [PATCH] arm64: dts: rockchip: Add hdmi for rk3576
Add hdmi and it's phy dt node for rk3576.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20241231095728.253943-3-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -625,6 +625,11 @@
};
};
+ hdptxphy_grf: syscon@26032000 {
+ compatible = "rockchip,rk3576-hdptxphy-grf", "syscon";
+ reg = <0x0 0x26032000 0x0 0x100>;
+ };
+
vo1_grf: syscon@26036000 {
compatible = "rockchip,rk3576-vo1-grf", "syscon";
reg = <0x0 0x26036000 0x0 0x100>;
@@ -1005,6 +1010,46 @@
status = "disabled";
};
+ hdmi: hdmi@27da0000 {
+ compatible = "rockchip,rk3576-dw-hdmi-qp";
+ reg = <0x0 0x27da0000 0x0 0x20000>;
+ clocks = <&cru PCLK_HDMITX0>,
+ <&cru CLK_HDMITX0_EARC>,
+ <&cru CLK_HDMITX0_REF>,
+ <&cru MCLK_SAI6_8CH>,
+ <&cru CLK_HDMITXHDP>,
+ <&cru HCLK_VO0_ROOT>;
+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
+ phys = <&hdptxphy>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>;
+ power-domains = <&power RK3576_PD_VO0>;
+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>;
+ reset-names = "ref", "hdp";
+ rockchip,grf = <&ioc_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
qos_hdcp1: qos@27f02000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f02000 0x0 0x20>;
@@ -1887,6 +1932,19 @@
status = "disabled";
};
+ hdptxphy: hdmiphy@2b000000 {
+ compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy";
+ reg = <0x0 0x2b000000 0x0 0x2000>;
+ clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>;
+ clock-names = "ref", "apb";
+ resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
+ <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
+ reset-names = "apb", "init", "cmn", "lane";
+ rockchip,grf = <&hdptxphy_grf>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
sram: sram@3ff88000 {
compatible = "mmio-sram";
reg = <0x0 0x3ff88000 0x0 0x78000>;

52
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From 36299757129c897ef8c7ace6981070d367d89f89 Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Fri, 28 Feb 2025 09:50:47 -0500
Subject: [PATCH] arm64: dts: rockchip: Add SFC nodes for rk3576
The rk3576 SoC has 2 SFC cores that provide FSPI functions.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Link: https://lore.kernel.org/r/20250228145304.581349-2-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1358,6 +1358,17 @@
status = "disabled";
};
+ sfc1: spi@2a300000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0x2a300000 0x0 0x4000>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sdmmc: mmc@2a310000 {
compatible = "rockchip,rk3576-dw-mshc";
reg = <0x0 0x2a310000 0x0 0x4000>;
@@ -1397,6 +1408,17 @@
status = "disabled";
};
+ sfc0: spi@2a340000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0x2a340000 0x0 0x4000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
otp: otp@2a580000 {
compatible = "rockchip,rk3576-otp";
reg = <0x0 0x2a580000 0x0 0x400>;

109
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From b5cb721adbe8b6c7a8e3b178fa0feb283f4a660a Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Mon, 10 Mar 2025 10:59:57 +0100
Subject: [PATCH] arm64: dts: rockchip: fix RK3576 SCMI clock IDs
Downstream Linux, and consequently both downstream and mainline TF-A,
all use a different set of clock IDs from mainline Linux. If we want to
fiddle with these clocks through SCMI, we'll need to use the right IDs.
If we don't do this we'll end up changing unrelated clocks all over the
place.
Change the clock IDs to the newly added SCMI clock IDs for the CPU and
GPU nodes, which are currently the only ones using SCMI clocks. This
fixes the terrible GPU performance, as we weren't reclocking it
properly.
Fixes: 57b1ce903966 ("arm64: dts: rockchip: Add rk3576 SoC base DT")
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Closes: https://libera.irclog.whitequark.org/linux-rockchip/2025-03-09#1741542223-1741542875;
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250310-rk3576-scmi-clocks-v1-2-e165deb034e8@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -111,7 +111,7 @@
reg = <0x0>;
enable-method = "psci";
capacity-dmips-mhz = <485>;
- clocks = <&scmi_clk ARMCLK_L>;
+ clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
#cooling-cells = <2>;
dynamic-power-coefficient = <120>;
@@ -124,7 +124,7 @@
reg = <0x1>;
enable-method = "psci";
capacity-dmips-mhz = <485>;
- clocks = <&scmi_clk ARMCLK_L>;
+ clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
@@ -135,7 +135,7 @@
reg = <0x2>;
enable-method = "psci";
capacity-dmips-mhz = <485>;
- clocks = <&scmi_clk ARMCLK_L>;
+ clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
@@ -146,7 +146,7 @@
reg = <0x3>;
enable-method = "psci";
capacity-dmips-mhz = <485>;
- clocks = <&scmi_clk ARMCLK_L>;
+ clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
@@ -157,7 +157,7 @@
reg = <0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk ARMCLK_B>;
+ clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
#cooling-cells = <2>;
dynamic-power-coefficient = <320>;
@@ -170,7 +170,7 @@
reg = <0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk ARMCLK_B>;
+ clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
@@ -181,7 +181,7 @@
reg = <0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk ARMCLK_B>;
+ clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
@@ -192,7 +192,7 @@
reg = <0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk ARMCLK_B>;
+ clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
@@ -932,7 +932,7 @@
gpu: gpu@27800000 {
compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
reg = <0x0 0x27800000 0x0 0x200000>;
- assigned-clocks = <&scmi_clk CLK_GPU>;
+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
assigned-clock-rates = <198000000>;
clocks = <&cru CLK_GPU>;
clock-names = "core";

135
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@ -0,0 +1,135 @@
From d4b9fc2af45d2b91b1654c4aaa1edcb4dd8f4918 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Mon, 14 Apr 2025 22:51:10 +0800
Subject: [PATCH] arm64: dts: rockchip: Add rk3576 pcie nodes
rk3576 has two pcie controllers, both are pcie2x1 work with
naneng-combphy.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Shawn Lin <Shawn.lin@rock-chips.com>
Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250414145110.11275-3-kever.yang@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 108 +++++++++++++++++++++++
1 file changed, 108 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1240,6 +1240,114 @@
reg = <0x0 0x27f22100 0x0 0x20>;
};
+ pcie0: pcie@2a200000 {
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+ reg = <0x0 0x22000000 0x0 0x00400000>,
+ <0x0 0x2a200000 0x0 0x00010000>,
+ <0x0 0x20000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x0 0xf>;
+ clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
+ <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
+ <&cru CLK_PCIE0_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ num-lanes = <1>;
+ phys = <&combphy0_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3576_PD_PHP>;
+ ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
+ 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
+ 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pwr", "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie0_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ pcie1: pcie@2a210000 {
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+ reg = <0x0 0x22400000 0x0 0x00400000>,
+ <0x0 0x2a210000 0x0 0x00010000>,
+ <0x0 0x21000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x20 0x2f>;
+ clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
+ <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
+ <&cru CLK_PCIE1_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ num-lanes = <1>;
+ phys = <&combphy1_psu PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3576_PD_SUBPHP>;
+ ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
+ 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
+ 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+ reset-names = "pwr", "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
gmac0: ethernet@2a220000 {
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
reg = <0x0 0x2a220000 0x0 0x10000>;

60
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@ -0,0 +1,60 @@
From 24d8127d801560c8fa811d554e8ab5db7e51511c Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Thu, 24 Apr 2025 20:52:23 +0200
Subject: [PATCH] arm64: dts: rockchip: add SATA nodes to RK3576
The Rockchip RK3576 features two SATA nodes. The first, sata0, is behind
combphy0, which muxes between pcie0 and sata0.
The second, sata1, is behind combphy1, which muxes between pcie1, sata1
and usb_drd1_dwc3.
I've only been able to test sata0 on my board, but it appears to work
just fine.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250424-rk3576-sata-v1-2-23ee89c939fe@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 30 ++++++++++++++++++++++++
1 file changed, 30 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1442,6 +1442,36 @@
};
};
+ sata0: sata@2a240000 {
+ compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
+ reg = <0x0 0x2a240000 0x0 0x1000>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
+ <&cru CLK_RXOOB0>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3576_PD_SUBPHP>;
+ phys = <&combphy0_ps PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata1: sata@2a250000 {
+ compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
+ reg = <0x0 0x2a250000 0x0 0x1000>;
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
+ <&cru CLK_RXOOB1>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3576_PD_SUBPHP>;
+ phys = <&combphy1_psu PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ dma-coherent;
+ status = "disabled";
+ };
+
ufshc: ufshc@2a2d0000 {
compatible = "rockchip,rk3576-ufshc";
reg = <0x0 0x2a2d0000 0x0 0x10000>,

33
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@ -0,0 +1,33 @@
From 5268f3b5d29887480011b44567bcbf0d422cda94 Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Wed, 30 Apr 2025 18:16:36 +0200
Subject: [PATCH] arm64: dts: rockchip: add RK3576 RNG node
The RK3576 has a hardware random number generator IP built into the SoC.
Add it to the SoC's .dtsi, now that there's a binding and driver for it.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250430-rk3576-hwrng-v1-3-480c15b5843e@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1557,6 +1557,14 @@
status = "disabled";
};
+ rng: rng@2a410000 {
+ compatible = "rockchip,rk3576-rng";
+ reg = <0x0 0x2a410000 0x0 0x200>;
+ clocks = <&cru HCLK_TRNG_NS>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_H_TRNG_NS>;
+ };
+
otp: otp@2a580000 {
compatible = "rockchip,rk3576-otp";
reg = <0x0 0x2a580000 0x0 0x400>;

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@ -0,0 +1,243 @@
From 3dfeccdd3cc88792e631539792a1ecc37a9581dc Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Tue, 6 May 2025 12:42:40 +0200
Subject: [PATCH] arm64: dts: rockchip: Add RK3576 SAI nodes
The RK3576 SoC has 10 SAI controllers in total. Five of them are in the
video output power domains, and are used for digital audio output along
with the video signal of those, e.g. HDMI audio.
The other five, SAI0 through SAI4, are exposed externally. SAI0 and SAI1
are capable of 8-channel audio, whereas SAI2, SAI3 and SAI4 are limited
to two channels. These five are in the audio power domain.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-1-a8b5f5733ceb@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 200 +++++++++++++++++++++++
1 file changed, 200 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1010,6 +1010,41 @@
status = "disabled";
};
+ sai5: sai@27d40000 {
+ compatible = "rockchip,rk3576-sai";
+ reg = <0x0 0x27d40000 0x0 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac2 3>;
+ dma-names = "rx";
+ power-domains = <&power RK3576_PD_VO0>;
+ resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>;
+ reset-names = "m", "h";
+ rockchip,sai-rx-route = <0 1 2 3>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SAI5";
+ status = "disabled";
+ };
+
+ sai6: sai@27d50000 {
+ compatible = "rockchip,rk3576-sai";
+ reg = <0x0 0x27d50000 0x0 0x1000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac2 4>, <&dmac2 5>;
+ dma-names = "tx", "rx";
+ power-domains = <&power RK3576_PD_VO0>;
+ resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>;
+ reset-names = "m", "h";
+ rockchip,sai-rx-route = <0 1 2 3>;
+ rockchip,sai-tx-route = <0 1 2 3>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SAI6";
+ status = "disabled";
+ };
+
hdmi: hdmi@27da0000 {
compatible = "rockchip,rk3576-dw-hdmi-qp";
reg = <0x0 0x27da0000 0x0 0x20000>;
@@ -1050,6 +1085,57 @@
};
};
+ sai7: sai@27ed0000 {
+ compatible = "rockchip,rk3576-sai";
+ reg = <0x0 0x27ed0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac2 19>;
+ dma-names = "tx";
+ power-domains = <&power RK3576_PD_VO1>;
+ resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>;
+ reset-names = "m", "h";
+ rockchip,sai-tx-route = <0 1 2 3>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SAI7";
+ status = "disabled";
+ };
+
+ sai8: sai@27ee0000 {
+ compatible = "rockchip,rk3576-sai";
+ reg = <0x0 0x27ee0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac1 7>;
+ dma-names = "tx";
+ power-domains = <&power RK3576_PD_VO1>;
+ resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>;
+ reset-names = "m", "h";
+ rockchip,sai-tx-route = <0 1 2 3>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SAI8";
+ status = "disabled";
+ };
+
+ sai9: sai@27ef0000 {
+ compatible = "rockchip,rk3576-sai";
+ reg = <0x0 0x27ef0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac0 26>;
+ dma-names = "tx";
+ power-domains = <&power RK3576_PD_VO1>;
+ resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>;
+ reset-names = "m", "h";
+ rockchip,sai-tx-route = <0 1 2 3>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SAI9";
+ status = "disabled";
+ };
+
qos_hdcp1: qos@27f02000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f02000 0x0 0x20>;
@@ -1604,6 +1690,120 @@
};
};
+ sai0: sai@2a600000 {
+ compatible = "rockchip,rk3576-sai";
+ reg = <0x0 0x2a600000 0x0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac0 0>, <&dmac0 1>;
+ dma-names = "tx", "rx";
+ power-domains = <&power RK3576_PD_AUDIO>;
+ resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>;
+ reset-names = "m", "h";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sai0m0_lrck
+ &sai0m0_sclk
+ &sai0m0_sdi0
+ &sai0m0_sdi1
+ &sai0m0_sdi2
+ &sai0m0_sdi3
+ &sai0m0_sdo0
+ &sai0m0_sdo1
+ &sai0m0_sdo2
+ &sai0m0_sdo3>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SAI0";
+ status = "disabled";
+ };
+
+ sai1: sai@2a610000 {
+ compatible = "rockchip,rk3576-sai";
+ reg = <0x0 0x2a610000 0x0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac0 2>, <&dmac0 3>;
+ dma-names = "tx", "rx";
+ power-domains = <&power RK3576_PD_AUDIO>;
+ resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>;
+ reset-names = "m", "h";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sai1m0_lrck
+ &sai1m0_sclk
+ &sai1m0_sdi0
+ &sai1m0_sdo0
+ &sai1m0_sdo1
+ &sai1m0_sdo2
+ &sai1m0_sdo3>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SAI1";
+ status = "disabled";
+ };
+
+ sai2: sai@2a620000 {
+ compatible = "rockchip,rk3576-sai";
+ reg = <0x0 0x2a620000 0x0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac1 0>, <&dmac1 1>;
+ dma-names = "tx", "rx";
+ power-domains = <&power RK3576_PD_AUDIO>;
+ resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>;
+ reset-names = "m", "h";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sai2m0_lrck
+ &sai2m0_sclk
+ &sai2m0_sdi
+ &sai2m0_sdo>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SAI2";
+ status = "disabled";
+ };
+
+ sai3: sai@2a630000 {
+ compatible = "rockchip,rk3576-sai";
+ reg = <0x0 0x2a630000 0x0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac1 2>, <&dmac1 3>;
+ dma-names = "tx", "rx";
+ power-domains = <&power RK3576_PD_AUDIO>;
+ resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>;
+ reset-names = "m", "h";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sai3m0_lrck
+ &sai3m0_sclk
+ &sai3m0_sdi
+ &sai3m0_sdo>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SAI3";
+ status = "disabled";
+ };
+
+ sai4: sai@2a640000 {
+ compatible = "rockchip,rk3576-sai";
+ reg = <0x0 0x2a640000 0x0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac2 0>, <&dmac2 1>;
+ dma-names = "tx", "rx";
+ power-domains = <&power RK3576_PD_AUDIO>;
+ resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>;
+ reset-names = "m", "h";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sai4m0_lrck
+ &sai4m0_sclk
+ &sai4m0_sdi
+ &sai4m0_sdo>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SAI4";
+ status = "disabled";
+ };
+
gic: interrupt-controller@2a701000 {
compatible = "arm,gic-400";
reg = <0x0 0x2a701000 0 0x10000>,

50
target/linux/rockchip/patches-6.12/050-14-v6.16-arm64-dts-rockchip-Add-RK3576-HDMI-audio.patch Normal file
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@ -0,0 +1,50 @@
From 7f1561d82e3d3589038782f75faa50c65d9cdd42 Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Tue, 6 May 2025 12:42:41 +0200
Subject: [PATCH] arm64: dts: rockchip: Add RK3576 HDMI audio
The RK3576 SoC now has upstream support for HDMI.
Add an HDMI audio node, which uses SAI6 as its audio controller
according to downstream.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-2-a8b5f5733ceb@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -413,6 +413,22 @@
};
};
+ hdmi_sound: hdmi-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "HDMI";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ status = "disabled";
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai6>;
+ };
+ };
+
pmu_a53: pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
@@ -1069,6 +1085,7 @@
reset-names = "ref", "hdp";
rockchip,grf = <&ioc_grf>;
rockchip,vo-grf = <&vo0_grf>;
+ #sound-dai-cells = <0>;
status = "disabled";
ports {

39
target/linux/rockchip/patches-6.12/050-15-v6.16-arm64-dts-rockchip-Add-missing-SFC-power-domains-to-rk357.patch Normal file
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@ -0,0 +1,39 @@
From ede1fa1384c230c9823f6bf1849cf50c5fc8a83e Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 20 May 2025 13:14:27 +0200
Subject: [PATCH] arm64: dts: rockchip: Add missing SFC power-domains to rk3576
Add the power-domains for the RK3576 SFC nodes according to the
TRM part 1. This fixes potential SErrors when accessing the SFC
registers without other peripherals (e.g. eMMC) doing a prior
power-domain enable. For example this is easy to trigger on the
Rock 4D, which enables the SFC0 interface, but does not enable
the eMMC interface at the moment.
Cc: stable@vger.kernel.org
Fixes: 36299757129c8 ("arm64: dts: rockchip: Add SFC nodes for rk3576")
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250520-rk3576-fix-fspi-pmdomain-v1-1-f07c6e62dadd@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1605,6 +1605,7 @@
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>;
clock-names = "clk_sfc", "hclk_sfc";
+ power-domains = <&power RK3576_PD_SDGMAC>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1655,6 +1656,7 @@
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>;
clock-names = "clk_sfc", "hclk_sfc";
+ power-domains = <&power RK3576_PD_NVM>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";

257
target/linux/rockchip/patches-6.12/050-16-v6.16-arm64-dts-rockchip-fix-rk3576-pcie-unit-addresses.patch Normal file
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@ -0,0 +1,257 @@
From 4d2587e0e1ce7145a38802fa281f4f1f411ec56f Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Mon, 19 May 2025 00:04:43 +0200
Subject: [PATCH] arm64: dts: rockchip: fix rk3576 pcie unit addresses
The rk3576 pcie nodes currently use the apb register as their unit address
which is the second reg area defined in the binding.
As can be seen by the dtc warnings like
../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1346.24-1398.5: Warning (simple_bus_reg): /soc/pcie@2a200000: simple-bus unit address format error, expected "22000000"
../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1400.24-1452.5: Warning (simple_bus_reg): /soc/pcie@2a210000: simple-bus unit address format error, expected "22400000"
using the first reg area as the unit address seems to be preferred.
This is the dbi area per the binding, so adapt the unit address accordingly
and move the nodes to their new position.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250518220449.2722673-2-heiko@sntech.de
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 216 +++++++++++------------
1 file changed, 108 insertions(+), 108 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -466,6 +466,114 @@
#size-cells = <2>;
ranges;
+ pcie0: pcie@22000000 {
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+ reg = <0x0 0x22000000 0x0 0x00400000>,
+ <0x0 0x2a200000 0x0 0x00010000>,
+ <0x0 0x20000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x0 0xf>;
+ clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
+ <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
+ <&cru CLK_PCIE0_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ num-lanes = <1>;
+ phys = <&combphy0_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3576_PD_PHP>;
+ ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
+ 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
+ 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pwr", "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie0_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ pcie1: pcie@22400000 {
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+ reg = <0x0 0x22400000 0x0 0x00400000>,
+ <0x0 0x2a210000 0x0 0x00010000>,
+ <0x0 0x21000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x20 0x2f>;
+ clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
+ <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
+ <&cru CLK_PCIE1_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ num-lanes = <1>;
+ phys = <&combphy1_psu PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3576_PD_SUBPHP>;
+ ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
+ 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
+ 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+ reset-names = "pwr", "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
usb_drd0_dwc3: usb@23000000 {
compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
reg = <0x0 0x23000000 0x0 0x400000>;
@@ -1343,114 +1451,6 @@
reg = <0x0 0x27f22100 0x0 0x20>;
};
- pcie0: pcie@2a200000 {
- compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
- reg = <0x0 0x22000000 0x0 0x00400000>,
- <0x0 0x2a200000 0x0 0x00010000>,
- <0x0 0x20000000 0x0 0x00100000>;
- reg-names = "dbi", "apb", "config";
- bus-range = <0x0 0xf>;
- clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
- <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
- <&cru CLK_PCIE0_AUX>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux";
- device_type = "pci";
- interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie0_intc 0>,
- <0 0 0 2 &pcie0_intc 1>,
- <0 0 0 3 &pcie0_intc 2>,
- <0 0 0 4 &pcie0_intc 3>;
- linux,pci-domain = <0>;
- max-link-speed = <2>;
- num-ib-windows = <8>;
- num-viewport = <8>;
- num-ob-windows = <2>;
- num-lanes = <1>;
- phys = <&combphy0_ps PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3576_PD_PHP>;
- ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
- 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
- 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
- resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
- reset-names = "pwr", "pipe";
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie0_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- pcie1: pcie@2a210000 {
- compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
- reg = <0x0 0x22400000 0x0 0x00400000>,
- <0x0 0x2a210000 0x0 0x00010000>,
- <0x0 0x21000000 0x0 0x00100000>;
- reg-names = "dbi", "apb", "config";
- bus-range = <0x20 0x2f>;
- clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
- <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
- <&cru CLK_PCIE1_AUX>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux";
- device_type = "pci";
- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie1_intc 0>,
- <0 0 0 2 &pcie1_intc 1>,
- <0 0 0 3 &pcie1_intc 2>,
- <0 0 0 4 &pcie1_intc 3>;
- linux,pci-domain = <0>;
- max-link-speed = <2>;
- num-ib-windows = <8>;
- num-viewport = <8>;
- num-ob-windows = <2>;
- num-lanes = <1>;
- phys = <&combphy1_psu PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3576_PD_SUBPHP>;
- ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
- 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
- 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
- resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
- reset-names = "pwr", "pipe";
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie1_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
gmac0: ethernet@2a220000 {
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
reg = <0x0 0x2a220000 0x0 0x10000>;

173
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@ -0,0 +1,173 @@
From 8ff721f60257d550daf524fc559c0f0d2176b198 Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Mon, 19 May 2025 00:04:44 +0200
Subject: [PATCH] arm64: dts: rockchip: move rk3576 pinctrl node outside the
soc node
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
as dtc points out:
../arch/arm64/boot/dts/rockchip/rk3576.dtsi:2351.20-2417.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property
Move the pinctrl node outside and adapt the indentation.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250518220449.2722673-3-heiko@sntech.de
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 136 +++++++++++------------
1 file changed, 68 insertions(+), 68 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -429,6 +429,74 @@
};
};
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3576-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@27320000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x27320000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2ae10000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae10000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2ae20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae20000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2ae30000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae30000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@2ae40000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae40000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+ };
+
pmu_a53: pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
@@ -2349,74 +2417,6 @@
compatible = "arm,scmi-shmem";
reg = <0x0 0x4010f000 0x0 0x100>;
};
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3576-pinctrl";
- rockchip,grf = <&ioc_grf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@27320000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x27320000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 32>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@2ae10000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae10000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 32 32>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@2ae20000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae20000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 64 32>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@2ae30000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae30000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 96 32>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@2ae40000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae40000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 128 32>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
- };
};
};

24
target/linux/rockchip/patches-6.12/050-18-v6.16-arm64-dts-rockchip-remove-a-double-empty-line-from-rk3576.patch Normal file
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@ -0,0 +1,24 @@
From f8b11d8cfbfc8a0232c1e7cc6af10583c8bdb3f1 Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Mon, 19 May 2025 00:04:45 +0200
Subject: [PATCH] arm64: dts: rockchip: remove a double-empty line from rk3576
core dtsi
Two empty lines between nodes, is one too many.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250518220449.2722673-4-heiko@sntech.de
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 -
1 file changed, 1 deletion(-)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -2002,7 +2002,6 @@
status = "disabled";
};
-
i2c6: i2c@2ac90000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2ac90000 0x0 0x1000>;

32
target/linux/rockchip/patches-6.12/050-19-v6.16-arm64-dts-rockchip-fix-rk3576-pcie1-linux-pci-domain.patch Normal file
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@ -0,0 +1,32 @@
From af0f43d5d0d6e486b6a83190000dfa7ad447f825 Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Tue, 3 Jun 2025 10:35:40 +0800
Subject: [PATCH] arm64: dts: rockchip: fix rk3576 pcie1 linux,pci-domain
pcie0 already used 0 as its pci-domain, so pcie1 will fail to
allocate the same pci-domain if both of them are used.
rk-pcie 2a210000.pcie: PCIe Link up, LTSSM is 0x130011
rk-pcie 2a210000.pcie: PCIe Gen.2 x1 link up
rk-pcie 2a210000.pcie: Scanning root bridge failed
rk-pcie 2a210000.pcie: failed to initialize host
Fixes: d4b9fc2af45d ("arm64: dts: rockchip: Add rk3576 pcie nodes")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://lore.kernel.org/r/1748918140-212263-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -615,7 +615,7 @@
<0 0 0 2 &pcie1_intc 1>,
<0 0 0 3 &pcie1_intc 2>,
<0 0 0 4 &pcie1_intc 3>;
- linux,pci-domain = <0>;
+ linux,pci-domain = <1>;
max-link-speed = <2>;
num-ib-windows = <8>;
num-viewport = <8>;

41
target/linux/rockchip/patches-6.12/050-20-v6.17-arm64-dts-rockchip-add-SDIO-controller-on-RK3576.patch Normal file
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@ -0,0 +1,41 @@
From e490f854b46369b096f3d09c0c6a00f340425136 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Sat, 14 Jun 2025 22:14:34 +0400
Subject: [PATCH] arm64: dts: rockchip: add SDIO controller on RK3576
RK3576 has one more SD/MMC controller than are currently listed in its
.dtsi, with the missing one intended as an SDIO controller. Add the
missing node (tested with the onboard WiFi module on ArmSoM Sige5 v1.2)
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20250614-sige5-updates-v2-2-3bb31b02623c@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1695,6 +1695,22 @@
status = "disabled";
};
+ sdio: mmc@2a320000 {
+ compatible = "rockchip,rk3576-dw-mshc";
+ reg = <0x0 0x2a320000 0x0 0x4000>;
+ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>;
+ pinctrl-names = "default";
+ power-domains = <&power RK3576_PD_SDGMAC>;
+ resets = <&cru SRST_H_SDIO>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
sdhci: mmc@2a330000 {
compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
reg = <0x0 0x2a330000 0x0 0x10000>;

32
target/linux/rockchip/patches-6.12/050-21-v6.17-arm64-dts-rockchip-Enable-HDMI-PHY-clk-provider-on-rk3576.patch Normal file
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@ -0,0 +1,32 @@
From aba7987a536cee67fb0cb724099096fd8f8f5350 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Thu, 12 Jun 2025 00:47:48 +0300
Subject: [PATCH] arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576
As with the RK3588 SoC, the HDMI PHY PLL on RK3576 can be used as a more
accurate pixel clock source for VOP2, which is actually mandatory to
ensure proper support for display modes handling.
Add the missing #clock-cells property to allow using the clock provider
functionality of HDMI PHY.
Fixes: ad0ea230ab2a ("arm64: dts: rockchip: Add hdmi for rk3576")
Cc: stable@vger.kernel.org
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-2-4b11007d8675@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -2407,6 +2407,7 @@
reg = <0x0 0x2b000000 0x0 0x2000>;
clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>;
clock-names = "ref", "apb";
+ #clock-cells = <0>;
resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
<&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
reset-names = "apb", "init", "cmn", "lane";

53
target/linux/rockchip/patches-6.12/050-22-v6.17-arm64-dts-rockchip-Add-HDMI-PHY-PLL-clock-source-to-VOP2.patch Normal file
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@ -0,0 +1,53 @@
From 4ab8b8ac952fb08d03655e1da0cfee07589e428f Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Thu, 12 Jun 2025 00:47:49 +0300
Subject: [PATCH] arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2
on rk3576
Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS
char rate via phy_configure_opts_hdmi"), the workaround of passing the
rate from DW HDMI QP bridge driver via phy_set_bus_width() became
partially broken, as it cannot reliably handle mode switches anymore.
Attempting to fix this up at PHY level would not only introduce
additional hacks, but it would also fail to adequately resolve the
display issues that are a consequence of the system CRU limitations.
Instead, proceed with the solution already implemented for RK3588: make
use of the HDMI PHY PLL as a better suited DCLK source for VOP2. This
will not only address the aforementioned problem, but it should also
facilitate the proper operation of display modes up to 4K@60Hz.
It's worth noting that anything above 4K@30Hz still requires high TMDS
clock ratio and scrambling support, which hasn't been mainlined yet.
Fixes: d74b842cab08 ("arm64: dts: rockchip: Add vop for rk3576")
Cc: stable@vger.kernel.org
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-By: Detlev Casanova <detlev.casanova@collabora.com>
Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-3-4b11007d8675@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1155,12 +1155,14 @@
<&cru HCLK_VOP>,
<&cru DCLK_VP0>,
<&cru DCLK_VP1>,
- <&cru DCLK_VP2>;
+ <&cru DCLK_VP2>,
+ <&hdptxphy>;
clock-names = "aclk",
"hclk",
"dclk_vp0",
"dclk_vp1",
- "dclk_vp2";
+ "dclk_vp2",
+ "pll_hdmiphy0";
iommus = <&vop_mmu>;
power-domains = <&power RK3576_PD_VOP>;
rockchip,grf = <&sys_grf>;

269
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@ -0,0 +1,269 @@
From 15e8ba9d8b14ae6de415186622379f5f4dcfd141 Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Tue, 10 Jun 2025 14:32:42 +0200
Subject: [PATCH] arm64: dts: rockchip: Add thermal nodes to RK3576
Add the TSADC node to the RK3576. Additionally, add everything the TSADC
needs to function, i.e. thermal zones, their trip points and maps, as
well as adjust the CPU cooling-cells property.
The polling-delay properties are set to 0 as we do have interrupts for
this TSADC on this particular SoC, though the polling-delay-passive
properties are set to 100 for the thermal zones that have a passive
cooling device, as otherwise the thermal throttling behaviour never
unthrottles.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-6-b6e9efbf1015@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 164 ++++++++++++++++++++++-
1 file changed, 162 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/power/rockchip,rk3576-power.h>
#include <dt-bindings/reset/rockchip,rk3576-cru.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3576";
@@ -113,9 +114,9 @@
capacity-dmips-mhz = <485>;
clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
- #cooling-cells = <2>;
dynamic-power-coefficient = <120>;
cpu-idle-states = <&CPU_SLEEP>;
+ #cooling-cells = <2>;
};
cpu_l1: cpu@1 {
@@ -127,6 +128,7 @@
clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
+ #cooling-cells = <2>;
};
cpu_l2: cpu@2 {
@@ -138,6 +140,7 @@
clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
+ #cooling-cells = <2>;
};
cpu_l3: cpu@3 {
@@ -149,6 +152,7 @@
clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
+ #cooling-cells = <2>;
};
cpu_b0: cpu@100 {
@@ -159,9 +163,9 @@
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
- #cooling-cells = <2>;
dynamic-power-coefficient = <320>;
cpu-idle-states = <&CPU_SLEEP>;
+ #cooling-cells = <2>;
};
cpu_b1: cpu@101 {
@@ -173,6 +177,7 @@
clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
+ #cooling-cells = <2>;
};
cpu_b2: cpu@102 {
@@ -184,6 +189,7 @@
clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
+ #cooling-cells = <2>;
};
cpu_b3: cpu@103 {
@@ -195,6 +201,7 @@
clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
+ #cooling-cells = <2>;
};
idle-states {
@@ -520,6 +527,143 @@
method = "smc";
};
+ thermal_zones: thermal-zones {
+ /* sensor near the center of the SoC */
+ package_thermal: package-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ package_crit: package-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ /* sensor for cluster1 (big Cortex-A72 cores) */
+ bigcore_thermal: bigcore-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 1>;
+
+ trips {
+ bigcore_alert: bigcore-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ bigcore_crit: bigcore-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&bigcore_alert>;
+ cooling-device =
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ /* sensor for cluster0 (little Cortex-A53 cores) */
+ littlecore_thermal: littlecore-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 2>;
+
+ trips {
+ littlecore_alert: littlecore-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ littlecore_crit: littlecore-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&littlecore_alert>;
+ cooling-device =
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 3>;
+
+ trips {
+ gpu_alert: gpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu_crit: gpu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert>;
+ cooling-device =
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ npu_thermal: npu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 4>;
+
+ trips {
+ npu_crit: npu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr_thermal: ddr-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 5>;
+
+ trips {
+ ddr_crit: ddr-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
@@ -2303,6 +2447,22 @@
status = "disabled";
};
+ tsadc: tsadc@2ae70000 {
+ compatible = "rockchip,rk3576-tsadc";
+ reg = <0x0 0x2ae70000 0x0 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ assigned-clocks = <&cru CLK_TSADC>;
+ assigned-clock-rates = <2000000>;
+ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
+ reset-names = "tsadc-apb", "tsadc";
+ #thermal-sensor-cells = <1>;
+ rockchip,hw-tshut-temp = <120000>;
+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+ };
+
i2c9: i2c@2ae80000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2ae80000 0x0 0x1000>;

91
target/linux/rockchip/patches-6.12/050-24-v6.17-arm64-dts-rockchip-Add-thermal-trim-OTP-and-tsadc-nodes.patch Normal file
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@ -0,0 +1,91 @@
From a4053badacf3699023527392c947314b074f5e0e Mon Sep 17 00:00:00 2001
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: Tue, 10 Jun 2025 14:32:43 +0200
Subject: [PATCH] arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes
Thanks to Heiko's work getting OTP working on the RK3576, we can specify
the thermal sensor trim values which are stored there now, and with my
driver addition to rockchip_thermal, we can make use of these.
Add them to the devicetree for the SoC.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-7-b6e9efbf1015@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 57 ++++++++++++++++++++++++
1 file changed, 57 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1937,6 +1937,30 @@
log_leakage: log-leakage@22 {
reg = <0x22 0x1>;
};
+ bigcore_tsadc_trim: bigcore-tsadc-trim@24 {
+ reg = <0x24 0x2>;
+ bits = <0 10>;
+ };
+ litcore_tsadc_trim: litcore-tsadc-trim@26 {
+ reg = <0x26 0x2>;
+ bits = <0 10>;
+ };
+ ddr_tsadc_trim: ddr-tsadc-trim@28 {
+ reg = <0x28 0x2>;
+ bits = <0 10>;
+ };
+ npu_tsadc_trim: npu-tsadc-trim@2a {
+ reg = <0x2a 0x2>;
+ bits = <0 10>;
+ };
+ gpu_tsadc_trim: gpu-tsadc-trim@2c {
+ reg = <0x2c 0x2>;
+ bits = <0 10>;
+ };
+ soc_tsadc_trim: soc-tsadc-trim@64 {
+ reg = <0x64 0x2>;
+ bits = <0 10>;
+ };
};
sai0: sai@2a600000 {
@@ -2461,6 +2485,39 @@
rockchip,hw-tshut-temp = <120000>;
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@0 {
+ reg = <0>;
+ nvmem-cells = <&soc_tsadc_trim>;
+ nvmem-cell-names = "trim";
+ };
+ sensor@1 {
+ reg = <1>;
+ nvmem-cells = <&bigcore_tsadc_trim>;
+ nvmem-cell-names = "trim";
+ };
+ sensor@2 {
+ reg = <2>;
+ nvmem-cells = <&litcore_tsadc_trim>;
+ nvmem-cell-names = "trim";
+ };
+ sensor@3 {
+ reg = <3>;
+ nvmem-cells = <&ddr_tsadc_trim>;
+ nvmem-cell-names = "trim";
+ };
+ sensor@4 {
+ reg = <4>;
+ nvmem-cells = <&npu_tsadc_trim>;
+ nvmem-cell-names = "trim";
+ };
+ sensor@5 {
+ reg = <5>;
+ nvmem-cells = <&gpu_tsadc_trim>;
+ nvmem-cell-names = "trim";
+ };
};
i2c9: i2c@2ae80000 {

52
target/linux/rockchip/patches-6.12/050-25-v6.17-arm64-dts-rockchip-add-mipi-dcphy-to-rk3576.patch Normal file
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@ -0,0 +1,52 @@
From 21bc1a7fcea4635a49f6b2eff3e4c661e80e8f43 Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Mon, 7 Jul 2025 18:49:03 +0200
Subject: [PATCH] arm64: dts: rockchip: add mipi-dcphy to rk3576
Add the MIPI-DC-phy node to the RK3576, that will be used by the one
DSI2 controller and hopefully in some future also for camera input.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250707164906.1445288-11-heiko@sntech.de
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -966,6 +966,12 @@
reg = <0x0 0x26032000 0x0 0x100>;
};
+ mipidcphy_grf: syscon@26034000 {
+ compatible = "rockchip,rk3576-dcphy-grf", "syscon";
+ reg = <0x0 0x26034000 0x0 0x2000>;
+ clocks = <&cru PCLK_PMUPHY_ROOT>;
+ };
+
vo1_grf: syscon@26036000 {
compatible = "rockchip,rk3576-vo1-grf", "syscon";
reg = <0x0 0x26036000 0x0 0x100>;
@@ -2563,6 +2569,22 @@
status = "disabled";
};
+ mipidcphy: phy@2b020000 {
+ compatible = "rockchip,rk3576-mipi-dcphy";
+ reg = <0x0 0x2b020000 0x0 0x10000>;
+ clocks = <&cru PCLK_MIPI_DCPHY>,
+ <&cru CLK_PHY_REF_SRC>;
+ clock-names = "pclk", "ref";
+ resets = <&cru SRST_M_MIPI_DCPHY>,
+ <&cru SRST_P_MIPI_DCPHY>,
+ <&cru SRST_P_DCPHY_GRF>,
+ <&cru SRST_S_MIPI_DCPHY>;
+ reset-names = "m_phy", "apb", "grf", "s_phy";
+ rockchip,grf = <&mipidcphy_grf>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
combphy0_ps: phy@2b050000 {
compatible = "rockchip,rk3576-naneng-combphy";
reg = <0x0 0x2b050000 0x0 0x100>;

53
target/linux/rockchip/patches-6.12/050-26-v6.17-arm64-dts-rockchip-add-the-dsi-controller-to-rk3576.patch Normal file
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@ -0,0 +1,53 @@
From e51828f80df99a2899e263b750cada6426f14c92 Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Mon, 7 Jul 2025 18:49:04 +0200
Subject: [PATCH] arm64: dts: rockchip: add the dsi controller to rk3576
The RK3576 comes with one DSI2 controllers based on the same newer
Synopsis IP as the ones on the RK3588.
Add the necessary node for it.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250707164906.1445288-12-heiko@sntech.de
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 28 ++++++++++++++++++++++++
1 file changed, 28 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1389,6 +1389,34 @@
status = "disabled";
};
+ dsi: dsi@27d80000 {
+ compatible = "rockchip,rk3576-mipi-dsi2";
+ reg = <0x0 0x27d80000 0x0 0x10000>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
+ clock-names = "pclk", "sys";
+ power-domains = <&power RK3576_PD_VO0>;
+ resets = <&cru SRST_P_DSIHOST0>;
+ reset-names = "apb";
+ phys = <&mipidcphy PHY_TYPE_DPHY>;
+ phy-names = "dcphy";
+ rockchip,grf = <&vo0_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_in: port@0 {
+ reg = <0>;
+ };
+
+ dsi_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
hdmi: hdmi@27da0000 {
compatible = "rockchip,rk3576-dw-hdmi-qp";
reg = <0x0 0x27da0000 0x0 0x20000>;

25
target/linux/rockchip/patches-6.12/050-27-v6.17-arm64-dts-rockchip-Enable-RK3576-watchdog.patch Normal file
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@ -0,0 +1,25 @@
From 9c059700fee595142676a9bbaff6e40e3fcd9cbb Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Mon, 18 Aug 2025 19:18:40 +0200
Subject: [PATCH] arm64: dts: rockchip: Enable RK3576 watchdog
The RK3576 watchdog does not need any board specific resources, so
let's enable it by default just like we do for RK3588.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250818-rk3576-watchdog-v1-1-28f82e01029c@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 -
1 file changed, 1 deletion(-)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -2275,7 +2275,6 @@
clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
clock-names = "tclk", "pclk";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
};
spi0: spi@2acf0000 {